CN117153775A - Preparation method of semiconductor structure - Google Patents
Preparation method of semiconductor structure Download PDFInfo
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- CN117153775A CN117153775A CN202311114026.4A CN202311114026A CN117153775A CN 117153775 A CN117153775 A CN 117153775A CN 202311114026 A CN202311114026 A CN 202311114026A CN 117153775 A CN117153775 A CN 117153775A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 230000000903 blocking effect Effects 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
Abstract
The invention provides a preparation method of a semiconductor structure, which comprises the steps of forming a first dielectric layer and a blocking structure on the surface of a metal layer, wherein the blocking structure is positioned right above a fuse part in the metal layer; forming a conductive column, a bonding pad, a second dielectric layer and a patterned first photoresist layer, etching to form a first opening and a second opening based on the patterned first photoresist layer, wherein the first opening exposes the blocking structure, and the second opening exposes the bonding pad; finally, the blocking structure is removed, and oxide with uniform thickness is formed above the fuse wire part. The invention can ensure that the oxide above the fuse wire part reaches the preset thickness by controlling the process of thinning the first dielectric layer, and can ensure that the oxide above the fuse wire part is better reserved due to the existence of the blocking structure, and the oxide with uniform thickness after thinning is obtained above the fuse wire part; in addition, the bonding pad and the fuse skylight are simultaneously opened by one-time exposure and development, so that compared with the traditional process, the invention has the advantages that the photoetching layer number is not increased, and the cost is controllable.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to a preparation method of a semiconductor structure.
Background
BCD (Bipolar CMOSDMOS) is a monolithic integrated process technology that enables bipolar transistors (Bipolar transistor), CMOS (Complementary Metal Oxide Semiconductor), and DMOS (Double Diffused MOS) to be fabricated on the same chip, and is widely used in wireless chargers, power over ethernet, USB power transfer controllers, smart devices, automobiles, electric bicycles, data centers, and the like.
In general, in the fabrication of an extraction structure using a chip manufactured by BCD process of 0.15 μm or more, a Metal Fuse (Fuse) structure uses a lower Metal layer located at a lower layer of a top Metal. In the process of etching the bonding Pad (Pad ET), an overetching process exists in order to ensure that the bonding Pad is opened, but in the process of etching the bonding Pad, the metal fuse is easily exposed in the air, so that oxides are formed on the surface of the metal fuse to influence the subsequent encapsulation trimming of the chip. To avoid this, it is common to open the fuse skylight by a process of one-shot exposure development after opening the bonding pad, leaving a certain oxide over the metal fuse. However, due to the small area of the metal fuse, the etching rate is not uniform in the process of opening the fuse skylight, so that the thickness of oxide above the metal fuse is not uniform, the accuracy of subsequent laser trimming is affected, and the chip is disabled.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor structure, in which a first dielectric layer and a blocking structure are sequentially formed on a surface of a metal layer, and the blocking structure is located right above a fuse portion in the metal layer; forming a conductive column, a bonding pad, a second dielectric layer and a patterned first photoresist layer, etching to form a first opening and a second opening based on the patterned first photoresist layer, wherein the first opening exposes the blocking structure, and the second opening exposes the bonding pad; finally, the blocking structure is removed, and oxide with uniform thickness is formed above the fuse wire part. In the preparation method of the semiconductor structure, the oxide above the fuse wire part can reach the preset thickness by controlling the process of thinning the first dielectric layer, and the blocking structure is etched after the second dielectric layer is etched due to the existence of the blocking structure, so that the oxide above the fuse wire part can be well reserved, and the oxide with uniform thickness after thinning is obtained above the fuse wire part; in addition, the bonding pad and the fuse skylight are simultaneously opened by one-time exposure and development, so that compared with the traditional process, the invention has the advantages that the photoetching layer number is not increased, and the cost is controllable.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the steps of:
providing a substrate, sequentially forming a metal layer and a first dielectric layer on the substrate, wherein the metal layer comprises lead parts and fuse parts which are positioned in different areas on the same horizontal plane, and the first dielectric layer covers the substrate and the metal layer;
thinning the first dielectric layer until the surface of the first dielectric layer is flush, wherein the thickness of the first dielectric layer positioned on the surface of the metal layer is a preset thickness;
forming a blocking structure on the surface of the first dielectric layer, wherein the blocking structure is positioned above the fuse wire part;
forming a conductive post, a bonding pad and a second dielectric layer above the structure, wherein the conductive post is positioned on the surface of the lead part, the bonding pad is positioned on the surface of the conductive post, and the second dielectric layer covers the structure;
and forming a patterned first photoresist layer on the surface of the second dielectric layer, and forming a first opening and a second opening in the second dielectric layer based on the patterned first photoresist layer, wherein the first opening exposes the blocking structure, and the second opening exposes the bonding pad.
Optionally, the predetermined thickness is between
Optionally, the method of thinning the first dielectric layer includes chemical mechanical polishing.
Optionally, forming a blocking structure on the surface of the first dielectric layer includes:
sequentially forming a barrier layer and a patterned second photoresist layer on the surface of the first dielectric layer;
etching the barrier layer based on the patterned second photoresist layer to form the barrier structure above the fuse portion;
and removing the patterned second photoresist layer.
Optionally, the thickness of the barrier layer is between
Optionally, the material of the blocking layer includes one of silicon nitride and silicon oxynitride.
Optionally, the bonding pad is over-etched in the process of forming the second opening.
Optionally, the first opening and the second opening are formed by a dry etching method.
Optionally, after forming the first opening and the second opening, the method further includes: and removing the blocking structure.
Optionally, after removing the blocking structure, the method further includes: and removing the patterned first photoresist layer.
The preparation method of the semiconductor structure provided by the invention has at least the following beneficial effects:
in the preparation method of the semiconductor structure, the oxide above the fuse wire part can reach the preset thickness by controlling the process of thinning the first dielectric layer, and the blocking structure is etched after the second dielectric layer is etched due to the existence of the blocking structure, so that the oxide above the fuse wire part can be well reserved, and the oxide with uniform thickness after thinning is obtained above the fuse wire part; in addition, the bonding pad and the fuse skylight are simultaneously opened by one-time exposure and development, so that compared with the traditional process, the invention has the advantages that the photoetching layer number is not increased, and the cost is controllable.
Drawings
Fig. 1 is a flow chart showing a method for manufacturing a semiconductor structure according to an embodiment.
Fig. 2 is a schematic diagram showing the structure obtained in step S1 in the embodiment.
Fig. 3 is a top view of a metal layer in an embodiment.
Fig. 4 is a schematic diagram showing the structure obtained in step S2 in the embodiment.
Fig. 5 is a schematic diagram showing the structure obtained in step S3 in the embodiment.
Fig. 6 is a schematic diagram showing the structure obtained in step S4 in the embodiment.
Fig. 7 to 10 are schematic views showing the structure obtained in step S5 in the examples.
Description of element reference numerals
10. Substrate and method for manufacturing the same
20. Metal layer
21. Lead part
22. Fuse part
31. A first dielectric layer
32. Second dielectric layer
321. A first opening
322. A second opening
40. Barrier layer
400. Barrier structure
51. First photoresist layer
52. Second photoresist layer
60. Conductive column
70. Bonding pad
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment only illustrate the basic concept of the present invention by way of illustration, but only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number, positional relationship and proportion of each component in actual implementation may be changed at will on the premise of implementing the present technical solution, and the layout of the components may be more complex.
Examples
The embodiment provides a method for preparing a semiconductor structure, as shown in fig. 1, including the following steps:
s1: providing a substrate, sequentially forming a metal layer and a first dielectric layer on the substrate, wherein the metal layer comprises lead parts and fuse parts which are positioned in different areas on the same horizontal plane, and the first dielectric layer covers the substrate and the metal layer;
as shown in fig. 2, a substrate 10 is provided, and the substrate 10 may be made of one of monocrystalline silicon, polycrystalline silicon and amorphous silicon, and a semiconductor device (not shown in the figure) is formed in the substrate 10, for example, one or a combination of bipolar transistor, CMOS and DMOS. In the present embodiment, bipolar transistors, CMOS, and DMOS are integrated in the substrate 10.
Next, a metal layer 20 is formed on the surface of the substrate 10, and as shown in fig. 2 and 3, the metal layer 20 includes a lead portion 21 and a fuse portion 22 located in different areas on the same horizontal plane. As an example, the material of the metal layer 20 may be one of copper, copper alloy, aluminum, and aluminum alloy.
Next, a first dielectric layer 31 is formed on the surface of the structure, and the first dielectric layer 31 covers the substrate 10 and the metal layer 20. As an example, the material of the first dielectric layer 31 is oxide, and in this embodiment, the first dielectric layer 31 is made of silicon oxide.
S2: thinning the first dielectric layer until the surface of the first dielectric layer is flush, wherein the thickness of the first dielectric layer positioned on the surface of the metal layer is a preset thickness;
as shown in fig. 4, the first dielectric layer 31 is thinned to be flush with its surface. By way of example, the method of thinning the first dielectric layer 31 includes chemical mechanical polishing or other suitable method.
As an example, the thickness d of the first dielectric layer 31 on the surface of the metal layer 20 is a preset thickness, which is set according to actual needs, and the thickness d of the first dielectric layer 31 on the surface of the metal layer 20 can be made to reach the preset thickness by controlling the thinning process. In this embodiment, the predetermined thickness is betweenPreferably->
S3: forming a blocking structure on the surface of the first dielectric layer, wherein the blocking structure is positioned above the fuse wire part;
first, as shown in fig. 4, a barrier layer 40 is formed on the surface of the first dielectric layer 31. As an example, the material of the barrier layer 40 includes one of silicon nitride and silicon oxynitride, and in this embodiment, the material of the barrier layer 40 is silicon oxynitride; the thickness of the barrier layer 40 is betweenPreferably +.>
Next, a second photoresist layer 52 is formed on the surface of the barrier layer 40, and a patterned second photoresist layer 52 is formed by using an exposure and development technique, and as shown in fig. 4, the patterned second photoresist layer 52 is located directly above the fuse portion 22.
Next, the barrier layer 40 is etched based on the patterned second photoresist layer 52, as shown in fig. 5, thereby forming a barrier structure 400 over the fuse portion 22.
Finally, the patterned second photoresist layer 52 is removed.
S4: forming a conductive post, a bonding pad and a second dielectric layer above the structure obtained in the step S3, wherein the conductive post is positioned on the surface of the lead part, the bonding pad is positioned on the surface of the conductive post, and the second dielectric layer covers the structure;
first, depositing a portion of the second dielectric layer 32 on the surface of the structure obtained in step S3; next, a through hole penetrating the first dielectric layer 31 and the second dielectric layer 32 is formed, and the through hole is located on the surface of the lead portion 21; next, filling a conductive material in the through hole to form a conductive post 60; next, a metal layer is deposited on the surface of the conductive post 60 to form a pad 70; finally, another portion of the second dielectric layer 32 is deposited on the surface of the structure, so that the second dielectric layer 32 covers the structure, and the structure shown in fig. 6 is formed.
By way of example, the conductive post 60 may be made of one of copper, aluminum, nickel, gold, silver, and titanium, or any other suitable conductive material. As an example, the conductive pillars 60 have a height in the range ofThat is, the distance from the lower surface of the pad 70 to the upper surface of the lead portion 21 is in the range +.>In the present embodiment, the height of the conductive pillar 60 is +.>The cross-sectional dimension of the conductive pillars 60 perpendicular to the height direction may be selected according to practical conditions while securing device performance, and is not limited herein.
By way of example, the material of the pad 70 may include one of copper, aluminum, nickel, gold, silver, and titanium, or other suitable conductive material. The size of the pad 70 may be selected according to the actual situation, without limitation, while securing the device performance.
As an example, the second dielectric layer 32 is made of the same material as the first dielectric layer 31, and is made of an oxide material, and in this embodiment, the second dielectric layer 32 is made of a silicon oxide material. The thickness of the second dielectric layer 32 may be selected according to practical situations, without limitation, while ensuring that the thickness of the second dielectric layer 32 is greater than the sum of the thickness of the pad 70 and the height of the conductive post 60. The upper surface of the second dielectric layer 32 located above the pad 70 protrudes from the upper surface of the second dielectric layer 32 around the pad 70 by a height equal to the thickness of the pad 70, where the thickness refers to the distance between the upper surface of the pad 70 and the lower surface of the pad 70. The distance of the upper surface of the pad 70 from the upper surface of the second dielectric layer 32 may be set according to practical situations, and is not limited herein.
S5: and forming a patterned first photoresist layer on the surface of the second dielectric layer, and forming a first opening and a second opening in the second dielectric layer based on the patterned first photoresist layer, wherein the first opening exposes the blocking structure, and the second opening exposes the bonding pad.
First, as shown in fig. 7, a first photoresist layer 51 is formed on the surface of the second dielectric layer 32; next, a patterned first photoresist layer 51 is formed using an exposure and development technique, as shown in fig. 8, the patterned first photoresist layer 51 reveals an upper surface of the second dielectric layer 32 over the pad 70, and an upper surface of the second dielectric layer 32 over the barrier structure 400.
Next, the second dielectric layer 32 is etched based on the patterned first photoresist layer 51, as shown in fig. 9, so that a first opening 321 and a second opening 322 are formed in the second dielectric layer 32, and the first opening 321 exposes the blocking structure 400 and the second opening 322 exposes the pad 70. As an example, the method of forming the first and second openings 321 and 322 includes dry etching, but other suitable methods are also possible. Over-etching the pad 70 during the formation of the second opening 322 to ensure that the pad 70 is opened, i.e., the second dielectric layer 32 covering the upper surface of the pad 70 is completely removed; during the over etching of the second opening 322, the bottom of the first opening 321 is simultaneously etched. In addition, in the process of etching the second dielectric layer 32, an etching gas with a large etching selectivity to the second dielectric layer 32 and a small etching selectivity to the barrier structure 400 is selected, so that the bottom surface of the first opening 321 is the surface of the barrier structure 400.
Next, the barrier structure 400 is removed by dry etching. In the process of etching to remove the barrier structure 400, an etching gas having a large selection ratio to the barrier structure 400 and a small selection ratio to the first dielectric layer 31 and the second dielectric layer 32 is selected to ensure that a dielectric layer having a predetermined thickness can be maintained on the surface of the fuse portion. As shown in fig. 10, in the resulting semiconductor structure, a certain thickness of oxide remains over the fuse portion 22, so that oxidation of the fuse portion 22 when exposed to air can be avoided; the thickness of the oxide above the fuse portion 22 is the preset thickness d in step S2, and the surface of the oxide above the fuse portion 22 is always covered by the barrier structure 400 to protect the same in the etching process of steps S2 to S5, and the oxide at the bottom of the barrier structure 400 is better preserved in the etching process of removing the barrier structure 400, so that the thickness of the oxide above the fuse portion 22 is uniform.
Finally, the patterned first photoresist layer 51 is removed, and the semiconductor structure after the patterned first photoresist layer 51 is removed is shown in fig. 10. As an example, the patterned first photoresist layer 51 may be washed away with a photoresist stripper, and the patterned first photoresist layer 51 may be removed by other suitable methods.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate, sequentially forming a metal layer and a first dielectric layer on the substrate, wherein the metal layer comprises lead parts and fuse parts which are positioned in different areas on the same horizontal plane, and the first dielectric layer covers the substrate and the metal layer;
thinning the first dielectric layer until the surface of the first dielectric layer is flush, wherein the thickness of the first dielectric layer positioned on the surface of the metal layer is a preset thickness;
forming a blocking structure on the surface of the first dielectric layer, wherein the blocking structure is positioned above the fuse wire part;
forming a conductive post, a bonding pad and a second dielectric layer above the structure, wherein the conductive post is positioned on the surface of the lead part, the bonding pad is positioned on the surface of the conductive post, and the second dielectric layer covers the structure;
and forming a patterned first photoresist layer on the surface of the second dielectric layer, and forming a first opening and a second opening in the second dielectric layer based on the patterned first photoresist layer, wherein the first opening exposes the blocking structure, and the second opening exposes the bonding pad.
2. The method of claim 1, wherein the predetermined thickness is between
3. The method of claim 1, wherein the thinning the first dielectric layer comprises chemical mechanical polishing.
4. The method of claim 1, wherein forming a barrier structure on a surface of the first dielectric layer comprises:
sequentially forming a barrier layer and a patterned second photoresist layer on the surface of the first dielectric layer;
etching the barrier layer based on the patterned second photoresist layer to form the barrier structure above the fuse portion;
and removing the patterned second photoresist layer.
5. The method of claim 4, wherein the barrier layer has a thickness between
6. The method of claim 4, wherein the barrier layer comprises one of silicon nitride and silicon oxynitride.
7. The method of manufacturing a semiconductor structure according to claim 1, wherein the bonding pad is over-etched during the forming of the second opening.
8. The method of manufacturing a semiconductor structure according to claim 1, wherein the first opening and the second opening are formed by dry etching.
9. The method of manufacturing a semiconductor structure of claim 1, further comprising, after forming the first opening and the second opening: and removing the blocking structure.
10. The method of fabricating a semiconductor structure of claim 9, further comprising, after removing the barrier structure: and removing the patterned first photoresist layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311114026.4A CN117153775A (en) | 2023-08-30 | 2023-08-30 | Preparation method of semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311114026.4A CN117153775A (en) | 2023-08-30 | 2023-08-30 | Preparation method of semiconductor structure |
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| Publication Number | Publication Date |
|---|---|
| CN117153775A true CN117153775A (en) | 2023-12-01 |
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| CN202311114026.4A Pending CN117153775A (en) | 2023-08-30 | 2023-08-30 | Preparation method of semiconductor structure |
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| CN (1) | CN117153775A (en) |
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