CN117080247A - Gallium nitride heterojunction field effect transistor, manufacturing method and electronic equipment - Google Patents

Gallium nitride heterojunction field effect transistor, manufacturing method and electronic equipment Download PDF

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Publication number
CN117080247A
CN117080247A CN202311309023.6A CN202311309023A CN117080247A CN 117080247 A CN117080247 A CN 117080247A CN 202311309023 A CN202311309023 A CN 202311309023A CN 117080247 A CN117080247 A CN 117080247A
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layer
field plate
gallium nitride
gate
gate field
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张紫淇
陈昌禧
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Honor Device Co Ltd
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Honor Device Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The embodiment of the application provides a gallium nitride heterojunction field effect transistor, a manufacturing method and electronic equipment, and relates to the technical field of semiconductors. The gallium nitride heterojunction field effect transistor solves the problem that proper threshold voltage and low on-resistance cannot be achieved simultaneously, and the problem that gate leakage current is large. The gallium nitride heterojunction field effect transistor includes: the barrier layer comprises a groove, a first part and a second part which are respectively arranged at two sides of the groove, and two-dimensional electron gas is formed on an interface where the channel layer is respectively contacted with the first part and the second part. The first drain electrode is arranged on one side of the first part far away from the channel layer. And the second drain electrode is arranged on one side of the second part far away from the channel layer. The first dielectric layer is at least arranged on the inner surface of the groove. The grid is arranged in the groove.

Description

Gallium nitride heterojunction field effect transistor, manufacturing method and electronic equipment
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a gallium nitride heterojunction field effect transistor, a manufacturing method thereof, and an electronic device.
Background
With the development of technology, portable mobile terminals are increasingly miniaturized and thinned. For a portable mobile terminal having both a wired charging function and a wireless charging function, a bidirectional on-off module should be respectively provided at a wired charging input end and a wireless charging input end of a circuit board thereof, and in order to save a circuit board space of the portable mobile terminal, a transistor having two drains may be used as the bidirectional on-off module.
When the transistor is required to be turned on, a voltage value higher than a threshold voltage is required to be applied between the gate and the drain, so that a conductive channel is established between the barrier layer and the channel layer, and a loop in which the transistor is located is turned on through the conductive channel. The transistor in the related art often has the problem that the suitable threshold voltage and the low on-resistance cannot be achieved, and the problem that the gate leakage current is large is needed to be solved.
Disclosure of Invention
In order to solve the technical problems, the application provides a gallium nitride heterojunction field effect transistor, a manufacturing method and electronic equipment, which can solve the problem that proper threshold voltage and low on-resistance cannot be achieved simultaneously, and the problem that gate leakage current is larger.
In a first aspect, the present application provides a gallium nitride heterojunction field effect transistor comprising: the channel layer is made of gallium nitride; the barrier layer is arranged on one side of the channel layer, the barrier layer comprises a groove, and a first part and a second part which are respectively arranged on two sides of the groove, the groove at least comprises a first opening, the opening direction of the first opening deviates from the direction of the channel layer, and two-dimensional electron gas is formed on the interface of the channel layer, which is respectively contacted with the first part and the second part; the first drain electrode is arranged on one side of the first part far away from the channel layer, and the first drain electrode is made of conductive materials; the second drain electrode is arranged on one side of the second part far away from the channel layer, and the second drain electrode is made of conductive materials; the first dielectric layer is at least arranged on the inner surface of the groove, and the first dielectric layer is made of insulating materials; the grid is arranged in the groove, and the grid is made of conductive materials.
The barrier layer of the transistor is provided with a groove which cuts off two-dimensional electron gas of the first part and the second part of the barrier layer, so that a conductive channel cannot be easily established, and the threshold voltage can be kept at a higher level. Therefore, even if the channel layer is kept thick, excessive drop of the threshold voltage is not caused. The thicker the barrier layer is, the higher the concentration of the two-dimensional electron gas is, and the smaller the on-resistance is. The arrangement mode ensures the concentration of the two-dimensional electron gas of the barrier layer, so that the on-resistance of the transistor is lower, and the threshold voltage is not too low. And because the first dielectric layer is arranged between the grid electrode and the semiconductor material, the first dielectric layer can block the current between the grid electrode made of metal material and the semiconductor material layer, so that the grid leakage current is greatly reduced.
In some possible implementations, the barrier layer is made of Al y Ga 1-y And N, wherein Al is aluminum, ga is gallium, N is nitrogen, and y is more than 0 and less than or equal to 1. The material of the barrier layer can be flexibly determined according to actual needs, and the electric performance of the transistor can be conveniently adjusted through adjustment of the material.
In some possible implementations, the material of the first dielectric layer includes silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide, or hafnium oxide. The material of the first dielectric layer can be flexibly determined according to actual needs.
In some possible implementations, the depth of the recess is the same as the thickness of the barrier layer. The barrier layer at the groove can be completely dug, so that two-dimensional electron gas between the barrier layer and the channel layer is better blocked.
In some possible implementations, the semiconductor device further includes a first gate field plate, the first gate field plate is connected to the gate, two sides of the first gate field plate extend toward a direction in which the first drain electrode is located and a direction in which the second drain electrode is located, and a first dielectric layer is disposed between the first gate field plate and the barrier layer. The first grid electrode field plate can adjust electric field distribution between the grid electrode and the first drain electrode and between the grid electrode and the second drain electrode, and reduces electric field density of local parts of the grid electrode, so that breakdown between the grid electrode and the drain electrode caused by too dense local electric fields is avoided. The electric field is uniformly distributed, and the voltage-withstanding capability of the transistor is improved.
In some possible implementations, the device further includes a second dielectric layer and a second gate field plate, the second gate field plate is disposed opposite to the first gate field plate, a second dielectric layer is disposed between the second gate field plate and the first drain, the second drain, and the first gate field plate, and the second gate field plate, the first gate field plate, and the gate are all electrically connected. The second grid field plate is additionally added on the basis of the first grid field plate, so that electric field distribution between the grid and the drain can be more uniform, and the voltage withstanding capability of the transistor is further improved.
In some possible implementations, the material of the second dielectric layer includes silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide, or hafnium oxide. The material of the second dielectric layer can be flexibly determined according to actual needs.
In some possible implementations, a transition layer is further included, the transition layer being disposed on a side of the channel layer remote from the barrier layer. By arranging the transition layer, not only the inter-crystal stress caused by different crystal materials of the substrate and the channel layer can be released, but also the distance between the grid electrode and the substrate can be increased, so that the breakdown of the transistor is avoided.
In some possible implementations, the transition layer includes a transition layer body disposed on a side of the channel layer remote from the barrier layer and a nucleation layer disposed on a side of the transition layer body remote from the channel layer. By arranging the nucleation layer, the growth of the transition layer is facilitated.
In some possible implementations, the material of the transition layer body includes aluminum gallium nitride of graded aluminum composition, N-type gallium nitride, homogenous aluminum gallium nitride, or superlattice aluminum gallium nitride; the material of the nucleation layer comprises gallium nitride or aluminum nitride. The material of the transition layer can be flexibly determined according to actual needs, and the electric performance of the transistor can be conveniently adjusted through adjustment of the material.
In some possible implementations, the semiconductor device further includes a substrate disposed on a side of the transition layer remote from the channel layer. By arranging the substrate, the formation of the transistor is facilitated.
In a second aspect, a method for manufacturing a gallium nitride heterojunction field effect transistor is provided, for manufacturing any one of the gallium nitride heterojunction field effect transistors, including: preparing a channel layer; preparing a barrier layer on the channel layer; a groove is formed in a position corresponding to the grid electrode on one side of the barrier layer away from the channel layer; forming a first dielectric layer on the inner surface of the groove and one side of the barrier layer away from the channel layer; removing the first dielectric layer at the position corresponding to the first drain electrode and the second drain electrode; and forming a first drain electrode and a second drain electrode, and forming a grid electrode. The above-mentioned manufacturing method adopts a method of forming a film layer first and then removing unnecessary portions. The manufacturing cost can be reduced in the manufacturing process of each film layer, and the production efficiency is improved.
In some possible implementations, after forming the gate, forming the first gate field plate further includes forming the first gate field plate on a side having the gate. The formation of the gate and the formation of the first gate field plate may be completed in two steps, thereby conditionally improving the quality of the first gate field plate.
In some possible implementations, forming the first gate field plate on the side having the gate includes forming a photoresist on the side having the gate and exposing a region where the first gate field plate is to be formed, and forming the first gate field plate on the region where the first gate field plate is to be formed using a sputtering or evaporation process. The first gate field plate can be shaped into a desired shape by the occupation of the photoresist.
In some possible implementations, the method further includes forming a second dielectric layer on a side of the first gate field plate remote from the gate, and forming a second gate field plate on a side of the second dielectric layer remote from the first gate field plate.
In some possible implementations, forming the second gate field plate on a side of the second dielectric layer away from the first gate field plate includes forming a photoresist on a side of the second dielectric layer away from the first gate field plate, exposing a region where the second gate field plate is to be formed, and forming the second gate field plate using a sputtering or evaporation process on the region where the second gate field plate is to be formed. The second gate field plate can be shaped into a desired shape by the occupation of the photoresist and the second dielectric layer.
In some possible implementations, forming the recess includes forming a photoresist on a side of the barrier layer away from the channel layer, exposing a portion where the recess is to be formed, and etching a side of the barrier layer away from the channel layer to form the recess. Through the etching process, the grooves of the barrier layer can be formed into a required shape, the barrier layer does not need to be molded at one time, and the production cost is reduced.
In some possible implementations, removing the first dielectric layer at locations corresponding to the first drain electrode and the second drain electrode includes forming a photoresist on a side of the first dielectric layer remote from the channel layer and exposing portions of the first drain electrode and the second drain electrode to be formed. Through the etching process, the first dielectric layer can be formed into a required shape, and the first dielectric layer does not need to be molded at one time, so that the production cost is reduced.
In some possible implementations, before preparing the channel layer, further includes: obtaining a substrate; forming a nucleation layer on the surface of the substrate by a vapor phase epitaxy technique; a transition layer body is grown on a side of the nucleation layer remote from the substrate. The vapor phase epitaxy technology is more beneficial to the formation of crystal lattices, not only improves the crystal quality of the nucleation layer, but also improves the crystal quality of the transition layer body grown on the nucleation layer.
In a third aspect, an electronic device is provided that uses any of the gallium nitride heterojunction field effect transistors described above. Because the transistor is smaller, the occupied area on the PCB of the electronic equipment can be reduced, and the integration degree of the electronic equipment can be improved while the electrical performance of the electronic equipment is ensured.
Drawings
Fig. 1 is a schematic diagram of a front structure of an electronic device according to an embodiment of the present application;
fig. 2 is a schematic diagram of a reverse structure of an electronic device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a charging circuit provided in the related art;
fig. 4 is a schematic structural diagram of a high electron mobility transistor according to the related art;
FIG. 5 is a schematic diagram of a process for preparing a transition layer according to an embodiment of the present application;
fig. 6 is a schematic diagram of a process for preparing a channel layer according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a process for preparing a barrier layer according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a process for forming a groove according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a process for preparing a first dielectric layer according to an embodiment of the present application;
fig. 10 is a schematic diagram of a process for removing a portion of a first dielectric layer according to an embodiment of the present application;
fig. 11 is a schematic diagram of a process for preparing a first drain electrode and a second drain electrode according to an embodiment of the present application;
Fig. 12 is a schematic diagram of a process for preparing a gate according to an embodiment of the present application;
fig. 13 is a schematic diagram of a process for preparing a first gate field plate according to an embodiment of the present application;
fig. 14 is a schematic diagram of a process for preparing a second gate field plate and a second dielectric layer according to an embodiment of the present application;
fig. 15 is a schematic view of a device in a first scenario provided by an embodiment of the present application;
fig. 16 is a schematic structural diagram of a charging circuit in a second scenario according to an embodiment of the present application.
Reference numerals:
001-a display screen; 002-battery cover; 003-middle frame;
USB_IN-wired charging interface; RX_IN-wireless charging interface;
1-a driving device; 2-a first transistor; 3-a second transistor;
601—existing substrate; 602-an existing nucleation layer; 603-an existing buffer layer; 604-existing channel layer; 605-an existing barrier layer; 606-a first semiconductor layer; 607-a first insulating dielectric layer; 608-a first field plate; 609—a first field plate extension metal; 610-a first drain electrode; 611-a second drain electrode;
11-a substrate; 12-a transition layer; 1201-nucleation layer; 1202-a transition layer body; 13-a channel layer; 14-a barrier layer; 1401-first part; 1402-second part; 15-a first dielectric layer; 16-a first drain; 17-a second drain; 18-gate; 19-a first gate field plate; 20-a second dielectric layer; 21-a second gate field plate;
G-gate pins; d1-a first drain pin; d2—second drain pin.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone.
The terms first and second and the like in the description and in the claims of embodiments of the application, are used for distinguishing between different objects and not necessarily for describing a particular sequential order of objects. For example, the first target object and the second target object, etc., are used to distinguish between different target objects, and are not used to describe a particular order of target objects.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" means two or more. For example, the plurality of processing units refers to two or more processing units; the plurality of systems means two or more systems.
The embodiment of the application provides electronic equipment, which can be any electronic equipment such as a mobile phone, a computer, a tablet personal computer, a personal digital assistant (personal digital assistant, PDA for short), a vehicle-mounted computer, a television, intelligent wearable equipment, intelligent household equipment and the like. The structure of the electronic device is described below by taking the example that the electronic device is a mobile phone.
Referring to fig. 1 and 2, an exemplary electronic device may be a mobile phone with a wireless charging function, including a display screen 001, a battery cover 002 and a middle frame 003, where the three enclose a housing cavity, a battery (not shown in the drawing), a wireless charging coil (not shown in the drawing) and a Printed Circuit Board (PCB) (not shown in the drawing) may be disposed in the housing cavity, and a circuit for controlling charging of the electronic device is disposed on the PCB. Referring to fig. 3, taking a mobile phone as an example, for a mobile phone charging path with both wired and wireless charging, IN order to control the on-off of the charging path and avoid mutual charging of wired charging and wireless charging current, devices capable of realizing bidirectional on-off are required to be respectively arranged on a line where a wired charging interface usb_in is located and a line where a wireless charging interface rx_in is located, and the on-off of the two-phase on-off devices is controlled by a driving device 1. A relatively common MOS tube can be selected as an on or off device. However, due to the parasitic diode in the MOS tube, a single MOS tube cannot realize bidirectional on or off. Therefore, two N-shaped MOS tubes can be arranged in a line needing to be turned on or turned off in a bidirectional manner, the source electrodes of the two MOS tubes are connected with each other, the grid electrodes of the two MOS tubes are connected with one end of the driving device 1, and the driving device 1 turns on or turns off the two MOS tubes simultaneously. Thus, the two-way on/off of the line where the USB_IN of the wired charging interface is located and the line where the RX_IN of the wireless charging interface is located can be realized.
However, with the development of technology, the degree of integration of electronic devices is higher and higher, the area of a motherboard where devices can be placed is more and more intense, and the solution of setting two MOS transistors occupies too much area of the motherboard, and some electronic devices cannot be distributed with space for placing two MOS transistors on the motherboard. Referring to fig. 4, based on the above-described problems, a high electron mobility transistor is given in the related art, and this transistor may include, from bottom to top: an existing substrate 601, an existing nucleation layer 602 that is epitaxial on the existing substrate 601, an existing buffer layer 603 that is epitaxial on the existing nucleation layer 602, an existing channel layer 604 that is epitaxial on the existing buffer layer 603, and an existing barrier layer 605 that is epitaxial on the existing channel layer 604. The gate structure layer may include: the first semiconductor layer 606 and the first insulating dielectric layer 607, the thickness of the first insulating dielectric layer 607 is smaller than the thickness of the first semiconductor layer 606. The field plate layer may include: the first field plate 608 and the first field plate extension metal 609 may form an inverted U-shaped gate field plate structure extending from the first field plate 608 to both sides. The first drain electrode 610 and the second drain electrode 611 are symmetrically distributed on two sides of the gate structure layer. It is not difficult to find out through the structure, the two-dimensional electron gas concentration of the channel is positively related to the structure thickness of the existing barrier layer 605, but the existing barrier layer 605 is too thick, so that a conductive channel is easy to build, and the threshold voltage is reduced. To maintain a reasonable threshold voltage, the existing barrier layer 605 needs to be thinned appropriately, so that the channel two-dimensional electron gas concentration is reduced and the impedance per unit area is increased. Further, since the first field plate 608 and the first semiconductor layer 606 are in direct contact, the leakage current of the gate electrode is large, and the gate voltage resistance is poor. It can be seen that the structural features in the related art cause several technical problems, including the problem that the ideal threshold voltage and the ideal on-resistance of the device are not compatible; and the leakage current of the grid electrode is larger, and the voltage withstand of the grid electrode is poorer.
Referring to fig. 5, in view of this, an embodiment of the present invention provides a gallium nitride (GaN) Heterojunction Field Effect Transistor (HFET) (hereinafter, referred to simply as a transistor), which may include a substrate 11, and may be selected from a material such as silicon, silicon carbide, sapphire, or gallium nitride, and the like, the substrate 11 may be formed with a transition layer 12, and a nucleation layer 1201 may be deposited on the substrate 11 using a novel vapor phase epitaxy (MOCVD) technique when the transition layer 12 is formed, thereby forming a film layer having a lattice structure corresponding to that of the nucleation layer material. The nucleation layer material may be gallium nitride (GaN) or aluminum nitride (AlN). However, since the crystal structure of the substrate 11 and the crystal structure of the nucleation layer 1201 are not identical, the lattice constants of the two, that is, the physical dimensions of the unit cells have differences. This results in a lattice mismatch in the lattice structure of the grown crystal on the substrate 11. The inter-crystal stress thus grown is large, and in order to grow a crystal with relaxed stress state, it is also necessary to continue the growth of the transition layer body 1202 on the basis of the nucleation layer 1201. The manner and materials of growth of the transition layer body 1202 may be varied, for example, an aluminum gallium nitride (AlGaN) transition layer body 1202 of graded aluminum composition may be grown on the side of the nucleation layer 1201 remote from the substrate 11. It may be arranged that the aluminum composition is highest on the side close to the nucleation layer 1201 until it transitions to the surface of the transition layer body 1202 on the side remote from the nucleation layer 1201, where the aluminum composition is zero. Alternatively, an N-type gallium nitride material formed by doping with carbon (C) or iron (Fe) may also be grown on the side of nucleation layer 1201 remote from substrate 11. Alternatively, a homogenous AlGaN material may be grown on the side of nucleation layer 1201 remote from substrate 11, with the Al and Ga ratios selected according to actual needs. Alternatively, superlattice AlGaN material may also be grown on the side of nucleation layer 1201 remote from substrate 11, i.e., the two materials may be alternately formed on nucleation layer 1201. By way of example, 20 nanometers of gallium nitride and 20 nanometers of aluminum gallium nitride may be alternately formed on nucleation layer 1201. Of course, the above examples are given for a few of the materials and growth methods of the transition layer 12, and other materials may be used for the transition layer 12, and other growth methods may be used. The superlattice structure may also be obtained by a combination of the above methods, for example, during growth of the bulk aluminum gallium nitride transition layer 1202 of graded aluminum composition on the side of the nucleation layer 1201 remote from the substrate 11. Embodiments of the present invention are not limited with respect to the particular materials and manner of preparation of the transition layer 12. During the growth of the transition layer body 1202, the newly grown inter-crystal stress gradually decreases, the unit cells gradually become regular and uniform, and the lattice mismatch gradually disappears. This reduces the stress between crystals and relaxes the lattice. Due to the presence of the transition layer body 1202, the nucleation layer 1201 dislocations are shielded, releasing the stress caused by the lattice mismatch, while also providing high resistance in the transistor height direction.
Referring to fig. 6, after the transition layer 12 is formed, a channel layer 13 may be epitaxially grown on a side of the transition layer 12 away from the substrate 11. The material of the channel layer 13 may be pure gallium nitride (ign), and during epitaxy, the gallium nitride material does not undergo any doping, and remains lattice relaxed, and remains with a higher material quality. The thickness of the channel layer 13 may be determined according to actual needs.
Referring to fig. 7, after forming the channel layer 13, a barrier layer 14 may be epitaxially grown on a side of the channel layer 13 remote from the transition layer 12. A two-dimensional electron gas is formed at the interface of the barrier layer 14 and the channel layer 13, and electrons in the two-dimensional electron gas can move in a plane along the interface of the barrier layer 14 and the channel layer 13. In which the movement of the electron flood in one direction is limited to a small extent, and a system which is free to move in a plane perpendicular to this direction is called a two-dimensional electron flood. If the electron density in the system is low, it is called a two-dimensional electron gas. Exemplary barrier layer 14 materials may be Al y Ga 1-y N, wherein y is more than 0 and less than or equal to 1. In other words, the material of the barrier layer 14 may be aluminum nitride or aluminum gallium nitride, wherein the ratio of aluminum to gallium may be determined according to practical needs. Since the material of the barrier layer 14 is different from that of the channel layer 13, there is a lattice mismatch phenomenon within the barrier layer 14, which has the advantage of enabling the barrier layer 14 to remain in a stressed state without relaxation to form piezoelectric polarization. Taking the material of the barrier layer 14 as aluminum gallium nitride as an example, since the lattice constant of the aluminum gallium nitride material is between that of aluminum nitride and gallium nitride, when aluminum gallium nitride grows on the gallium nitride material, the aluminum gallium nitride material will be subjected to tensile stress in the transverse direction and compressed in the longitudinal direction. This causes the distance between the center of positive electricity and the center of negative electricity, which are not coincident with each other, to further increase, thereby generating a piezoelectric polarization effect. Such an arrangement can form a two-dimensional electron gas at the interface of the barrier layer 14 and the channel layer 13, thereby obtaining a conductive channel having high electron mobility.
Referring to fig. 8, after the formation of the barrier layer 14, a recess is etched in the barrier layer 14 at a location where the gate electrode 18 is to be received, the recess dividing the barrier layer 14 into a first portion 1401 and a second portion 1402 on opposite sides of the recess. The process of forming the recess may be any etching process, such as a chemical etching process, etc. The depth of the groove can be determined according to actual needs, the barrier layer 14 can be completely etched in the area where the groove is located, and a certain thickness can be reserved. The provision of the grooves can cut off the two-dimensional electron gas in the channel layer 13, so that the transistor can be kept in an off state without an external voltage being applied.
Referring to fig. 9, after forming the recess, a first dielectric layer 15 may be formed on the surface of the barrier layer 14 and the surface of the recess. The first dielectric layer 15 may be formed in any manner, and illustratively, the first dielectric layer 15 may be formed by plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD). Specifically, the method is a method of depositing a semiconductor thin film material by performing a chemical reaction on the surface of the barrier layer 14 and the surface of the recess after ionization of the formation by glow discharge in the deposition chamber. In the chemical vapor deposition, a gas is excited to generate low-temperature plasma to enhance the chemical activity of a reactant substance, so that epitaxy is performed. The method can form a solid film at a lower temperature. For example, a substrate material is placed on a cathode in a reaction chamber, reaction gas is introduced to lower pressure (1-600 Pa), the substrate is kept at a certain temperature, glow discharge is generated in a certain mode, gas near the surface of the substrate is ionized, the reaction gas is activated, and cathode sputtering is generated on the surface of the substrate, so that the surface activity is improved. There are not only usual thermochemical reactions but also complex plasma chemical reactions on the surface. The deposited film is formed by the combined action of the two chemical reactions. In addition to the above method, the first dielectric layer 15 may be formed by a low pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition, LPCVD). When using low pressure chemical vapor deposition, one or more gaseous precursors (chemical gases) need to be introduced into the reaction chamber. This step is carried out at a lower pressure, typically below atmospheric pressure. This helps to increase the reaction speed and uniformity, and improve the quality of the film. The flow and pressure of the gas are typically precisely regulated by dedicated controllers and valves. The choice of gas determines the nature of the film that is ultimately formed. The gas precursor molecules adsorb at the surface of the barrier layer 14 and the surface of the grooves. Adsorption is the process by which precursor molecules stay on and interact with the substrate surface. In particular the number of the elements, Molecules are transferred from the gas phase to the solid phase, but are not actually incorporated into the solid phase, adsorption includes physical adsorption, chemical adsorption, and the like. The precursors adsorbed on the surface of the barrier layer 14 and on the surface of the recess then chemically react at a set temperature to form a thin film deposited on the surface. These reactions may be decomposition reactions, substitution reactions, reduction reactions, etc., and the specific type of reaction depends on the type of gas and the reaction conditions. The resultant material of the reaction forms a thin film that is uniformly deposited on the surface of the barrier layer 14 and the surface of the recess. The first dielectric layer 15 may also be formed by atomic layer deposition (atomic layer deposition, ALD). This is a method by which substances can be plated onto the substrate surface layer by layer in the form of monoatomic films. Atomic layer deposition is similar to common chemical deposition. However, during atomic layer deposition, the chemical reaction of a new atomic layer is directly related to the previous layer in such a way that only one atomic layer is deposited per reaction. The material of the first dielectric layer 15 may be silicon nitride (SiN x ) Alumina (Al) 2 O 3 ) Aluminum nitride (AlN), silicon dioxide (SiO) 2 ) Or hafnium oxide (HfO) 2 ) And insulating materials. The foregoing gives a variety of processes for forming the first dielectric layer 15 and materials for the first dielectric layer 15, which are only examples, and the embodiments of the present invention are not limited to the processes for forming the first dielectric layer 15 and the materials for the first dielectric layer 15.
Referring to fig. 10, after the first dielectric layer 15 is formed, a partial region of the first dielectric layer 15 needs to be removed to form the first drain electrode 16 and the second drain electrode 17. The first drain is electrically connected to the first portion 1401 of the barrier layer 14 and the second drain is electrically connected to the second portion 1402 of the barrier layer 14. The manner of removing the regions of the first dielectric layer 15 corresponding to the first drain electrode 16 and the second drain electrode 17 is varied. During the production of transistors, a plurality of transistors are often gathered on a wafer. After the completion of the production, the wafer needs to be diced to form individual transistors. For example, a photoresist may be formed on a surface of the first dielectric layer 15 on a side away from the barrier layer 14, and the photoresist may be disposed on the other first dielectric layer 15 except for corresponding regions of the first drain electrode 16 and the second drain electrode 17. The formation of the photoresist may include the steps of coating a photoresist film on the surface of the first dielectric layer 15, and then attaching a mask plate having a predetermined hollowed-out pattern to the first dielectric layer 15, and exposing the mask plate by irradiating ultraviolet light. Ultraviolet light irradiates the photoresist film through the hollowed-out area of the eye template, at the moment, photoreaction occurs, and the solubility difference is generated between the illuminated part and the non-illuminated part. Then immersing the exposed wafer in a developing solution, wherein the exposed areas of the positive photoresist and the non-exposed areas of the negative photoresist are dissolved in the developing solution. Thereby presenting a three-dimensional pattern. The developed wafer requires a high temperature process called hardening, which is mainly used to further enhance the adhesion of the photoresist to the substrate 11. Then, the wafer is further etched to remove the first dielectric layer 15, which is not protected by the photoresist, in the corresponding areas of the first drain electrode 16 and the second drain electrode 17. The etching operation may be wet etching in a liquid state or dry etching in a gaseous state. For wet etching, a strong acid solution is often used for etching; dry etching often uses a plasma or a high-energy ion beam to damage the material surface and etch it. After the etching is finished, photoresist is removed, all steps of the etching are finished, and the removal of the first dielectric layer 15 in the corresponding areas of the first drain electrode 16 and the second drain electrode 17 is finished.
Referring to fig. 11, after the removal of the first dielectric layer 15 in the corresponding regions of the first drain electrode 16 and the second drain electrode 17 is completed and the barrier layer 14 in the corresponding regions is exposed, preparation of the first drain electrode 16 and the second drain electrode 17 is required. The metal material may be formed by any process in the corresponding regions of the first drain electrode 16 and the second drain electrode 17 of the barrier layer 14. An ohmic junction may be formed, for example, by an ohmic contact process, thereby obtaining the first drain electrode 16 and the second drain electrode 17 made of metal. Ohmic contact processes can be broadly classified into ion implantation processes and epitaxial processes. The ion implantation process is to generate impurity ions with positive charges from raw materials, the impurity ions are accelerated by an electric field to obtain enough energy, so that the impurity ions can enter a target lattice, and then the impurity ions are activated by a thermal annealing process, so that the impurity doping of the substrate material is realized. Because ion implantation can accurately control the concentration and depth of implanted impurities, the ion implantation is more suitable for the Moore law of smaller and smaller device sizes, and therefore, the ion implantation plays an irreplaceable role in the process. However, ion implantation has some drawbacks, namely that high-energy impurity ions bombard the substrate 11, and lattice damage is caused despite the repair by annealing; in addition, the high precision control of impurity ions by ion implantation necessarily entails the complexity of the ion implanter. The epitaxial technique is to grow a single crystal layer on the substrate 11, and can be basically classified into three modes according to the mode of transporting atoms to the substrate 11: solid phase epitaxy (Solid Phase Exitaxy, SPE), vapor phase epitaxy (Vapor Phase Exitaxy, VPE) and liquid phase epitaxy (Liquid Phase Exitaxy, LPE). Unlike ion implantation, depending on the epitaxy mode, a different apparatus or method may be selected for epitaxy, such as a different gas phase reactor or some chemical vapor deposition apparatus for VPE mode, a liquid phase reactor or alloy mode for LPE mode, etc. Therefore, the equipment for epitaxy is relatively simple and much less damaging to the substrate 11 than the ion implantation method. From the above, it can be seen that the ohmic contact process is implemented in various ways, and a specific process can be selected according to actual needs to perform production and manufacture.
Referring to fig. 12, after the step of forming the first dielectric layer 15, the gate electrode 18 of the transistor is also prepared. The gate 18 may be made of metal. The gate electrode 18 may be prepared by sputtering or vapor deposition, wherein the sputtering is to guide ions to a target electrode to be sputtered by utilizing the characteristic that charged ions have a certain kinetic energy after being accelerated in an electric field. In the case where the ion energy satisfies a certain condition, the incident ion causes the target atoms to be sputtered from the surface during collision with the target atoms, and the sputtered atoms have a certain kinetic energy and are directed in a certain direction to the region where the gate electrode 18 is to be formed, thereby realizing the formation of the gate electrode 18 in the recess. The vapor deposition is a process method of evaporating and gasifying a coating material (or film material) by adopting a certain heating and evaporating mode, and enabling particles to fly to the surface of a groove of a wafer to be condensed. Has the advantages of simple film forming method, high purity and compactness of the film, unique film structure and performance, and the like.
In order to ensure that the current flowing from the first drain electrode 16 through the second drain electrode 17 is consistent with the electrical characteristics of the second drain electrode 17 flowing through the first drain electrode 16, symmetry of the transistor structure should be ensured. I.e. the transistors on both sides of the recess should be symmetrical to each other. If the structures of the transistors are symmetrical, the consistency of the electrical properties of the two ends of the transistors can be ensured.
The barrier layer 14 of the present embodiment is provided with a recess that intercepts the two-dimensional electron gas of the first portion 1401 and the second portion 1402 of the barrier layer 14, so that the conductive channel is not easily established and the threshold voltage is maintained at a high level. Therefore, even if the channel layer 13 is kept thick, an excessive drop in threshold voltage is not caused. Further, the thicker the barrier layer 14 is, the higher the concentration of the two-dimensional electron gas is, and the smaller the on-resistance is. The arrangement ensures that the concentration of the two-dimensional electron gas of the barrier layer 14 is low, so that the on-resistance of the transistor is low, and the threshold voltage is not too low. And because the first dielectric layer 15 is arranged between the grid electrode 18 and the semiconductor material, the first dielectric layer 15 can block the current between the grid electrode 18 made of metal and the semiconductor material layer, so that the leakage current of the grid electrode 18 is greatly reduced.
Referring to fig. 13, in other embodiments, a first gate field plate 19 may be further added, where the first gate field plate 19 is electrically connected to the gate 18. The first gate field plate 19 may be formed simultaneously with the formation of the gate electrode 18. After the gate electrode 18 is prepared, the region occupying the space where the first gate electrode field plate 19 is not required to be formed may be covered with photoresist, and then the first gate electrode field plate 19 may be formed by sputtering or vapor deposition. The first gate field plate 19 extends in the direction of the first drain electrode 16 and the second drain electrode 17, respectively, and is not in contact with the first drain electrode 16 and the second drain electrode 17, and the shape and size of the first gate field plate 19 may be determined according to actual needs. Due to the presence of the first gate field plate 19, the electric field distribution state of the gate 18 is changed, and the gate electric field is uniformly distributed. The electric field spikes caused by too dense an electric field between the gate 18 edge and the first drain 16, and between the gate 18 edge and the second drain 17, are largely relieved. The electric field is uniformly distributed, the voltage-withstanding capability of the transistor is improved by the balanced electric field, and the current collapse effect is improved. The current collapse effect is an effect that when the voltage of the first drain or the second drain of the transistor exceeds a certain value, the current starts to drop with the increase of the drain voltage, and the ideal value cannot be reached. In addition, the structure has stronger pressure resistance, so that smaller wafer size can be realized under the same pressure resistance level, thereby further reducing the cost and the area of the device.
In other embodiments, the number of gate field plates may be two or more, with all gate field plates being connected to gate 18. Referring to fig. 14, for example, two gate field plates may be provided, and the method of providing the two gate field plates may be to prepare the second dielectric layer 20 on the side of the wafer having the gate field plates and provide the second gate field plates 21 in the second dielectric layer 20 after the gate field plates are formed in the above embodiments. Wherein the material and preparation method of the second dielectric layer 20 may be the same as those of the first dielectric layer 15; the material and preparation method of the second gate field plate 21 may be the same as those of the first gate field plate 19. For example, a second dielectric layer 20 may be formed on the side of the first gate field plate 19 remote from the gate electrode 18, and a cured photoresist may be formed on the side of the second dielectric layer 20 remote from the first gate field plate 19, where the cured photoresist covers only the area outside the second gate field plate 21, and may expose the area where the second gate field plate 21 is to be fabricated. The second gate field plate 21 is formed using a sputtering or evaporation process at a region where the second gate field plate 21 is to be prepared.
The second gate field plate 21 may have a larger footprint than the first gate field plate 19. The shape of the second gate field plate 21 may be set such that both side edges of the second gate field plate 21 are slightly lower in height than the body portion of the second gate field plate 21. The advantage of this arrangement is that the electric field optimizing capability of the second gate field plate 21 can be made stronger, and the voltage withstanding capability of the transistor can be further improved.
The gallium nitride heterojunction field effect transistor above is applicable to several scenarios, two of which will be described herein by way of example.
Scene one
The transistor provided by the embodiment of the invention can be applied to any scene needing bidirectional on and off. Referring to fig. 15, a transistor with two sides symmetrical along a groove provided by the embodiment of the invention can be arranged on a line needing to be turned on and off in a bidirectional manner, and the transistor can be packaged into a patch type or pin type device. The device comprises at least a gate pin G connected to the gate 18 of the transistor, a first drain pin D1 connected to the first drain 16 of the transistor, and a second drain pin D2 connected to the second drain 17 of the transistor. The driving circuit needs to be connected with the gate pin G, and the device is connected into a line which needs to be controlled to be turned on and off in a bidirectional manner through the first drain pin D1 and the second drain pin D2. When the transistor is required to be turned on, a voltage needs to be applied to the gate 18 of the transistor, so that the gate voltage is higher than the voltage of the first drain 16, and the voltage difference between the gate 18 and the first drain 16 is greater than the first threshold voltage; alternatively, the gate voltage is made higher than the voltage of the second drain 17, and the voltage difference between the gate 18 and the second drain 17 is made greater than the second threshold voltage. Since the two sides of the transistor are symmetrical along the groove, the electrical properties of the first drain side and the second drain side of the transistor are also the same, and the first threshold voltage is equal to the second threshold voltage. Wherein the threshold voltage is related to the transistor parameter, which can be known by measuring the transistor. After the gate voltage reaches the above range, carriers, i.e., induced electrons, are generated in the channel layer 13. The induced electrons are connected with the two-dimensional electron gas in the barrier layer 14, which is interrupted by the grooves, to form a conductive channel, and conduction between the first drain electrode 16 and the second drain electrode 17 is realized. When the gate voltage does not reach the above range, the induced electrons in the channel layer 13 decrease, and the induced electrons are insufficient to connect the first portion 1401 and the second portion 1402 of the barrier layer 14, and the conductive channel is disconnected. A disconnection between the first drain electrode 16 and the second drain electrode 17 is achieved.
Scene two
The transistor of the embodiment of the application can be applied to a mobile phone PCB with both wired charging function and wireless charging function. Referring to fig. 16, IN order to control the on-off of the charging path and avoid mutual charging of the wired charging and the wireless charging, the first transistor 2 provided IN the embodiment of the present application needs to be provided on the line where the wired charging interface usb_in is located, and the second transistor 3 provided IN the embodiment of the present application needs to be provided on the line where the wireless charging interface rx_in is located. The first transistor 2 and the second transistor 3 are controlled to be turned on or off respectively by two pins of the driving device 1. For example, when wired charging is performed, the first transistor 2 may be controlled to be on by the driving device 1, and the second transistor 3 may be turned off. When the wireless charging is performed, the second transistor 3 can be controlled to be turned on by the driving device 1, and the first transistor 2 is turned off, so that current backflow is prevented.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims (20)

1. A gallium nitride heterojunction field effect transistor, comprising:
the channel layer is made of gallium nitride;
the barrier layer is arranged on one side of the channel layer, the barrier layer comprises a groove, and a first part and a second part which are respectively arranged on two sides of the groove, the groove at least comprises a first opening, the opening direction of the first opening deviates from the direction of the channel layer, and two-dimensional electron gas is formed on the interface of the channel layer, which is respectively contacted with the first part and the second part;
the first drain electrode is arranged on one side of the first part, far away from the channel layer, and the first drain electrode is made of a conductive material;
the second drain electrode is arranged on one side of the second part far away from the channel layer, and the material of the second drain electrode is conductive material;
the first dielectric layer is at least arranged on the inner surface of the groove, and the material of the first dielectric layer is an insulating material;
the grid is arranged in the groove, and the grid is made of conductive materials.
2. The gallium nitride heterojunction field effect transistor of claim 1, wherein the material of the barrier layer is Al y Ga 1-y And N, wherein Al is aluminum, ga is gallium, N is nitrogen, and y is more than 0 and less than or equal to 1.
3. The gallium nitride heterojunction field effect transistor of claim 1, wherein the material of the first dielectric layer comprises silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide, or hafnium dioxide.
4. The gallium nitride heterojunction field effect transistor of claim 1, wherein the depth of the recess is the same as the thickness of the barrier layer.
5. The gallium nitride heterojunction field effect transistor of claim 1, further comprising a first gate field plate, wherein the first gate field plate is connected to the gate, two sides of the first gate field plate extend in a direction in which the first drain electrode is located and a direction in which the second drain electrode is located, and the first dielectric layer is disposed between the first gate field plate and the barrier layer.
6. The gallium nitride heterojunction field effect transistor of claim 5, further comprising a second dielectric layer and a second gate field plate disposed opposite the first gate field plate, the second gate field plate being disposed between the first drain, the second drain, and the first gate field plate with the second dielectric layer, the second gate field plate, the first gate field plate, and the gate being electrically connected.
7. The gallium nitride heterojunction field effect transistor of claim 6, wherein the material of the second dielectric layer comprises silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide, or hafnium dioxide.
8. The gallium nitride heterojunction field effect transistor of claim 1, further comprising a transition layer disposed on a side of the channel layer remote from the barrier layer.
9. The gallium nitride heterojunction field effect transistor of claim 8, wherein the transition layer comprises a transition layer body and a nucleation layer, the transition layer body being disposed on a side of the channel layer remote from the barrier layer, the nucleation layer being disposed on a side of the transition layer body remote from the channel layer.
10. The gallium nitride heterojunction field effect transistor of claim 9, wherein the material of the transition layer body comprises aluminum gallium nitride of graded aluminum composition, N-type gallium nitride, homogenous aluminum gallium nitride, or superlattice aluminum gallium nitride; the material of the nucleation layer comprises gallium nitride or aluminum nitride.
11. The gallium nitride heterojunction field effect transistor of claim 8, further comprising a substrate disposed on a side of the transition layer remote from the channel layer.
12. A method for manufacturing a gallium nitride heterojunction field effect transistor according to any one of claims 1 to 11, comprising:
preparing the channel layer;
preparing the barrier layer on the channel layer;
the groove is formed in the position, corresponding to the grid electrode, of one side, far away from the channel layer, of the barrier layer;
forming the first dielectric layer on the inner surface of the groove and one side of the barrier layer away from the channel layer;
removing the first dielectric layer at the positions corresponding to the first drain electrode and the second drain electrode;
and forming the first drain electrode and the second drain electrode, and forming the grid electrode.
13. The method of claim 12, further comprising forming a first gate field plate on a side having the gate after forming the gate.
14. The method of claim 13, wherein forming the first gate field plate on the side having the gate electrode comprises forming a photoresist on the side having the gate electrode, exposing a region where the first gate field plate is to be formed, and forming the first gate field plate on the region where the first gate field plate is to be formed using a sputtering or evaporation process.
15. The method of claim 12, further comprising forming a second dielectric layer on a side of the first gate field plate remote from the gate and forming the second gate field plate on a side of the second dielectric layer remote from the first gate field plate.
16. The method of claim 15, wherein forming the second gate field plate on a side of the second dielectric layer away from the first gate field plate comprises forming a photoresist on a side of the second dielectric layer away from the first gate field plate, exposing a region where the second gate field plate is to be formed, and forming the second gate field plate on the region where the second gate field plate is to be formed using a sputtering or evaporation process.
17. The method of claim 12, wherein forming the recess comprises forming a photoresist on a side of the barrier layer away from the channel layer, exposing a portion of the recess to be formed, and etching a side of the barrier layer away from the channel layer to form the recess.
18. The method of claim 12, wherein removing the first dielectric layer at a location corresponding to the first drain electrode and the second drain electrode comprises forming a photoresist on a side of the first dielectric layer away from the channel layer and exposing portions of the first drain electrode and the second drain electrode to be formed.
19. The method of manufacturing a gallium nitride heterojunction field effect transistor of claim 12, further comprising, prior to preparing the channel layer:
obtaining a substrate;
forming a nucleation layer on the surface of the substrate by a vapor phase epitaxy technique;
a transition layer body is grown on a side of the nucleation layer remote from the substrate.
20. An electronic device characterized in that the gallium nitride heterojunction field effect transistor according to any one of claims 1 to 11 is used.
CN202311309023.6A 2023-10-11 2023-10-11 Gallium nitride heterojunction field effect transistor, manufacturing method and electronic equipment Pending CN117080247A (en)

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