CN117057302A - Heuristic layout wiring method for circuit schematic diagram - Google Patents
Heuristic layout wiring method for circuit schematic diagram Download PDFInfo
- Publication number
- CN117057302A CN117057302A CN202311316090.0A CN202311316090A CN117057302A CN 117057302 A CN117057302 A CN 117057302A CN 202311316090 A CN202311316090 A CN 202311316090A CN 117057302 A CN117057302 A CN 117057302A
- Authority
- CN
- China
- Prior art keywords
- elements
- layout
- value
- bubble
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000010586 diagram Methods 0.000 title claims abstract description 32
- 230000005587 bubbling Effects 0.000 claims description 28
- 238000002407 reforming Methods 0.000 claims description 13
- 238000012163 sequencing technique Methods 0.000 claims description 6
- 235000013399 edible fruits Nutrition 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 7
- 230000002457 bidirectional effect Effects 0.000 description 7
- 238000002679 ablation Methods 0.000 description 5
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 238000005457 optimization Methods 0.000 description 3
- 230000002087 whitening effect Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000001792 White test Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of automatic circuit design, and provides a heuristic layout wiring method of a circuit schematic diagram. The method comprises the following steps: extracting element information and connection information from the netlist file; preliminary layout is carried out on the element information through a topology algorithm; performing a forward value propagation bubble ordering from a first column element to a last column element and a reverse value propagation bubble ordering from a last column element to a first column element, wherein each is obtained by calculating an average value of the bubble values of the previous sequence as a current column bubble value; assigning new bubble values to elements with equal bubble values in any column to optimize element position relationship; stretching the columns with less elements to leave blank so as to be the same as the elements in the reference columns; wiring is carried out according to the connection information to obtain a preliminary wiring result, and a plurality of through lines share a vertical axis space through a greedy algorithm; drawing a schematic circuit diagram. The invention can reduce the time complexity of the algorithm and generate the schematic diagram with higher aesthetic degree and logic definition in real time.
Description
Technical Field
The invention relates to the technical field of circuit automation design, in particular to a heuristic layout wiring method of a circuit schematic diagram.
Background
Converting netlist files into schematic diagrams plays an important role in the technical field of circuit automation design, and can help designers to quickly understand circuit structures or to check circuit errors. Solving such problems requires fast operation speed, and high aesthetic and logic definition of the generated schematic diagram. Existing solutions can be divided into two major categories, knowledge-based methods and formalized algorithm-based methods.
The knowledge-based method mainly solves the problem by using an artificial intelligence method based on symbology, and solves the problem by using an expert system by establishing a series of rules. Such methods have problems of low operation efficiency and difficulty in constructing a practically effective system.
Whereas formalized algorithm-based methods divide the overall problem into several sub-phases, such as logic phase, geometry phase, layout phase, routing phase, etc., and solve the problem by setting up optimization targets and solutions for each phase. However, the existing method has high algorithm time complexity and cannot guarantee 100% of the routing rate, and in addition, the generated circuit layout and wiring schematic diagram has low aesthetic degree, so that the use efficiency and the accuracy of the circuit schematic diagram used later are affected.
Disclosure of Invention
The present invention is directed to solving at least one of the technical problems existing in the related art. To this end, the invention provides a heuristic layout wiring method of a circuit schematic.
The invention provides a heuristic layout wiring method of a circuit schematic diagram, which comprises the following steps:
s100: extracting element information and connection information required by circuit diagram layout wiring from the netlist file;
s200: performing preliminary layout on the element information through a topology algorithm to obtain a preliminary layout result;
s300: performing forward value propagation bubbling sequencing from the first row element to the last row element on the preliminary layout result, and performing reverse value propagation bubbling sequencing from the last row element to the first row element on the preliminary layout result to obtain forward and reverse layout results, wherein all the forward and reverse layout results are obtained by calculating the average value of the bubbling values of the previous sequence so as to obtain the bubbling value required by the current row;
s400: assigning new bubbling values to the elements with equal bubbling values in any column in the forward and reverse layout results, and optimizing the position relationship of the elements in the forward and reverse layout results through the new bubbling values to obtain a reforming layout result;
s500: obtaining the most element columns in the reforming layout result as reference columns, and stretching and leaving the other columns in the reforming layout result until the elements in the other columns correspond to the absolute line numbers of the elements in the reference columns one by one to obtain a final layout result with the minimum line difference value;
s600: wiring is carried out according to the connection information to obtain a preliminary wiring result, and a plurality of wires in the preliminary wiring result share a vertical axis space through a greedy algorithm to obtain a final wiring result;
s700: and drawing a circuit schematic diagram according to the final layout result and the final wiring result.
According to the heuristic layout and wiring method of the circuit schematic of the present invention, in step S400, the expression for assigning new bubble values to the elements with equal bubble values in any column in the forward and reverse layout results is:
wherein,new bubble value assigned to element with equal bubble value,/v>Original bubble value for element with equal bubble value,/-bubble value>The difference between the bubble values of the element group consisting of the elements with equal bubble values and the element above the element group,difference between the bubble values of the element group consisting of the elements with the same bubble value and the element below the element group, +.>For the serial number of the current element in the element group consisting of elements with equal bubbling values, +.>For the first column element bubble value interval proportionality coefficient in forward and reverse layout result, +.>The number of elements included in the element group consisting of the elements with equal bubbling values of the current element.
According to the heuristic layout and wiring method of the circuit schematic diagram of the present invention, the step S200 includes:
s210: abstracting elements in the element information into directed graph nodes;
s220: abstracting connection relations among elements in the element information into directed graph edges;
s230: and dividing the element row by topological sorting according to the directed graph nodes and the directed graph edges to obtain a preliminary layout result.
According to the heuristic layout and wiring method of the circuit schematic of the present invention, the expression of the minimum row difference value of the final layout result in step S500 is:
wherein,index value for element number in each column in the reformed layout result, < >>For reference line number, +.>For the elements in other columns not to be placed out of order in the smallest row difference calculated after the same row as the elements in the reference row, +.>The row differences calculated before leaving the other in-column elements stretched.
According to the heuristic layout and routing method of the circuit schematic of the present invention, the initial relative positions of the first-row elements in the preliminary layout result in step S300 are randomly specified.
According to the heuristic layout wiring method of the circuit schematic diagram, a topological ordering algorithm is introduced to perform preliminary layout, a value propagation algorithm is introduced to optimize the layout of elements in a column, a bidirectional value propagation algorithm is designed to obtain a better sequence of the elements in the column, a dynamic programming algorithm is designed to stretch the elements in the column to leave white, a through line, a complex line and other design ideas are introduced, and a column gap compression algorithm based on a greedy algorithm is designed, so that the time complexity of the algorithm can be reduced, and a schematic diagram with higher aesthetic degree and logic definition can be generated in real time.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a heuristic layout wiring method of a schematic circuit diagram according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a circuit schematic heuristic layout method according to an embodiment of the present invention, in which step S500 extends the reforming layout result before leaving white.
Fig. 3 is a schematic diagram of a final layout result after stretching and leaving white in step S500 in a circuit schematic heuristic layout wiring method according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The following examples are illustrative of the invention but are not intended to limit the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "coupled," "coupled," and "connected" should be construed broadly, and may be either a fixed connection, a removable connection, or an integral connection, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in embodiments of the present invention will be understood in detail by those of ordinary skill in the art.
In embodiments of the invention, unless expressly specified and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
An embodiment provided by the present invention is described below with reference to fig. 1.
The invention provides a heuristic layout wiring method of a circuit schematic diagram, which comprises the following steps:
s100: extracting element information and connection information required by circuit diagram layout wiring from the netlist file;
s200: performing preliminary layout on the element information through a topology algorithm to obtain a preliminary layout result;
wherein, step S200 includes:
s210: abstracting elements in the element information into directed graph nodes;
s220: abstracting connection relations among elements in the element information into directed graph edges;
s230: and dividing the element row by topological sorting according to the directed graph nodes and the directed graph edges to obtain a preliminary layout result.
Furthermore, the topology ordering algorithm abstracts elements into nodes of the directed graph and the connection relationship among the elements into edges of the directed graph, and uses the concept similar to the topology ordering to divide the elements into rows and columns, so that the effect that the left-to-right direction of connecting lines in the output schematic graph is the flow direction or the signal propagation direction of most of actual currents is achieved.
S300: performing forward value propagation bubbling sequencing from the first row element to the last row element on the preliminary layout result, and performing reverse value propagation bubbling sequencing from the last row element to the first row element on the preliminary layout result to obtain forward and reverse layout results, wherein all the forward and reverse layout results are obtained by calculating the average value of the bubbling values of the previous sequence so as to obtain the bubbling value required by the current row;
wherein, the initial relative positions of the first elements in the preliminary layout result in step S300 are randomly specified.
Further, after one pass of forward value propagation from the first column to the last column, one pass of backward value propagation from the last column to the first column is performed, and thus, the plurality of passes are repeated, and finally, one pass of forward value propagation is performed. This strategy considers that the initial bubble values of the first column elements, i.e., the bus, tend to be randomly specified, while poor initial bubble values may cause the ordering of elements within subsequent columns to be affected. The method can relieve the influence of incorrect sequence of the elements in the first column on the sequence optimization of the elements in the column by a multi-pass bidirectional value transmission mode, thereby achieving the effect of improving logic definition.
Further, in calculating the bubble values of elements in a column, the bubble values of elements in all columns preceding the connection are averaged, rather than only the elements of the previous column, thereby increasing the optimization of the position of the elements connected across columns.
S400: assigning new bubbling values to the elements with equal bubbling values in any column in the forward and reverse layout results, and optimizing the position relationship of the elements in the forward and reverse layout results through the new bubbling values to obtain a reforming layout result;
further, both the methods of step S300 and step S400 are improved on the basis of the classical value propagation algorithm, and the bubble value reforming method of step S400 is performed during the bi-directional value propagation algorithm of step S300, that is, the bubble value reforming and bi-directional value propagation methods are performed simultaneously.
Wherein, in step S400, the expression for assigning a new bubble value to the element with the same bubble value in any column in the forward and reverse layout result is:
wherein,new bubble value assigned to element with equal bubble value,/v>Original bubble value for element with equal bubble value,/-bubble value>The difference between the bubble values of the element group consisting of the elements with equal bubble values and the element above the element group,difference between the bubble values of the element group consisting of the elements with the same bubble value and the element below the element group, +.>For the serial number of the current element in the element group consisting of elements with equal bubbling values, +.>For the first column element bubble value interval proportionality coefficient in forward and reverse layout result, +.>The number of elements included in the element group consisting of the elements with equal bubbling values of the current element.
Further, after the elements in a column are ordered according to the bubble values, the elements with the same bubble values in the column are endowed with new bubble values, so that the information of the relative positions of the elements in the column is introduced on the basis of the relative position relation of the previous column, and the position relation of the elements in the subsequent column is further optimized.
S500: obtaining the most element columns in the reforming layout result as reference columns, and stretching and leaving the other columns in the reforming layout result until the elements in the other columns correspond to the absolute line numbers of the elements in the reference columns one by one to obtain a final layout result with the minimum line difference value;
the stretch-blank process of step S500 is described below with reference to fig. 2 to 3, in which the right column of elements is the column with the largest number of elements in the result of the reforming layout, and is selected as the reference column, the reference columns have element numbers of J1 to J7, respectively, the left column of elements is relatively fewer, and the other columns have element numbers of Q1 to Q3, respectively, in which Q1 is in line with J1, but Q1 is connected with J2, Q2 is in line with J3, but Q2 is connected with J4, Q3 is in line with J5, but Q3 is connected with J6, and after stretch-blank, Q1 is in line with J2 and is connected, Q2 is in line with J4 and is connected, and three connecting lines are parallel, that is, the distance between the elements in connection through stretch-blank is closer, and the circuit layout is more attractive.
Further, the absolute line number of the element is the line number of the element corresponding to the reference column in the horizontal direction of the current element, according to fig. 2, i.e., Q1 is the first element in the other column, the relative line number is 1, the element in the reference column corresponding to the same horizontal line is J1, J1 is the first element in the reference column, the relative line number of J1 is 1, the absolute line number of Q1 is the relative line number of J1, the absolute line number of Q1 is also 1, the element in the reference column corresponding to the same Q2 level is J3, the relative line number of Q2 is 2, the absolute line number is 3, and other elements are the same.
In some embodiments, there may be a parallel structure where one element is connected to two elements, for example, A1 is an element in another column, B1 and B2 are elements in a reference column, A1 is connected in parallel to B1 and B2 respectively, before stretching, A1 corresponds to B1 horizontally, after stretching, A1 corresponds to B1 horizontally, or corresponds to B2 horizontally, so as to ensure that the line difference value of the elements in the column is minimum.
The expression of the minimum row difference value of the final layout result in step S500 is:
wherein,index value for element number in each column in the reformed layout result, < >>For reference line number, +.>For the elements in other columns not to be placed out of order in the smallest row difference calculated after the same row as the elements in the reference row, +.>The row differences calculated before leaving the other in-column elements stretched.
Further, the algorithm in step S500 is defined as a dynamic programming algorithm, the column with the largest number of elements is set as the reference column, and according to the dynamic programming algorithm, each of the remaining columns of elements is "stretched", i.e. the absolute line number of each element in the column is calculated, and if the relative line number of the first element is smaller than the relative line number of the second element for any two elements in a column, the absolute line number of the first element is smaller than the absolute line number of the second element and is smaller than the number of the elements in the reference column, i.e. the relative order of the elements in the column is kept unchanged, so that the column line difference is the smallest.
Further, the element row differences sum the absolute row numbers of the elements with the determined absolute row numbers connected with the element absolute row number-reference column direction, and the element row differences in the column sum the element row differences in the column.
S600: wiring is carried out according to the connection information to obtain a preliminary wiring result, and a plurality of wires in the preliminary wiring result share a vertical axis space through a greedy algorithm to obtain a final wiring result;
further, the wiring algorithm is to wire a through line according to the connection condition of the elements and the thinking of sharing a longitudinal line and connect the through line with the elements, wherein a plurality of through lines form a compound line, and the compound line is a set formed by a plurality of groups of two [ elements and ports ]; the open line is an element of the equivalent relation quotient set of the complex line that the [ element, port ] positions are located on two sides of the same channel.
When further wiring is specifically performed, the sets formed by the two groups of elements and ports are combined into multiple wires for processing, the multiple wires are divided into a plurality of through wires, namely, the through wires are firstly wired, and then the through wires belonging to the same multiple wires are connected.
Furthermore, the invention also provides a column gap compression algorithm based on a greedy algorithm, wherein the column gap compression algorithm is that a plurality of pass lines can share the same y-axis space through the greedy algorithm, so that the distance between columns is reduced, and the aesthetic degree of a schematic diagram is improved.
S700: and drawing a circuit schematic diagram according to the final layout result and the final wiring result.
Further, the drawing algorithm uses QT tool to convert the position information of the elements and wires represented by text files in the layout and wiring results into JPG, PNG or SVG format files.
In some embodiments, the present invention uses the actual circuit netlist file generated in the actual integrated circuit design for evaluation verification, uses 10 different netlist files as inputs, from two different circuit design projects, containing a number of components ranging from 7 to 637 and a maximum number of degrees ranging from 4 to 641, the details of the netlist files used in this embodiment are given in Table 1.
TABLE 1 netlist file details
In order to fully reflect the logic definition of the layout and wiring result, the embodiment counts the total number of the cross points, the total number of the turning points of the connecting lines and the length of the connecting lines in the output picture and gives the running time of the system for completing the layout and the wiring. The experimental results are shown in table 2.
TABLE 2 Performance index results obtained by running the heuristic layout and routing method of the schematic circuit diagram of the present invention on the netlist file shown in TABLE 1
As can be seen from the performance index results in Table 2, the heuristic layout wiring system can complete tasks within 100ms when laying out and wiring netlist files of several elements to hundreds of elements, thereby meeting the real-time requirement, and the total number of intersection points, the total number of turning points of connection lines and the total length of connection lines of the graph can basically keep a linear growth relation with the total number of elements.
In addition, in some embodiments, the invention is a combination of mechanisms which together ensure that the output result has higher logic definition, and the embodiment evaluates and verifies the effectiveness of a bi-directional value propagation algorithm and a stretch-to-white algorithm in a dynamic programming column.
Further, in the first part of the embodiment, under the condition that a dynamic programming intra-column stretching white-keeping algorithm is not used, compared with the three conditions that a value propagation algorithm is not adopted, a classical value propagation algorithm is adopted and a bidirectional value propagation algorithm is adopted, the total length of connecting lines, the total number of turning points and the number of crossing points obtained on a 10-group netlist file are compared, the experimental result is shown in a table 3, and the weighted average weight in the table is the inverse of the number of elements.
Table 3 ablation experiment results without using dynamic programming in-column stretch chronicle propagation algorithm
In table 3, avg1 represents the average value of the ablation experimental result of the spreading value propagation algorithm in the dynamic programming column, and Wavg1 is the weighted average value of the ablation experimental result of the spreading value propagation algorithm in the dynamic programming column, and as can be seen from the test result of table 3, when the bidirectional value propagation algorithm is used in the invention, the optimal total length of the connecting line, the total number of turning points and the number of crossing points are obtained, no matter in the weighted or average situation, which indicates that the bidirectional value propagation algorithm is effective for improving the logic definition and the aesthetic degree of the schematic diagram generated by the heuristic layout wiring system, and the bidirectional value propagation algorithm considers the relative position sequence of the elements in the initial column and the element connection relation between different columns, so that the number of crossing points in the wiring process is reduced, and the total length of the connecting line is shortened.
Further, the second part of the embodiment compares whether to use the dynamic programming in-column stretch-to-white algorithm, and the total length of the connection lines, the total number of turning points and the number of crossing points obtained by running the method on 10 groups of data sets are shown in table 4.
Table 4 results of dynamic programming intra-column stretch-to-white test using value propagation algorithm
In table 4, avg2 represents the average value of the ablation experimental results of the stretching and whitening algorithm in the dynamic programming column when the value propagation algorithm is used, and the same Wavg2 represents the weighted average value of the ablation experimental results of the stretching and whitening algorithm in the dynamic programming column when the value propagation algorithm is used, and as can be seen from the system test results of table 4, the total length of the weighted average connection, the total number of turning points and the number of crossing points of the heuristic layout wiring system are reduced by 0.4%, 20.4% and 19.7%, which further indicates that the spacing between elements with connection relations can be effectively compressed by using the stretching and whitening algorithm in the dynamic programming column, the total length of the connection, the total number of turning points and the total number of crossing points are reduced, and the aesthetic degree and the logic definition of the schematic diagram generated by the heuristic layout wiring system are further improved.
According to the heuristic layout wiring method of the circuit schematic diagram, the topology ordering algorithm is introduced to perform preliminary layout, the value propagation algorithm is introduced to optimize the layout of elements in a column, the bidirectional value propagation algorithm is designed to obtain a better sequence of the elements in the column, the dynamic programming algorithm is designed to stretch the elements in the column to leave white, the through line, the complex line and other design ideas are introduced, and the greedy algorithm-based column gap compression algorithm is designed, so that the schematic diagram with higher aesthetic degree and logic definition can be generated in real time, the operation efficiency is high, an actual and effective system can be constructed, the time complexity is reduced, the distribution ratio is also guaranteed, the aesthetic degree of the generated circuit layout wiring schematic diagram is high, and the use efficiency and the accuracy of the circuit schematic diagram used later can be indirectly improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A circuit schematic heuristic layout wiring method, comprising:
s100: extracting element information and connection information required by circuit diagram layout wiring from the netlist file;
s200: performing preliminary layout on the element information through a topology algorithm to obtain a preliminary layout result;
s300: performing forward value propagation bubbling sequencing from the first row element to the last row element on the preliminary layout result, and performing reverse value propagation bubbling sequencing from the last row element to the first row element on the preliminary layout result to obtain forward and reverse layout results, wherein all the forward and reverse layout results are obtained by calculating the average value of the bubbling values of the previous sequence so as to obtain the bubbling value required by the current row;
s400: assigning new bubbling values to the elements with equal bubbling values in any column in the forward and reverse layout results, and optimizing the position relationship of the elements in the forward and reverse layout results through the new bubbling values to obtain a reforming layout result;
s500: obtaining the most element columns in the reforming layout result as reference columns, and stretching and leaving the other columns in the reforming layout result until the elements in the other columns correspond to the absolute line numbers of the elements in the reference columns one by one to obtain a final layout result with the minimum line difference value;
s600: wiring is carried out according to the connection information to obtain a preliminary wiring result, and a plurality of wires in the preliminary wiring result share a vertical axis space through a greedy algorithm to obtain a final wiring result;
s700: and drawing a circuit schematic diagram according to the final layout result and the final wiring result.
2. The heuristic circuit schematic layout routing method of claim 1 wherein the step S400 is performed by assigning a new bubble value to elements of equal bubble values in any column in the forward and reverse layout results as:
wherein,new bubble value assigned to element with equal bubble value,/v>Original bubble value for element with equal bubble value,/-bubble value>Difference between element group composed of elements with equal bubbling values and element above element group, +.>Difference between the bubble values of the element group consisting of the elements with the same bubble value and the element below the element group, +.>For the serial number of the current element in the element group consisting of elements with equal bubbling values, +.>For the first column element bubble value interval proportionality coefficient in forward and reverse layout result, +.>The number of elements included in the element group consisting of the elements with equal bubbling values of the current element.
3. The heuristic circuit schematic layout routing method of claim 1, wherein step S200 comprises:
s210: abstracting elements in the element information into directed graph nodes;
s220: abstracting connection relations among elements in the element information into directed graph edges;
s230: and dividing the element row by topological sorting according to the directed graph nodes and the directed graph edges to obtain a preliminary layout result.
4. The heuristic circuit schematic layout routing method of claim 1 wherein the minimum row difference value of the final layout result in step S500 is expressed as:
wherein,layout junction for reformingElement number index value in each column in the fruit, < ->For reference line number, +.>For the elements in other columns not to be placed out of order in the smallest row difference calculated after the same row as the elements in the reference row, +.>The row differences calculated before leaving the other in-column elements stretched.
5. The heuristic routing method of claim 1, wherein the initial relative positions of the first-column elements in the preliminary routing result in step S300 are randomly assigned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311316090.0A CN117057302B (en) | 2023-10-12 | 2023-10-12 | Heuristic layout wiring method for circuit schematic diagram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311316090.0A CN117057302B (en) | 2023-10-12 | 2023-10-12 | Heuristic layout wiring method for circuit schematic diagram |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117057302A true CN117057302A (en) | 2023-11-14 |
| CN117057302B CN117057302B (en) | 2024-01-23 |
Family
ID=88661275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311316090.0A Active CN117057302B (en) | 2023-10-12 | 2023-10-12 | Heuristic layout wiring method for circuit schematic diagram |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117057302B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1963827A (en) * | 2006-12-08 | 2007-05-16 | 清华大学 | Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm |
| CN103279442A (en) * | 2013-06-14 | 2013-09-04 | 浪潮电子信息产业股份有限公司 | Message filtering system and message filtering method of high-speed interconnection bus |
| CN107527331A (en) * | 2017-09-26 | 2017-12-29 | 南京大学 | Polar region iceberg remote sensing recognition method based on double bubbling methods |
| US20210042830A1 (en) * | 2019-08-09 | 2021-02-11 | Ruon Global Ltd | User media platform server system |
| CN113659595A (en) * | 2021-07-27 | 2021-11-16 | 国创移动能源创新中心(江苏)有限公司 | Three-phase balance control method and device of alternating current charging system |
-
2023
- 2023-10-12 CN CN202311316090.0A patent/CN117057302B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1963827A (en) * | 2006-12-08 | 2007-05-16 | 清华大学 | Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm |
| CN103279442A (en) * | 2013-06-14 | 2013-09-04 | 浪潮电子信息产业股份有限公司 | Message filtering system and message filtering method of high-speed interconnection bus |
| CN107527331A (en) * | 2017-09-26 | 2017-12-29 | 南京大学 | Polar region iceberg remote sensing recognition method based on double bubbling methods |
| US20210042830A1 (en) * | 2019-08-09 | 2021-02-11 | Ruon Global Ltd | User media platform server system |
| CN113659595A (en) * | 2021-07-27 | 2021-11-16 | 国创移动能源创新中心(江苏)有限公司 | Three-phase balance control method and device of alternating current charging system |
Non-Patent Citations (1)
| Title |
|---|
| 丁华兴等: "《重叠隧道盾构掘进顺序对桥梁桩基的影响分析》", 《市政技术》, vol. 39, no. 10 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117057302B (en) | 2024-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4815003A (en) | Structured design method for high density standard cell and macrocell layout of VLSI chips | |
| CN106599519B (en) | The cut deal motherboard and slab collaborative design method and system of facing to manufacture order combination optimization | |
| CN110795908B (en) | Bus sensing overall wiring method driven by deviation | |
| CN106339350B (en) | The method and device thereof of many-core processor on piece memory access distance optimization | |
| CN106125671A (en) | A kind of multiclass pel hybrid process method for optimizing route | |
| JP4424494B2 (en) | Distribution system configuration optimization device and distribution system configuration optimization method | |
| CN115859899B (en) | Method for migrating multiple-driving-capability integrated circuit standard unit layout | |
| CN107247447A (en) | A kind of mixed-model assembly dispatch control method based on hybrid algorithm framework | |
| CN117057302B (en) | Heuristic layout wiring method for circuit schematic diagram | |
| CN112733486A (en) | Intelligent wiring method and system for chip design | |
| CN110059405A (en) | High-quality Steiner minimum tree construction method with differential evolution under X structure | |
| CN112183001B (en) | Hypergraph-based multistage clustering method for integrated circuits | |
| CN109639267B (en) | Method for optimizing number of inverters in XOR-majority logic diagram | |
| CN113268946A (en) | Chip layout method based on minimum connection sum | |
| CN103235849B (en) | The integrated circuit automatic wiring method that electric current drives and device | |
| CN112528592B (en) | Multi-stage optimization-based X-structure wiring method considering wiring resource relaxation | |
| CN109033510B (en) | Three-dimensional integrated circuit interconnection line length optimization method and device based on genetic algorithm | |
| Zhang et al. | Identity-linked group channel pruning for deep neural networks | |
| CN112800547B (en) | Layout optimization method and device for electric vehicle motor controller and storage medium | |
| CN114564905A (en) | Circuit schematic diagram layout and wiring method based on iterative tabu search algorithm | |
| CN111884566B (en) | Photovoltaic panel cluster wiring method | |
| CN111723420A (en) | Structural topology optimization method based on deep learning | |
| CN112836388B (en) | Offshore wind farm current collection circuit design method | |
| CN114612770B (en) | Article detection method based on convolutional neural network | |
| CN116911245B (en) | Layout method, system, equipment and storage medium of integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| OL01 | Intention to license declared |