CN117037893A - Microprocessor system for storing vector generator of chip tester - Google Patents
Microprocessor system for storing vector generator of chip tester Download PDFInfo
- Publication number
- CN117037893A CN117037893A CN202311290681.5A CN202311290681A CN117037893A CN 117037893 A CN117037893 A CN 117037893A CN 202311290681 A CN202311290681 A CN 202311290681A CN 117037893 A CN117037893 A CN 117037893A
- Authority
- CN
- China
- Prior art keywords
- address
- instruction
- jump
- operation code
- execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013598 vector Substances 0.000 title claims abstract description 40
- 238000012360 testing method Methods 0.000 claims abstract description 28
- 238000013507 mapping Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 8
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The invention relates to the technical field of memory testers, and discloses a microprocessor system for storing a vector generator of a chip tester, which comprises: instruction domain: parsing and execution of various instructions in processing vector generation; address field: generating an address of the memory device under test; data field: generating data of the memory device under test; control domain: the mapping relation between pin resources used for controlling the external DUT and internal channels of the tester; vector buffer: a timing module and a comparison module for receiving the generated vector and outputting to the outside; and (3) a microprocessor: the upper computer sends the instruction to an analysis module of the microprocessor; the analysis module analyzes the instruction to obtain an operation code and an operand, and sends the operation code and the operand to the execution module; the execution module executes different operations according to the classification of the operation codes, and the executed instructions and marks are output to an external address field and a data field through the output module. Compared with the prior art, the invention improves the working efficiency.
Description
Technical Field
The invention relates to the technical field of memory testers, in particular to a microprocessor system for storing a vector generator of a chip tester.
Background
Critical to the development of the integrated circuit industry is testing, which extends throughout the process of integrated circuit design, chip fabrication, packaging, and integrated circuit application. The main purpose of the test is to ensure that the device can completely realize the functions and performance indexes specified by the design specification under severe environmental conditions. The test contents can be categorized into two main categories: parameter testing and functional testing. The parameter test is mainly direct current parameter test, wherein voltage or current is applied to a DUT pin to measure a specific parameter value; the function test is a logic test, and a test for realizing the expected logic function is realized by applying predetermined stimulus according to a vector truth table.
The types of the test chips can be classified into SOC testers, analog testers, memory testers, and the like. The storage tester is different from the common SOC tester in that the test vector is large and the information to be stored is more. In the memory chip test equipment, the generation of test vectors is different from that of the common SOC test equipment, because a large number of test vectors are needed for the memory chip test, the types and the depths of the test vectors are different, but a certain rule is followed. And the common SOC test equipment has no obvious association relation between the address and the test data.
Disclosure of Invention
The present invention is directed to a microprocessor system for storing a vector generator of a chip tester, which is used for solving the above-mentioned technical problems.
The aim of the invention can be achieved by the following technical scheme:
a microprocessor system for storing a chip tester vector generator, comprising:
instruction domain: the method is used for analyzing and executing various instructions during vector generation, wherein the instructions comprise a loop instruction, a jump instruction, a matching instruction and a timing instruction;
address field: generating an address of the memory device under test;
data field: generating data of the memory device under test;
control domain: the mapping relation between pin resources used for controlling the external DUT and internal channels of the tester;
vector buffer: a timing module and a comparison module for receiving the generated vector and outputting to the outside;
and (3) a microprocessor: the upper computer is arranged in the instruction domain and sends the instruction to an analysis module of the microprocessor; the analysis module analyzes the instruction to obtain an operation code and an operand, and sends the operation code and the operand to the execution module; the execution module executes different operations according to the classification of the operation codes, and the executed instructions and marks are output to an external address field and a data field through the output module.
As a further scheme of the invention: the loop instruction specifically comprises the following steps:
reading the current operation code one by one;
if the current operation code is a loop instruction, recording a current loop starting address, wherein the current operand comprises a loop ending address and a loop number;
starting execution from a cycle start address, and subtracting one cycle number from the execution to an end address of the cycle;
if the number of times after the subtraction is not 0, the cycle is skipped from the end address of the cycle to the start address of the cycle, and then the cycle is executed sequentially until the number of times of the cycle is 0, and the cycle is ended.
As a further scheme of the invention: the jump instruction specifically comprises the following steps:
reading the current operation code one by one;
if the current operation code is a jump instruction, the jump instruction comprises conditional jump and direct jump;
if the jump instruction is a conditional jump, the operands are the start address and the end address of the sub-segment;
the next address of the current address is put into the stack, then the next address jumps to a new address execution sub-segment, when the sub-segment execution is finished, the address cached in the stack is released, and then the execution is started from the address;
if the jump instruction is a direct jump, the operand is the new address of the jump, and the new address after the jump is directly executed.
As a further scheme of the invention: the matching instruction specifically comprises the following steps:
reading the current operation code one by one;
if the current operation code is a matching instruction, the operand is a matched end address;
the address +1 starts to be executed, if the address +1 is matched, the execution is not continued, the matching section is directly jumped out, and the subsequent operation is executed;
if the matching is not successful until the matched end address, the method is directly ended.
As a further scheme of the invention: the timing instruction specifically comprises the following steps:
reading the current operation code one by one;
if the current operation code is a timing instruction, the operand is a timing time;
the timer starts timing, the address +1 starts executing, if the address +1 is matched, the timing is not continued, the timing operation is directly jumped out, and the subsequent operation is executed;
if the timer is timed until the condition that the timer does not accord with the setting condition finally occurs, the timer is directly ended.
The invention has the beneficial effects that: the design of the microprocessor increases the flexibility and intelligence of vector generation; for example, if we do not use the loop instruction, then the same vector is written in multiple times, which occupies storage space and increases workload of testers; the method also has the instructions of matching, timing and the like, so that the intelligence of the vector generator is improved; for example, a match instruction, which is expected to operate within a certain address range, indicates that the chip is operating properly, and if this instruction is not present, the subsequent test may be performed in the event that the chip is not operating properly, resulting in inaccurate results and wasted time for the tester.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the overall architecture of a microprocessor system for storing a vector generator of a chip tester according to the present invention;
FIG. 2 is a schematic diagram of the overall architecture of a microprocessor according to the present invention;
FIG. 3 is a flow chart of a loop instruction of the present invention;
FIG. 4 is a flow chart of a jump instruction of the present invention;
FIG. 5 is a flow chart of a match instruction of the present invention;
FIG. 6 is a flow chart of timing instructions of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to FIG. 1, the present invention is a microprocessor system for storing a vector generator of a chip tester, the whole structure of which is shown in FIG. 1, the whole vector generator has four parts, namely an instruction domain, an address domain, a data domain and a control domain;
the instruction domain is a module where a microprocessor is located, and has the main functions of analyzing and executing various instructions during vector generation, such as vector repetition, circulation, jump, timing and the like; the address field is used for generating an address of the tested storage device, and the address can be selected, calculated and the like according to an instruction of the instruction field; the data field is used for generating the data of the tested storage device, and the data can also be selected, calculated and the like according to the instructions of the instruction field; the control domain mainly controls the mapping relation between pin resources of an external DUT and internal channels of the tester, and the generated vector passes through the buffer and then outputs an external time sequence and comparison module.
The block diagram of the microprocessor is shown in fig. 2, the upper computer sends the instruction to the analysis module of the microprocessor through the gigabit network, the analysis module analyzes the instruction to obtain an operation code and an operand, then sends the operation code and the operand to the execution module, and the execution module executes different operations such as circulation, jump, matching, timing and the like according to the classification of the operation code, and the executed instruction and the mark are output to an external address field and a data field through the output module.
FIG. 3 is a flow chart of a loop, in which we read the current opcode one by one, and record the current loop start address if the current opcode is a loop instruction; the current operand includes the end address of the loop and the number of loops; sequentially executing downwards, and subtracting one cycle number when executing to the end address of the cycle; if the number of times after the subtraction is not 0, the address jumps to the start address of the loop and then is sequentially executed until the number of times of the loop is 0, the loop is ended, and other operations are continuously executed until the end.
FIG. 4 is a jump flow chart, we read the current opcode one by one, if the current opcode is a jump instruction, the jump instruction is split into two types, conditional jump and direct jump; if the instruction is a conditional jump instruction, the operand is the starting address and the ending address of the sub-segment, the next address of the current address is put into the stack, then the sub-segment is executed by jumping to a new address, when the execution of the sub-segment is ended, the address cached in the stack is released, and then the execution is started from the address; if the jump instruction is a direct jump, the operand is the new address of the jump, then the program directly executes the new address after the jump; and continuing to execute other operations until the end.
FIG. 5 is a flow chart of a match, which means that a vector meeting the set condition can be found in a section of address after the current address; reading the current operation code one by one, and if the current operation code is a matching instruction; the operand is the matched end address; the address +1 starts to be executed, if the address +1 is matched, the execution is not continued, the matching section is directly jumped out, and the subsequent operation is executed; if the match is not successful until the matched end address, then the process is ended directly.
FIG. 6 is a timing flow diagram, timing being the ability to find vectors that meet a set condition over a period of time; reading the current operation code one by one, and if the current operation code is a timing instruction; the operand is a timing time; the timer starts timing, the address +1 starts executing, if the address +1 is matched, the timing is not continued, the timing operation is directly jumped out, and the subsequent operation is executed; if the timer times to the last that the condition is not met, the method is directly finished.
As can be seen from the several instructions above, the design of the microprocessor increases the flexibility and intelligence of vector generation. For example, if we do not use this instruction, then the same vector is written multiple times in the vector, which occupies storage space and increases tester workload. And also the instructions of matching, timing, etc., increases the intelligence of the vector generator. For example, a match instruction, which is expected to operate within a certain address range, indicates that the chip is operating properly, and if this instruction is not present, the subsequent test may be performed in the event that the chip is not operating properly, resulting in inaccurate results and wasted time for the tester.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (5)
1. A microprocessor system for storing a chip tester vector generator, comprising:
instruction domain: the method is used for analyzing and executing various instructions during vector generation, wherein the instructions comprise a loop instruction, a jump instruction, a matching instruction and a timing instruction;
address field: generating an address of the memory device under test;
data field: generating data of the memory device under test;
control domain: the mapping relation between pin resources used for controlling the external DUT and internal channels of the tester;
vector buffer: a timing module and a comparison module for receiving the generated vector and outputting to the outside;
and (3) a microprocessor: the upper computer is arranged in the instruction domain and sends the instruction to an analysis module of the microprocessor; the analysis module analyzes the instruction to obtain an operation code and an operand, and sends the operation code and the operand to the execution module; the execution module executes different operations according to the classification of the operation codes, and the executed instructions and marks are output to an external address field and a data field through the output module.
2. A microprocessor system for storing a vector generator of a chip tester as claimed in claim 1, wherein said loop instruction comprises the steps of:
reading the current operation code one by one;
if the current operation code is a loop instruction, recording a current loop starting address, wherein the current operand comprises a loop ending address and a loop number;
starting execution from a cycle start address, and subtracting one cycle number from the execution to an end address of the cycle;
if the number of times after the subtraction is not 0, the cycle is skipped from the end address of the cycle to the start address of the cycle, and then the cycle is executed sequentially until the number of times of the cycle is 0, and the cycle is ended.
3. A microprocessor system for storing a vector generator of a chip tester as claimed in claim 1, wherein said jump instruction comprises the steps of:
reading the current operation code one by one;
if the current operation code is a jump instruction, the jump instruction comprises conditional jump and direct jump;
if the jump instruction is a conditional jump, the operands are the start address and the end address of the sub-segment;
the next address of the current address is put into the stack, then the next address jumps to a new address execution sub-segment, when the sub-segment execution is finished, the address cached in the stack is released, and then the execution is started from the address;
if the jump instruction is a direct jump, the operand is the new address of the jump, and the new address after the jump is directly executed.
4. A microprocessor system for storing a vector generator of a chip tester as claimed in claim 1, wherein said match instruction comprises the steps of:
reading the current operation code one by one;
if the current operation code is a matching instruction, the operand is a matched end address;
the address +1 starts to be executed, if the address +1 is matched, the execution is not continued, the matching section is directly jumped out, and the subsequent operation is executed;
if the matching is not successful until the matched end address, the method is directly ended.
5. A microprocessor system for storing a vector generator of a chip tester as claimed in claim 1, wherein said timing instructions comprise the steps of:
reading the current operation code one by one;
if the current operation code is a timing instruction, the operand is a timing time;
the timer starts timing, the address +1 starts executing, if the address +1 is matched, the timing is not continued, the timing operation is directly jumped out, and the subsequent operation is executed;
if the timer is timed until the condition that the timer does not accord with the setting condition finally occurs, the timer is directly ended.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311290681.5A CN117037893A (en) | 2023-10-08 | 2023-10-08 | Microprocessor system for storing vector generator of chip tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311290681.5A CN117037893A (en) | 2023-10-08 | 2023-10-08 | Microprocessor system for storing vector generator of chip tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117037893A true CN117037893A (en) | 2023-11-10 |
Family
ID=88645203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311290681.5A Pending CN117037893A (en) | 2023-10-08 | 2023-10-08 | Microprocessor system for storing vector generator of chip tester |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117037893A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883905A (en) * | 1997-02-18 | 1999-03-16 | Schlumberger Technologies, Inc. | Pattern generator with extended register programming |
| TW533313B (en) * | 1998-10-30 | 2003-05-21 | Advantest Corp | Method and structure for testing embedded cores based system-on-a-chip |
| US6671844B1 (en) * | 2000-10-02 | 2003-12-30 | Agilent Technologies, Inc. | Memory tester tests multiple DUT's per test site |
| US20050086650A1 (en) * | 1999-01-28 | 2005-04-21 | Ati International Srl | Transferring execution from one instruction stream to another |
| US7424658B1 (en) * | 2002-07-01 | 2008-09-09 | Altera Corporation | Method and apparatus for testing integrated circuits |
| CN102737725A (en) * | 2011-04-13 | 2012-10-17 | 复旦大学 | Programmable built-in self testing system capable of automatic optimization on memory performance and built-in self testing method |
| CN114428642A (en) * | 2022-02-23 | 2022-05-03 | 中电科申泰信息科技有限公司 | Random instruction generation environment based on novel processor architecture |
-
2023
- 2023-10-08 CN CN202311290681.5A patent/CN117037893A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883905A (en) * | 1997-02-18 | 1999-03-16 | Schlumberger Technologies, Inc. | Pattern generator with extended register programming |
| TW533313B (en) * | 1998-10-30 | 2003-05-21 | Advantest Corp | Method and structure for testing embedded cores based system-on-a-chip |
| US20050086650A1 (en) * | 1999-01-28 | 2005-04-21 | Ati International Srl | Transferring execution from one instruction stream to another |
| US6671844B1 (en) * | 2000-10-02 | 2003-12-30 | Agilent Technologies, Inc. | Memory tester tests multiple DUT's per test site |
| US7424658B1 (en) * | 2002-07-01 | 2008-09-09 | Altera Corporation | Method and apparatus for testing integrated circuits |
| CN102737725A (en) * | 2011-04-13 | 2012-10-17 | 复旦大学 | Programmable built-in self testing system capable of automatic optimization on memory performance and built-in self testing method |
| CN114428642A (en) * | 2022-02-23 | 2022-05-03 | 中电科申泰信息科技有限公司 | Random instruction generation environment based on novel processor architecture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5202889A (en) | Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs | |
| EP1783503A1 (en) | Tester and testing method | |
| US6820222B2 (en) | Apparatus and method for processor power measurement in a digital signal processor using trace data and simulation techniques | |
| CN105190334A (en) | Method and apparatus for device testing using multiple processing paths | |
| US11507348B2 (en) | Method and apparatus for generating chip-based computing function, device, and storage medium | |
| CN112444731B (en) | Chip testing method and device, processor chip and server | |
| US20030053358A1 (en) | Dft technique for avoiding contention/conflict in logic built-in self-test | |
| CN114637638B (en) | Templated memory test pattern generator and method | |
| CN111045880A (en) | Chip testing method, verification system and storage medium | |
| CN113641545B (en) | Automatic learning method and system for digital test vectors | |
| US20060161828A1 (en) | Digital logic test method to systematically approach functional coverage completely and related apparatus and system | |
| US11054469B2 (en) | Integrated circuit test apparatus and method | |
| CN109783837A (en) | Emulator, analogue system, emulation mode and simulated program | |
| US6842712B2 (en) | Method for testing an electronic component; computer program product, computer readable medium, and computer embodying the method; and method for downloading the program embodying the method | |
| CN117037893A (en) | Microprocessor system for storing vector generator of chip tester | |
| CN112100015A (en) | Chip testing device and chip testing method | |
| US9478313B2 (en) | Fast semantic processor for Per-pin APG | |
| US6536020B2 (en) | Efficient generation of optimum test data | |
| KR101229677B1 (en) | Method and apparatus for the determination of a repetitive bit value pattern | |
| KR100277770B1 (en) | Sequence control circuit | |
| EP2820547B1 (en) | Debugging method and computer program product | |
| CN113535545A (en) | Binary pile inserting method for program dynamic analysis | |
| JP2001014893A (en) | Pattern generator and electric parts testing device | |
| JPH096646A (en) | Program simulation device | |
| KR102308990B1 (en) | Apparatus and method for generating semiconductor test pattern |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |