CN116955040A - Chip read-write performance test method, system, equipment and storage medium - Google Patents
Chip read-write performance test method, system, equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the application provides a chip read-write performance test method, a system, equipment and a storage medium, belongs to the technical field of chip test, and aims to solve the technical problem that the existing chip read-write performance test method is low in efficiency. Comprising the following steps: acquiring chip attribute information of a chip to be detected; processing the chip attribute information based on the SOC framework to generate a chip detection file; detecting the chip to be detected based on the chip detection file, and generating test data; judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure. The automatic detection of the chip quality is realized, so that the chip with poor chip quality is intercepted and screened, the difficulty that the traditional read-write performance test method consumes a great deal of time and effort of an engineer and has low test efficiency is solved, and the use experience of a user is improved.
Description
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a method, a system, an apparatus, and a storage medium for testing read-write performance of a chip.
Background
In chip design, besides the functional requirements, the most important point is the performance requirements of chip data transmission, which is also a very important parameter of the chip. At present, the read-write performance test of the interface in chip verification is generally performed at important chip design nodes, and the main process is based on a simulation environment, wherein a specific amount of data is sent through a test case, then a carrier wave shape is downloaded, and the time for manually calculating the data is spent, so that the bandwidth of the corresponding interface is estimated.
Along with the rapid increase of the chip scale, the functional modules of the chip are more and more complex, and interface protocols among the modules are more and more, such as an APB protocol, a PCIE protocol, a DDR protocol and the like, the traditional read-write performance test method can consume a great deal of time and effort of engineers, and visual performance data cannot be timely given out when the design of the modules is changed. Therefore, a strategy capable of automatically detecting the read-write performance of the chip is needed.
Disclosure of Invention
The embodiment of the application provides a chip read-write performance test method, a system, equipment and a storage medium, which are used for solving the technical problem of low efficiency of the existing chip read-write performance test method.
The application aims to provide a scientific, reasonable and efficient chip read-write performance test method based on chip attributes, which can judge the chip quality of a chip to be detected according to one or more parameters in the attribute information of the chip to be detected by acquiring the chip attribute information of the chip to be detected, and can simply and rapidly automatically detect the chip quality so as to intercept and screen the chip with poor chip quality, thereby fundamentally solving the technical problems that the traditional read-write performance test method consumes a great deal of time and effort of engineers and has low test efficiency, greatly improving the efficiency of the chip read-write performance test and improving the use experience of users. The following specifically describes a method, a system, a device and a storage medium for testing read-write performance of a chip provided by the embodiment of the application.
The embodiment of the application provides a method for testing read-write performance of a chip, which comprises the following steps: acquiring chip attribute information of a chip to be detected; processing the chip attribute information based on the SOC framework to generate a chip detection file; detecting the chip to be detected based on the chip detection file, and generating test data; judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
In one implementation manner of the present application, in the foregoing method for testing read-write performance of a chip, the process of processing the chip attribute information based on the SOC framework specifically includes: integrating the register information related to each IP core in a linked list form, and storing the register information into each IP attribute file; according to the SOC framework, adding IP attribute files corresponding to IP cores required by the SOC framework, obtaining corresponding base address values of each IP core in the SOC framework, and modifying the base address of each corresponding IP core in each IP attribute file according to the obtained base address values; and integrating the modified IP attribute files through a linked list form organization and storing the modified IP attribute files to form a chip attribute file.
In an implementation manner of the present application, a method for testing read-write performance of a chip as described above, the method further includes: and forming a corresponding register file according to the required register information of each IP core in the integrated verification stage of the SOC framework design process through the chip attribute file, wherein one IP core corresponds to one register file.
In one implementation manner of the present application, as the foregoing method for testing the read-write performance of a chip, the determining that the type of the read-write performance abnormality is a single-bit failure process specifically includes: judging whether the row value and the column number value of the storage unit corresponding to the abnormal test data are unique; and if the row value and the column value are unique, determining that the abnormal type of the read-write performance is single-bit failure.
In one implementation manner of the present application, as the foregoing method for testing the read-write performance of a chip, the determining that the type of the read-write performance abnormality is a local failure process specifically includes: judging that the row value and the column number value of the storage unit corresponding to the abnormal test data are not unique, and determining that the abnormal type of the read-write performance is local failure; wherein the local failure comprises: unfilled corner cracks, blockiness, and non-blockiness.
In one implementation manner of the present application, as the foregoing method for testing the read-write performance of a chip, the process of determining that a local failure is an unfilled corner crack abnormality is specifically: determining the read-write function abnormality of the chip to be detected based on the abnormal test data, and obtaining the position information of a storage unit with the read-write function abnormality on the abnormal chip; obtaining the distribution of the memory units with abnormal read-write functions on the chip according to the position information, and judging the abnormal read-write performance type as unfilled-corner crack abnormality if the memory units with abnormal read-write functions are a plurality of rows or columns of memory units from the edge of the abnormal chip to the center of the abnormal chip; and determining that the memory unit with abnormal read-write function is a multi-row or multi-column memory unit of an abnormal chip, judging that the read-write performance abnormality type is blocky abnormality, and otherwise, judging that the read-write performance abnormality type is non-blocky abnormality.
In an implementation manner of the present application, in the foregoing method for testing read-write performance of a chip, the chip attribute information of the chip to be tested includes: the method comprises the steps of IP core name, IP core base address, IP core abstract, IP core usage description register name, register abstract, register usage description, register occupied space size, register offset address, register bit section name, start and stop range of each register bit section, register bit section read-write attribute, register bit section reset value, register bit section abstract and register bit section usage description.
The embodiment of the application also provides a system for testing the read-write performance of the chip, which comprises: the attribute acquisition unit is used for acquiring chip attribute information of the chip to be detected; the detection file generation unit is used for processing the chip attribute information based on the SOC framework to generate a chip detection file; the detection unit is used for detecting the chip to be detected based on the chip detection file and generating test data; an anomaly type judging unit for judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on the abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
The embodiment of the application also provides a chip read-write performance test device, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to: acquiring chip attribute information of a chip to be detected; processing the chip attribute information based on the SOC framework to generate a chip detection file; detecting the chip to be detected based on the chip detection file, and generating test data; judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
The embodiment of the application also provides a nonvolatile computer storage medium for testing the read-write performance of the chip, which stores computer executable instructions, wherein the computer executable instructions are set as follows: acquiring chip attribute information of a chip to be detected; processing the chip attribute information based on the SOC framework to generate a chip detection file; detecting the chip to be detected based on the chip detection file, and generating test data; judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
According to the chip read-write performance testing method, system, device and storage medium provided by the embodiment of the application, the chip attribute information of the chip to be detected is obtained, then the attribute information is processed according to the SOC framework, then the read-write performance of the chip is tested by generating the test file, and the type of the read-write performance abnormality of the chip is judged based on the abnormal condition of the test data. The automatic detection of the chip quality is simply and quickly realized, so that the chip with poor chip quality is intercepted and screened, the technical problems that the traditional read-write performance test method consumes a great deal of time and effort of an engineer and has low test efficiency are solved, the efficiency of the read-write performance test of the chip is greatly improved, and the use experience of a user is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a flow chart of a method for testing read-write performance of a chip according to an embodiment of the present application;
FIG. 2 is a diagram showing the components of a system for testing the read-write performance of a chip according to an embodiment of the present application;
fig. 3 is a schematic diagram of a chip read-write performance test device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In chip design, besides the functional requirements, the most important point is the performance requirements of chip data transmission, which is also a very important parameter of the chip. At present, the read-write performance test of the interface in chip verification is generally performed at important chip design nodes, and the main process is based on a simulation environment, wherein a specific amount of data is sent through a test case, then a carrier wave shape is downloaded, and the time for manually calculating the data is spent, so that the bandwidth of the corresponding interface is estimated.
Along with the rapid increase of the chip scale, the functional modules of the chip are more and more complex, and interface protocols among the modules are more and more, such as an APB protocol, a PCIE protocol, a DDR protocol and the like, the traditional read-write performance test method can consume a great deal of time and effort of engineers, and visual performance data cannot be timely given out when the design of the modules is changed. Therefore, a strategy capable of automatically detecting the read-write performance of the chip is needed.
The embodiment of the application aims to provide a scientific, reasonable and efficient chip read-write performance test method based on chip attributes, which can judge the chip quality of a chip to be detected according to one or more parameters in the attribute information of the chip to be detected by acquiring the chip attribute information of the chip to be detected, and can simply and quickly automatically detect the chip quality so as to intercept and screen the chip with poor chip quality, thereby fundamentally solving the technical problems that the traditional read-write performance test method consumes a great deal of time and effort of engineers and has low test efficiency, greatly improving the efficiency of the chip read-write performance test and improving the use experience of users.
The embodiment of the application provides a chip read-write performance test method, a system, equipment and a storage medium, which are used for solving the technical problem of low efficiency of the existing chip read-write performance test method.
The following describes the technical scheme provided by the embodiment of the application in detail through the attached drawings.
Fig. 1 is a flowchart of a method for testing read-write performance of a chip according to an embodiment of the present application. As shown in fig. 1, the method mainly comprises the following steps:
and 101, acquiring chip attribute information of a chip to be detected.
In the embodiment of the application, the acquisition of the chip attribute information is realized through the bottom node value of the register, the bottom node value can refer to a port for calling the register value, the bottom node value corresponds to the register one by one, and the value of the register can be acquired by reading the bottom node value. The bottom node value may be pre-created and stored in the test software, and may include, but is not limited to, a chip model number, a node number, etc. for distinguishing the identification information of the bottom node.
Specifically, the electronic device may send an instruction to the bottom node to invoke reading of the value of the bottom node, and read the register by obtaining the value of the bottom node, so as to obtain the value of the register. The electronic device may be a computer, an iPad, or other device that may be electrically connected to the terminal to be detected.
In the embodiment of the present application, the chip attribute information of the chip to be detected includes, but is not limited to: the method comprises the steps of IP core name, IP core base address, IP core abstract, IP core usage description register name, register abstract, register usage description, register occupied space size, register offset address, register bit section name, start and stop range of each register bit section, register bit section read-write attribute, register bit section reset value, register bit section abstract and register bit section usage description. The chip attribute information refers to parameters for characterizing the health condition of the chip itself to be detected. It is understood that the chip quality may be directly determined using the chip attribute information, or may be used as auxiliary information for determining the chip quality.
It should be noted that, the register may store attribute information of the chip to be detected, and one of the parameters in the attribute information of the chip may be represented by a value of one or more registers. The attribute information of the chip can be obtained by reading the value of each bit of the register. The chip attribute information parameters corresponding to the values of one or more bits of the register can be fixed, and the attribute information of the chip to be detected can be identified by acquiring the chip attribute information corresponding to the value of each bit of the register in advance and confirming the value of the register.
And 102, processing the chip attribute information based on the SOC framework to generate a chip detection file.
In the embodiment of the application, the process of processing the chip attribute information based on the SOC framework specifically comprises the following steps: integrating the register information related to each IP core in a linked list form, and storing the register information into each IP attribute file; according to the SOC framework, adding IP attribute files corresponding to IP cores required by the SOC framework, obtaining corresponding base address values of each IP core in the SOC framework, and modifying the base address of each corresponding IP core in each IP attribute file according to the obtained base address values; and integrating the modified IP attribute files through a linked list form organization and storing the modified IP attribute files to form a chip attribute file.
Further, through the chip attribute file, according to the register information related to each IP core required in the integrated verification stage of the SOC architecture design process, the required register information related to each IP core is formed into a corresponding register file, and one IP core corresponds to one register file.
And 103, detecting the chip to be detected based on the chip detection file, and generating test data.
In the embodiment of the application, the chip detection file comprises a bin file. The bin is a binary file, and the attribute information of a chip can be correspondingly generated into a bin file, and the attribute information of the chip can be analyzed and judged through the bin file. In an embodiment, the code for analyzing and judging the attribute information can be written in a programming tool, and then the code is compiled to generate a bin file. The bin file can be stored in the electronic equipment, and the attribute information of the chip can be analyzed and judged by calling the bin file.
Further, the chip test file is used for testing the chip, and then generating test data, wherein the test data is divided into normal data and abnormal data.
In the embodiment of the application, the HASH value of the bin file of the whole user firmware program is calculated and then transmitted to the SOC chip; after receiving and processing all upgrade packages of the bin file, the SOC chip reads the bin file data stored in the FLASH memory in a local package, and uses a Hash algorithm of the SM3 cryptographic key to calculate the HASH value of the whole received bin file in a sectional manner, and then compares the HASH value with a HASH value result calculated by an upper computer; if the two are the same, the data of the bin file received by the SOC chip is correct and complete, and the upgraded user program can normally run; otherwise, the file data content of the bin file is wrong, or all data are not received, or the data packet is lost in the transmission process, or the data content is modified in the transmission process. In the embodiment of the application, through adding the step, the correctness verification of the data content of the bin file can be realized, whether the received bin file is tampered or not is detected, and the authenticity and the reliability of the data source are ensured in the whole process of the chip read-write performance test, so that the accuracy of the chip read-write performance test is integrally improved.
And 104, judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on the abnormal test data.
In the embodiment of the present application, the read-write performance exception types include: single bit failure, partial failure.
Further, the process of determining the abnormal type of the read-write performance as single-bit failure specifically comprises the following steps: judging whether the row value and the column number value of the storage unit corresponding to the abnormal test data are unique; and if the row value and the column value are unique, determining that the abnormal type of the read-write performance is single-bit failure.
Further, the process of determining the abnormal type of the read-write performance as the local failure specifically comprises the following steps: judging that the row value and the column number value of the storage unit corresponding to the abnormal test data are not unique, and determining that the abnormal type of the read-write performance is local failure; wherein the local failure comprises: unfilled corner cracks, blockiness, and non-blockiness.
Further, the process of determining the local failure as the unfilled corner crack abnormality is specifically as follows: determining the read-write function abnormality of the chip to be detected based on the abnormal test data, and obtaining the position information of a storage unit with the read-write function abnormality on the abnormal chip; obtaining the distribution of the memory units with abnormal read-write functions on the chip according to the position information, and judging the abnormal read-write performance type as unfilled-corner crack abnormality if the memory units with abnormal read-write functions are a plurality of rows or columns of memory units from the edge of the abnormal chip to the center of the abnormal chip; and determining that the memory unit with abnormal read-write function is a multi-row or multi-column memory unit of an abnormal chip, judging that the read-write performance abnormality type is blocky abnormality, and otherwise, judging that the read-write performance abnormality type is non-blocky abnormality.
According to the chip read-write performance testing method provided by the embodiment of the application, the chip attribute information of the chip to be detected is obtained, then the attribute information is processed according to the SOC framework, then the read-write performance of the chip is tested by generating the test file, and the type of the abnormality of the read-write performance of the chip is judged based on the abnormality of the test data. The automatic detection of the chip quality is simply and quickly realized, so that the chip with poor chip quality is intercepted and screened, the technical problems that the traditional read-write performance test method consumes a great deal of time and effort of an engineer and has low test efficiency are solved, the efficiency of the read-write performance test of the chip is greatly improved, and the use experience of a user is improved.
The foregoing is a method for testing read-write performance of a chip according to an embodiment of the present application, and based on the same inventive concept, the embodiment of the present application further provides a system for testing read-write performance of a chip, and fig. 2 is a composition diagram of the system for testing read-write performance of a chip according to an embodiment of the present application, as shown in fig. 2, where the system mainly includes: an attribute obtaining unit 201, configured to obtain chip attribute information of a chip to be detected; a detection file generating unit 202, configured to process the chip attribute information based on the SOC framework, and generate a chip detection file; the detecting unit 203 is configured to detect the chip to be detected based on the chip detection file, and generate test data; an anomaly type determining unit 204, configured to determine a read-write performance anomaly type of the memory unit of the chip to be detected based on the anomaly test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
In the embodiment of the present application, the abnormality type determination unit 204 specifically performs: judging whether the row value and the column number value of the storage unit corresponding to the abnormal test data are unique; and if the row value and the column value are unique, determining that the abnormal type of the read-write performance is single-bit failure.
The abnormality type determination unit 204 is also configured to perform: judging that the row value and the column number value of the storage unit corresponding to the abnormal test data are not unique, and determining that the abnormal type of the read-write performance is local failure; wherein the local failure comprises: unfilled corner cracks, blockiness, and non-blockiness.
The abnormality type determination unit 204 is also configured to perform: determining the read-write function abnormality of the chip to be detected based on the abnormal test data, and obtaining the position information of a storage unit with the read-write function abnormality on the abnormal chip; obtaining the distribution of the memory units with abnormal read-write functions on the chip according to the position information, and judging the abnormal read-write performance type as unfilled-corner crack abnormality if the memory units with abnormal read-write functions are a plurality of rows or columns of memory units from the edge of the abnormal chip to the center of the abnormal chip; and determining that the memory unit with abnormal read-write function is a multi-row or multi-column memory unit of an abnormal chip, judging that the read-write performance abnormality type is blocky abnormality, and otherwise, judging that the read-write performance abnormality type is non-blocky abnormality.
According to the chip read-write performance test system provided by the embodiment of the application, the chip attribute information of the chip to be detected is obtained, then the attribute information is processed according to the SOC framework, then the read-write performance of the chip is tested by generating the test file, and the type of the abnormality of the read-write performance of the chip is judged based on the abnormality of the test data. The automatic detection of the chip quality is simply and quickly realized, so that the chip with poor chip quality is intercepted and screened, the technical problems that the traditional read-write performance test method consumes a great deal of time and effort of an engineer and has low test efficiency are solved, the efficiency of the read-write performance test of the chip is greatly improved, and the use experience of a user is improved.
The foregoing is a system for testing read-write performance of a chip according to the embodiment of the present application, and based on the same inventive concept, the embodiment of the present application further provides a device for testing read-write performance of a chip, and fig. 3 is a schematic diagram of a device for testing read-write performance of a chip according to the embodiment of the present application, as shown in fig. 3, where the device mainly includes: at least one processor 301; and a memory 302 communicatively coupled to the at least one processor; wherein the memory 302 stores instructions executable by the at least one processor 301, the instructions being executable by the at least one processor 301 to enable the at least one processor 301 to: acquiring a value of a register corresponding to a chip to be detected in real time based on a pre-established bottom node value; acquiring chip attribute information of the chip to be detected based on the value of the register; generating a bin file for analyzing the attribute information of the chip to be detected, and detecting the chip quality of the chip to be detected based on the chip attribute information of the chip to be detected and the bin file.
In addition, the embodiment of the application also provides a nonvolatile computer storage medium for testing the read-write performance of the chip, which stores computer executable instructions, wherein the computer executable instructions are configured to: acquiring a value of a register corresponding to a chip to be detected in real time based on a pre-established bottom node value; acquiring chip attribute information of the chip to be detected based on the value of the register; generating a bin file for analyzing the attribute information of the chip to be detected, and detecting the chip quality of the chip to be detected based on the chip attribute information of the chip to be detected and the bin file.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The embodiments of the present application are described in a progressive manner, and the same and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in the differences from the other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (10)
1. A method for testing the read-write performance of a chip is characterized by comprising the following steps:
acquiring chip attribute information of a chip to be detected;
processing the chip attribute information based on the SOC framework to generate a chip detection file;
detecting the chip to be detected based on the chip detection file, and generating test data;
judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
2. The method for testing the read-write performance of the chip according to claim 1, wherein the processing of the chip attribute information based on the SOC framework specifically comprises:
integrating the register information related to each IP core in a linked list form, and storing the register information into each IP attribute file;
according to the SOC framework, adding IP attribute files corresponding to IP cores required by the SOC framework, obtaining corresponding base address values of each IP core in the SOC framework, and modifying the base address of each corresponding IP core in each IP attribute file according to the obtained base address values;
and integrating the modified IP attribute files through a linked list form organization and storing the modified IP attribute files to form a chip attribute file.
3. The method for testing read-write performance of a chip according to claim 2, further comprising:
and forming a corresponding register file according to the required register information of each IP core in the integrated verification stage of the SOC framework design process through the chip attribute file, wherein one IP core corresponds to one register file.
4. The method for testing the read-write performance of the chip according to claim 1, wherein the determining that the read-write performance anomaly type is a single-bit failure process comprises:
judging whether the row value and the column number value of the storage unit corresponding to the abnormal test data are unique;
and if the row value and the column value are unique, determining that the abnormal type of the read-write performance is single-bit failure.
5. The method for testing the read-write performance of the chip according to claim 1, wherein the determining that the read-write performance anomaly type is a local failure comprises:
judging that the row value and the column number value of the storage unit corresponding to the abnormal test data are not unique, and determining that the abnormal type of the read-write performance is local failure; wherein the local failure comprises: unfilled corner cracks, blockiness, and non-blockiness.
6. The method for testing the read-write performance of a chip according to claim 5, wherein the determining that the local failure is an unfilled corner crack abnormality comprises:
determining the read-write function abnormality of the chip to be detected based on the abnormal test data, and obtaining the position information of a storage unit with the read-write function abnormality on the abnormal chip;
obtaining the distribution of the memory units with abnormal read-write functions on the chip according to the position information, and judging the abnormal read-write performance type as unfilled-corner crack abnormality if the memory units with abnormal read-write functions are a plurality of rows or columns of memory units from the edge of the abnormal chip to the center of the abnormal chip;
and determining that the memory unit with abnormal read-write function is a multi-row or multi-column memory unit of an abnormal chip, judging that the read-write performance abnormality type is blocky abnormality, and otherwise, judging that the read-write performance abnormality type is non-blocky abnormality.
7. The method for testing read-write performance of a chip according to claim 1, wherein the chip attribute information of the chip to be tested includes: the method comprises the steps of IP core name, IP core base address, IP core abstract, IP core usage description register name, register abstract, register usage description, register occupied space size, register offset address, register bit section name, start and stop range of each register bit section, register bit section read-write attribute, register bit section reset value, register bit section abstract and register bit section usage description.
8. A system for testing read-write performance of a chip, the system comprising:
the attribute acquisition unit is used for acquiring chip attribute information of the chip to be detected;
the detection file generation unit is used for processing the chip attribute information based on the SOC framework to generate a chip detection file;
the detection unit is used for detecting the chip to be detected based on the chip detection file and generating test data;
an anomaly type judging unit for judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on the abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
9. A chip read-write performance test apparatus, the apparatus comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to: acquiring chip attribute information of a chip to be detected;
processing the chip attribute information based on the SOC framework to generate a chip detection file;
detecting the chip to be detected based on the chip detection file, and generating test data;
judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
10. A non-volatile computer storage medium storing computer executable instructions for chip read-write performance testing, the computer executable instructions configured to: acquiring chip attribute information of a chip to be detected;
processing the chip attribute information based on the SOC framework to generate a chip detection file;
detecting the chip to be detected based on the chip detection file, and generating test data;
judging the abnormal type of the read-write performance of the storage unit of the chip to be detected based on abnormal test data; wherein, the read-write performance exception types include: single bit failure, partial failure.
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