CN116864509A - Photoelectric integrated silicon optical chip, preparation method thereof and semiconductor device - Google Patents

Photoelectric integrated silicon optical chip, preparation method thereof and semiconductor device Download PDF

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Publication number
CN116864509A
CN116864509A CN202310823317.4A CN202310823317A CN116864509A CN 116864509 A CN116864509 A CN 116864509A CN 202310823317 A CN202310823317 A CN 202310823317A CN 116864509 A CN116864509 A CN 116864509A
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CN
China
Prior art keywords
silicon
integrated
insulator substrate
circuit component
substrate
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CN202310823317.4A
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Chinese (zh)
Inventor
孙旭
刘晟昊
胡朝阳
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Suzhou Haiguang Xinchuang Photoelectric Technology Co ltd
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Suzhou Haiguang Xinchuang Photoelectric Technology Co ltd
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Application filed by Suzhou Haiguang Xinchuang Photoelectric Technology Co ltd filed Critical Suzhou Haiguang Xinchuang Photoelectric Technology Co ltd
Priority to CN202310823317.4A priority Critical patent/CN116864509A/en
Publication of CN116864509A publication Critical patent/CN116864509A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application relates to the field of semiconductors, and discloses an optoelectronic integrated silicon optical chip, a preparation method thereof and a semiconductor device, wherein the optoelectronic integrated silicon optical chip comprises the following components: a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a base, an insulating layer and a monocrystalline silicon layer which are laminated from bottom to top; an integrated optical circuit component provided in the region of the single crystal silicon layer; an integrated circuit component disposed in the substrate region; a through silicon via; the through silicon vias penetrate through the silicon on insulator substrate in the thickness direction of the silicon on insulator substrate; the first conductive interconnection structure is arranged on the upper surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via; and the second conductive interconnection structure is arranged on the lower surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via. In the application, the integrated circuit component and the integrated circuit component are arranged on the silicon-on-insulator substrate, and the integrated circuit component is arranged on the lower surface, so that the manufacturing process can be simplified, the difficulty of the manufacturing process can be reduced, and the processing yield can be improved.

Description

Photoelectric integrated silicon optical chip, preparation method thereof and semiconductor device
Technical Field
The application relates to the field of semiconductors, in particular to an optoelectronic integrated silicon optical chip, a preparation method thereof and a semiconductor device.
Background
Silicon optical technology is a technology in which devices such as modulators, detectors, passive filters, etc. are integrated on a silicon-based chip.
The structure schematic diagram of the monolithically integrated optoelectronic integrated chip is shown in fig. 1, and integrated circuit components and integrated optical path components are directly processed on a wafer through a semiconductor chip processing technology, so that the monolithic integrated optoelectronic integrated chip has the advantages of low mass production cost and high integration level. However, since the integrated optical circuit can only be fabricated on silicon-on-insulator (SOI), whereas the conventional CMOS (Complementary Metal Oxide Semiconductor ) process employs a silicon process, the current silicon optical chip fabrication process is not matched with the conventional CMOS process fabrication route. Therefore, when the monolithically integrated optoelectronic integrated chip is manufactured, the insulating material on the silicon on the insulator needs to be removed in the processing area of the electrical chip, and then the processing technology of the CMOS chip is performed.
Therefore, how to solve the above technical problems should be of great interest to those skilled in the art.
Disclosure of Invention
The application aims to provide an optoelectronic integrated silicon optical chip, a preparation method thereof and a semiconductor device, so as to reduce the processing complexity and difficulty of the optoelectronic integrated silicon optical chip and improve the yield.
In order to solve the above technical problems, the present application provides an optoelectronic integrated silicon optical chip, comprising:
a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a base, an insulating layer and a monocrystalline silicon layer which are laminated from bottom to top;
an integrated optical circuit component provided in the single crystal silicon layer region;
an integrated circuit component disposed in the base region;
a through silicon via; the through silicon vias penetrate through the silicon on insulator substrate in the thickness direction of the silicon on insulator substrate;
the first conductive interconnection structure is arranged on the upper surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via;
and the second conductive interconnection structure is arranged on the lower surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via.
Optionally, the method further comprises:
and the bonding pad is arranged on the outer surface of the photoelectric integrated silicon optical chip.
Optionally, when the packaging mode of the optoelectronic integrated silicon optical chip is gold wire bonding packaging, the bonding pad is electrically connected with the first conductive interconnection structure or the second conductive interconnection structure.
Optionally, when the packaging mode of the optoelectronic integrated silicon optical chip is a flip-chip packaging mode, at least one of the first conductive interconnection structure and the second conductive interconnection structure is electrically connected with the bonding pad.
Optionally, the first conductive interconnection structure and the second conductive interconnection structure are metal interconnection layers.
The application also provides a preparation method of the photoelectric integrated silicon optical chip, which comprises the following steps:
manufacturing an integrated optical circuit component in a monocrystalline silicon layer region of a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a base, an insulating layer and the monocrystalline silicon layer which are laminated from bottom to top;
fabricating an integrated circuit component in the substrate region;
manufacturing a silicon through hole penetrating through the silicon-on-insulator substrate in the thickness direction of the silicon-on-insulator substrate;
manufacturing a first conductive interconnection structure and a second conductive interconnection structure on the upper surface and the lower surface of the silicon-on-insulator substrate respectively, wherein the first conductive interconnection structure is electrically connected with the integrated optical circuit component and the through silicon via respectively; the second conductive interconnection structure is electrically connected with the integrated circuit component and the through silicon via respectively.
Optionally, before the fabricating the through silicon via penetrating through the silicon on insulator substrate, the method further includes:
thinning the substrate.
Optionally, thinning the substrate includes:
grinding the substrate;
and polishing the ground substrate.
Optionally, fabricating a through silicon via through the silicon-on-insulator substrate includes:
manufacturing a through hole penetrating through the silicon-on-insulator substrate in the thickness direction of the silicon-on-insulator substrate;
and filling the through holes with conductive medium to form silicon through holes.
The application also provides a semiconductor device which comprises any one of the photoelectric integrated silicon optical chips.
The application provides an optoelectronic integrated silicon optical chip, which comprises: a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a base, an insulating layer and a monocrystalline silicon layer which are laminated from bottom to top; an integrated optical circuit component provided in the single crystal silicon layer region; an integrated circuit component disposed in the base region; a through silicon via; the through silicon vias penetrate through the silicon on insulator substrate in the thickness direction of the silicon on insulator substrate; the first conductive interconnection structure is arranged on the upper surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via; and the second conductive interconnection structure is arranged on the lower surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via.
Therefore, the integrated optical circuit component and the integrated circuit component are integrated on the silicon substrate on the insulator, which belongs to monolithic integration and has the characteristic of high integration level, and the integrated optical circuit component and the integrated circuit component are respectively arranged on the two surfaces of the silicon substrate on the insulator, and are electrically connected through the through silicon via, the first conductive interconnection structure and the second conductive interconnection structure, so that the area of the integrated optical silicon chip can be effectively reduced, and the cost of the integrated optical silicon chip is reduced. The integrated circuit component is arranged in the region of the substrate in the silicon-on-insulator substrate, and the substrate is monocrystalline silicon, so that independent adjustment of the manufacturing process of the integrated circuit component is not needed, the manufacturing process is simplified, the difficulty of the manufacturing process is reduced, and the processing yield is improved.
In addition, the application also provides a preparation method and a semiconductor device with the advantages.
Drawings
For a clearer description of embodiments of the application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a monolithically integrated optoelectronic integrated chip according to the related art;
fig. 2 is a schematic structural diagram of an optoelectronic integrated silicon optical chip according to an embodiment of the present application;
FIG. 3 is a flowchart of a method for fabricating an optoelectronic integrated silicon optical chip according to an embodiment of the present application;
fig. 4 to 8 are flowcharts of a process for fabricating an optoelectronic integrated silicon optical chip according to an embodiment of the present application;
in the figure, 1, a silicon substrate on insulator, 2, a silicon waveguide, 3, a P-type doped waveguide, 4, an N-type doped waveguide, 5, germanium, 6, a P-type doped electron tube, 7, an N-type doped electron tube, 8, polysilicon, 9, a through silicon via, 10, a first conductive interconnection structure, 11, a substrate, 12, an insulating layer, 13, a monocrystalline silicon layer, 14, a second conductive interconnection structure, 15 and a bonding pad are shown.
Detailed Description
In order to better understand the aspects of the present application, the present application will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background art, when the monolithically integrated optoelectronic integrated chip is manufactured, the insulating material on the silicon on the insulator needs to be removed in the processing area of the optoelectronic chip, and then the processing technology of the CMOS chip is performed.
In view of this, the present application provides an optoelectronic integrated silicon optical chip, please refer to fig. 2, comprising:
a silicon-on-insulator substrate 1; the silicon-on-insulator substrate 1 includes a base 11, an insulating layer 12, and a single crystal silicon layer 13 stacked from bottom to top;
an integrated optical circuit member provided in the region of the single crystal silicon layer 13;
an integrated circuit component disposed in the region of the substrate 11;
a through silicon via 9; the through silicon vias 9 penetrate through the silicon on insulator substrate 1 in the thickness direction of the silicon on insulator substrate 1;
the first conductive interconnection structure 10 is arranged on the upper surface of the silicon-on-insulator substrate 1, and the first conductive interconnection structure 10 is respectively and electrically connected with the integrated optical circuit component and the through silicon via 9;
and the second conductive interconnection structure 14 is arranged on the lower surface of the SOI substrate 1, and the second conductive interconnection structure 14 is electrically connected with the integrated circuit component and the through silicon via 9 respectively.
The base 11 in the silicon-on-insulator substrate 1 is a monocrystalline silicon base and the insulating layer 12 may be a silicon dioxide layer.
The integrated optical circuit component may refer to the structure of the integrated optical circuit component in the related art, including a silicon waveguide 2, a P-type doped waveguide 3, an N-type doped waveguide 4, germanium 5, and the like. The integrated circuit device may refer to the structure of the integrated circuit device in the related art, including the polysilicon 8, the P-type doped valve 6, the N-type doped valve 7, and the like.
The through silicon via 9 (Through Silicon Via, TSV) includes a via, and a conductive medium filled in the via. The conductive medium may be a metallic material such as copper, tungsten, or other type of conductive material. The through silicon vias 9 extend from the upper surface of the silicon on insulator substrate 1 to the lower surface of the silicon on insulator substrate 1, and the upper surface and the lower surface of the silicon on insulator substrate 1 are electrically connected, thereby realizing the separate preparation of a silicon photoprocess (based on silicon on insulator) and a conventional CMOS process (based on silicon).
The first conductive interconnection structure 10 is arranged on the upper surface of the silicon-on-insulator substrate 1 and is electrically connected with the integrated circuit component and the through silicon via 9 respectively, and the second conductive interconnection structure 14 is arranged on the lower surface of the silicon-on-insulator substrate 1 and is electrically connected with the integrated circuit component and the through silicon via 9 respectively, so that the integrated circuit component and the integrated circuit component are connected.
As an embodiment, the first conductive interconnection structure 10 and the second conductive interconnection structure 14 are metal interconnection layers.
The integrated optical circuit component and the integrated circuit component are integrated on the silicon substrate 1 on the insulator, which belongs to monolithic integration and has the characteristic of high integration level, and the integrated optical circuit component and the integrated circuit component are respectively arranged on the two surfaces of the silicon substrate 1 on the insulator, and are electrically connected through the through silicon vias 9, the first conductive interconnection structure 10 and the second conductive interconnection structure 14, so that the area of the integrated optical silicon chip can be effectively reduced, and the cost of the integrated optical silicon chip is reduced. The integrated circuit component is arranged in the region of the base 11 in the silicon-on-insulator substrate 1, and the base 11 is monocrystalline silicon, so that independent adjustment of the manufacturing process of the integrated circuit component is not required, the manufacturing process is simplified, the manufacturing process difficulty is reduced, and the processing yield is improved.
On the basis of the above embodiments, in one embodiment of the present application, the optoelectronic integrated silicon optical chip may further include:
and the bonding pad 15 is arranged on the outer surface of the photoelectric integrated silicon optical chip.
The specific arrangement position of the bonding pads 15 may be determined according to the packaging mode of the optoelectronic integrated silicon optical chip, which will be described below.
As an embodiment, when the package mode of the optoelectronic integrated silicon optical chip is gold wire bonding package, the bonding pad 15 is electrically connected to the first conductive interconnection structure 10 or the second conductive interconnection structure 14. That is, the pad 15 is provided on the upper surface side of the silicon-on-insulator substrate 1, or the pad 15 is provided on the lower surface side of the silicon-on-insulator substrate 1.
As another embodiment, when the packaging mode of the optoelectronic integrated silicon optical chip is flip-chip packaging, at least one of the first conductive interconnection structure 10 and the second conductive interconnection structure 14 is electrically connected to the bonding pad 15.
When the packaging mode of the optoelectronic integrated silicon optical chip is the flip-chip packaging, the arrangement modes of the bonding pad 15 include three types, the first type, the first conductive interconnection structure 10 and the bonding pad 15 are electrically connected, that is, the bonding pad 15 is arranged on one side of the upper surface of the silicon on insulator substrate 1, the second type, the second conductive interconnection structure 14 and the bonding pad 15 are electrically connected, that is, the bonding pad 15 is arranged on one side of the lower surface of the silicon on insulator substrate 1, and the third type, the first conductive interconnection structure 10 and the second conductive interconnection structure 14 are electrically connected with the bonding pad 15, that is, the bonding pad 15 is respectively arranged on one side of the upper surface and one side of the lower surface of the silicon on insulator substrate 1, as shown in fig. 2.
The application also provides a preparation method of the photoelectric integrated silicon optical chip, please refer to fig. 3, comprising:
step S101: manufacturing an integrated optical circuit component in a monocrystalline silicon layer region of a silicon-on-insulator substrate; the silicon-on-insulator substrate includes a base, an insulating layer, and the single crystal silicon layer stacked from bottom to top.
The fabrication process of the integrated optical circuit component is based on a silicon optical process, and specific fabrication process can refer to related technology, and will not be described in detail here.
The integrated optical circuit component is completed as shown in fig. 4.
Step S102: and manufacturing an integrated circuit component in the substrate area.
The specific fabrication process of the integrated circuit component may refer to the related art, and will not be described in detail herein.
The integrated circuit component is completed as shown in fig. 5.
In one embodiment of the present application, before fabricating the through silicon via penetrating through the silicon on insulator substrate, the method may further include:
thinning the substrate.
The thickness reduction may be determined according to the depth of the through silicon via, and is not particularly limited in the present application. Typically, the reduced thickness is between 100 and 300 microns.
A schematic diagram of the thinned substrate is shown in fig. 6.
As one embodiment, thinning the substrate comprises:
grinding the substrate;
and polishing the ground substrate.
The grinding process can comprise coarse grinding and fine grinding, the coarse grinding speed is high, the thinning efficiency can be improved, and the fine grinding can remove some damages caused by the coarse grinding.
Step S103: and manufacturing a silicon through hole penetrating through the silicon-on-insulator substrate in the thickness direction of the silicon-on-insulator substrate.
As one embodiment, fabricating a through silicon via through the silicon-on-insulator substrate comprises:
step S1031: and manufacturing a through hole penetrating through the silicon-on-insulator substrate in the thickness direction of the silicon-on-insulator substrate.
The manufacturing mode of the through hole comprises but is not limited to an etching mode and a laser mode.
Step S1032: and filling the through holes with conductive medium to form silicon through holes.
The material of the conductive medium may be copper, tungsten, or other metal material or other type of conductive material.
After the through silicon via is completed, it is shown in fig. 7.
Step S104: manufacturing a first conductive interconnection structure and a second conductive interconnection structure on the upper surface and the lower surface of the silicon-on-insulator substrate respectively, wherein the first conductive interconnection structure is electrically connected with the integrated optical circuit component and the through silicon via respectively; the second conductive interconnection structure is electrically connected with the integrated circuit component and the through silicon via respectively.
The first conductive interconnection structure and the second conductive interconnection structure may be metal interconnection layers, and specific manufacturing processes may refer to related technologies, which are not described herein.
The first conductive interconnection structure and the second conductive interconnection structure are manufactured as shown in fig. 8.
Step S105: and manufacturing a bonding pad on the outer surface of the photoelectric integrated silicon optical chip.
The manufacturing position of the bonding pad in the step is determined according to the packaging mode of the photoelectric integrated silicon optical chip.
When the packaging mode of the photoelectric integrated silicon optical chip is gold wire bonding packaging, the bonding pad is manufactured on one side of the upper surface of the silicon substrate on the insulator, or the bonding pad is manufactured on one side of the lower surface of the silicon substrate on the insulator. That is, the bonding pad is electrically connected with the first conductive interconnection structure or with the second conductive interconnection structure.
When the packaging mode of the photoelectric integrated silicon optical chip is inverted packaging, the bonding pad can be only manufactured on one side of the upper surface of the silicon substrate on the insulator and is electrically connected with the first conductive interconnection structure; or the bonding pad is only manufactured on one side of the lower surface of the silicon-on-insulator substrate and is electrically connected with the second conductive interconnection structure; alternatively, the bonding pads are formed on the upper surface side and the lower surface side of the silicon-on-insulator substrate, respectively, and the bonding pads are formed as shown in fig. 2 after completion of the formation of the bonding pads.
The application also provides a semiconductor device, which comprises the photoelectric integrated silicon optical chip in any embodiment.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
The photoelectric integrated silicon optical chip, the preparation method and the semiconductor device provided by the application are described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.

Claims (10)

1. An optoelectronic integrated silicon photonics chip, comprising:
a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a base, an insulating layer and a monocrystalline silicon layer which are laminated from bottom to top;
an integrated optical circuit component provided in the single crystal silicon layer region;
an integrated circuit component disposed in the base region;
a through silicon via; the through silicon vias penetrate through the silicon on insulator substrate in the thickness direction of the silicon on insulator substrate;
the first conductive interconnection structure is arranged on the upper surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via;
and the second conductive interconnection structure is arranged on the lower surface of the silicon-on-insulator substrate and is respectively and electrically connected with the integrated circuit component and the through silicon via.
2. The optoelectronic integrated silicon photodie of claim 1, further comprising:
and the bonding pad is arranged on the outer surface of the photoelectric integrated silicon optical chip.
3. The integrated optoelectronic silicon photochip of claim 2 wherein the bonding pad is electrically connected to the first conductive interconnect structure or to the second conductive interconnect structure when the integrated optoelectronic silicon photochip is packaged in a gold wire bonding package.
4. The integrated optoelectronic silicon photochip of claim 2 wherein when the packaging mode of the integrated optoelectronic silicon photochip is flip-chip packaging, at least one of the first conductive interconnect structure and the second conductive interconnect structure is electrically connected to the bonding pad.
5. The optoelectronic integrated silicon photodie of any one of claims 1 to 4 wherein the first conductive interconnect structure and the second conductive interconnect structure are metal interconnect layers.
6. The preparation method of the photoelectric integrated silicon optical chip is characterized by comprising the following steps of:
manufacturing an integrated optical circuit component in a monocrystalline silicon layer region of a silicon-on-insulator substrate; the silicon-on-insulator substrate comprises a base, an insulating layer and the monocrystalline silicon layer which are laminated from bottom to top;
fabricating an integrated circuit component in the substrate region;
manufacturing a silicon through hole penetrating through the silicon-on-insulator substrate in the thickness direction of the silicon-on-insulator substrate;
manufacturing a first conductive interconnection structure and a second conductive interconnection structure on the upper surface and the lower surface of the silicon-on-insulator substrate respectively, wherein the first conductive interconnection structure is electrically connected with the integrated optical circuit component and the through silicon via respectively; the second conductive interconnection structure is electrically connected with the integrated circuit component and the through silicon via respectively.
7. The optoelectronic integrated silicon photodie of claim 6, further comprising, prior to fabricating a through silicon via through the silicon-on-insulator substrate:
thinning the substrate.
8. The optoelectronic integrated silicon photodie of claim 7 wherein thinning the substrate comprises:
grinding the substrate;
and polishing the ground substrate.
9. The optoelectronic integrated silicon photonics chip of claim 6, wherein fabricating a through silicon via through the silicon-on-insulator substrate comprises:
manufacturing a through hole penetrating through the silicon-on-insulator substrate in the thickness direction of the silicon-on-insulator substrate;
and filling the through holes with conductive medium to form silicon through holes.
10. A semiconductor device comprising the optoelectronic integrated silicon photodie according to any one of claims 1 to 5.
CN202310823317.4A 2023-07-06 2023-07-06 Photoelectric integrated silicon optical chip, preparation method thereof and semiconductor device Pending CN116864509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310823317.4A CN116864509A (en) 2023-07-06 2023-07-06 Photoelectric integrated silicon optical chip, preparation method thereof and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310823317.4A CN116864509A (en) 2023-07-06 2023-07-06 Photoelectric integrated silicon optical chip, preparation method thereof and semiconductor device

Publications (1)

Publication Number Publication Date
CN116864509A true CN116864509A (en) 2023-10-10

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