CN116798969A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN116798969A CN116798969A CN202310231154.0A CN202310231154A CN116798969A CN 116798969 A CN116798969 A CN 116798969A CN 202310231154 A CN202310231154 A CN 202310231154A CN 116798969 A CN116798969 A CN 116798969A
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- semiconductor device
- electronic component
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 92
- 239000012790 adhesive layer Substances 0.000 claims description 84
- 239000010410 layer Substances 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 24
- 238000002844 melting Methods 0.000 claims description 20
- 230000008018 melting Effects 0.000 claims description 20
- 239000007787 solid Substances 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 14
- 238000003466 welding Methods 0.000 abstract description 2
- 229910001338 liquidmetal Inorganic materials 0.000 description 55
- 229910052751 metal Inorganic materials 0.000 description 30
- 239000002184 metal Substances 0.000 description 30
- 239000003292 glue Substances 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 101710149792 Triosephosphate isomerase, chloroplastic Proteins 0.000 description 1
- 101710195516 Triosephosphate isomerase, glycosomal Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
Abstract
The invention discloses a semiconductor device, comprising: a substrate; an electronic element disposed on the substrate; the cover body is arranged on the substrate and covers the electronic element; the heat conducting element is arranged between the electronic element and the cover body; and the dam body is arranged between the electronic element and the cover body and surrounds the heat conducting element. The heat conducting element is arranged on the electronic element, so that the heat dissipation of the electronic element can be assisted, and the heat dissipation efficiency is improved; the scheme of the invention can prevent the heat conducting element from overflowing outside the dam body during the non-return welding process, and correspondingly prevent the heat conducting element from polluting the substrate or other elements.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
A conventional semiconductor device includes a substrate and an electronic component disposed on the substrate. However, the electronic components inevitably generate heat during operation (or work). Therefore, how to dissipate the heat of the electronic device has become an important issue in the industry.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, which solves the above-mentioned problems.
According to a first aspect of the present invention, there is disclosed a semiconductor device comprising:
a substrate;
an electronic element disposed on the substrate;
the cover body is arranged on the substrate and covers the electronic element; and
the heat conducting element is arranged between the electronic element and the cover body; and
the dam body is arranged between the electronic element and the cover body and surrounds the heat conducting element.
According to a second aspect of the present invention, there is disclosed a method of manufacturing a semiconductor device, comprising:
disposing an electronic component on a substrate;
a cover body is arranged on the substrate and covers the electronic element; and
a heat conducting element is provided, the heat conducting element being surrounded by the dam.
The semiconductor device of the present invention includes: a substrate; an electronic element disposed on the substrate; the cover body is arranged on the substrate and covers the electronic element; the heat conducting element is arranged between the electronic element and the cover body; and the dam body is arranged between the electronic element and the cover body and surrounds the heat conducting element. The heat conducting element is arranged on the electronic element, so that the heat dissipation of the electronic element can be assisted, and the heat dissipation efficiency is improved; the scheme of the invention can prevent the heat conducting element from overflowing outside the dam body during the non-return welding process, and correspondingly prevent the heat conducting element from polluting the substrate or other elements.
Drawings
Fig. 1A shows a schematic diagram of a top view of a semiconductor device according to an embodiment of the present invention;
FIG. 1B is a cross-sectional view of the semiconductor device of FIG. 1A along the direction 1B-1B';
FIG. 1C shows a schematic diagram of a bottom view of the lid (or cover, lid) of FIG. 1B; and
fig. 2A to 2E illustrate a manufacturing process of the semiconductor device of fig. 1B;
FIG. 3A is a top view of a semiconductor device according to one embodiment of the present invention;
FIG. 3B is a cross-sectional view of the semiconductor device of FIG. 3A taken along the direction 3B-3B';
fig. 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
fig. 6A to 6C illustrate a manufacturing process of the semiconductor device of fig. 3B;
fig. 7A to 7C illustrate a manufacturing process of the semiconductor device of fig. 4; and
fig. 8A to 8C illustrate a manufacturing process of the semiconductor device of fig. 5.
Detailed Description
In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The invention relates to a method for manufacturing a semiconductor device. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.
It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, these layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary component, region, layer or section discussed below could be termed a second or secondary component, region, layer or section without departing from the teachings of the present inventive concept.
Further, spatially relative terms such as "below," "under," "above," "over," and the like may be used herein for ease of description to describe one component or feature's relationship thereto. Another component or feature as shown. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terms "about", "approximately" and "approximately" generally mean within a range of ±20% of a specified value, or ±10% of the specified value, or ±5% of the specified value, or ±3% of the specified value, or ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The prescribed value of the present invention is an approximation. When not specifically described, the stated values include the meaning of "about," approximately, "and" about. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be understood that when an "element" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.
Note that: (i) The same features will be denoted by the same reference numerals throughout the figures and not necessarily described in detail in each of the figures in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear in the entire sequence or may appear only in selected figures of the sequence.
In the following embodiments, the same reference numerals denote the same or similar elements or components.
Referring to fig. 1A to 1C, fig. 1A is a top view of a semiconductor device 100 according to an embodiment of the invention, and fig. 1B is a cross-sectional view of the semiconductor device 100 of fig. 1A. Fig. 1C is a bottom view schematic diagram of the cover plate (or lid, cover) 130 of fig. 1B.
The semiconductor device 100 is, for example, a flip chip ball grid array (Flip Chip Ball Grid Array, FCBGA), such as a high performance FCBGA; however, such examples are not meant to be limiting.
As shown in fig. 1A and 1B, the semiconductor device 100 includes a substrate 110, an electronic component 120, a cover (or lid, cover plate) 130, a liquid metal 140, a first adhesive layer 150, a second adhesive layer 160, a first seal 170, a second seal 180, and at least one conductive portion 190.
As shown in fig. 1B, the electronic component 120 is disposed on the substrate 110. The cover 130 is disposed on the substrate 110 and covers the electronic component 120. The liquid metal 140 is formed between the cover 130 and the electronic component 120. Therefore, the heat generated by the electronic component 120 can be dissipated through the liquid metal 140 and the cover 130. The cover 130 may be integrally formed or a single piece, thereby improving mechanical strength of the semiconductor device and improving heat dissipation efficiency.
The substrate 110 has, for example, a single-layer structure or a multi-layer structure. Although not shown, the substrate 110 includes at least one conductive trace, at least one conductive via, and/or at least one conductive pad, wherein the conductive trace is electrically connected to the at least one conductive via. In one embodiment, the substrate 110 is, for example, a printed circuit board (printed circuit board, PCB), an interposer (interposer), another semiconductor device, or a semiconductor package.
The electronic component 120 is electrically connected to the conductive portion (conductive portion) 190 through the substrate 110. The electronic component 120 is, for example, a component that can be applied to (or provided in) a package requiring a high power operation, such as a Flip Chip BGA (FCBGA), a Fan-out (Fan-out) package, a 3D IC package, or the like. The electronic component 120 comprises at least one conductive portion (conductive portion) 121, wherein the conductive portion 121 is, for example, a bump or a solder ball. The electronic component 120 is bonded to at least one conductive pad (not shown) of the substrate 110 through at least one conductive portion 121.
The material of the cover 130 is, for example, metal, such as copper, aluminum, iron, or a combination thereof. The cover 130 may conduct heat and increase the strength of the semiconductor device 100 to reduce warpage.
As shown in fig. 1B and 1C, the cover 130 includes a plate 131, a first surrounding portion 132, at least one column 133, and a second surrounding portion 134. The plate body 131 has a first surface 131s1 and a second surface 131s2 (opposite to the first surface 131s 1). The first surface 131s1 faces the electronic component 120. The first surrounding portion 132, the pillar 133 and the second surrounding portion 134 are disposed on the plate 131 and protrude relative to the first surface 131s1. The first surrounding portion 132 is, for example, a closed loop, and is configured to surround the entire liquid metal 140. Since the columns 133 protrude with respect to the first surface 131s1, a heat conduction area of the cover 130 may be increased. The second surrounding portion 134 surrounds the first surrounding portion 132, the pillar 133, the electronic component 120, and the liquid metal 140. The second surrounding portion 134 is a closed loop, and is configured to surround the entire first surrounding portion 132, the pillar 133, the electronic component 120 and the liquid metal 140.
As shown in fig. 1A to 1C, the cover 130 has a first through hole 131A1 and a second through hole 131A2. In the present embodiment, the first through hole 131a1 and the second through hole 131a2 are located on the plate 131. For example, the first through hole 131a1 and the second through hole 131a2 each extend from the first surface 131s1 to the second surface 131s2. Thus, during the injection of the liquid metal 140, the liquid metal 140 may flow in through the first through holes 131a1, and air (if any) may be discharged through the second through holes 131a2.
As shown in fig. 1A to 1C, the first through hole 131A1 and the second through hole 131A2 are located near the first surrounding portion 132. The first and second through holes 131a1 and 131a2 are located between the entire region 133R. In the present embodiment, the first through hole 131a1 and the second through hole 131a2 are disposed at opposite sides of the entire region 133R or the first surrounding portion 132, so that the distance between the first through hole 131a1 and the second through hole 131a2 is long. Therefore, during the injection of the liquid metal 140, the liquid metal 140 flows in through the first through holes 131a1, and most of the air may be discharged through the second through holes 131a2. In another embodiment, the first through hole 131a1 and the second through hole 131a2 may be disposed at two opposite corners of the whole region 133R or the first surrounding portion 132 (i.e. at two ends of a diagonal line of the whole region 133R or the first surrounding portion 132). Therefore, the distance between the first through hole 131a1 and the second through hole 131a2 is longest, which is more advantageous for exhaust. In another embodiment, the second through hole 131a2 may be omitted, and the first through hole 131a1 may be disposed at a middle position of the second surface 131s2 of the plate body 131 or other positions of the plate body 130. For example, as shown in fig. 1C, the first through hole 131a1 and the second through hole 131a2 are respectively located at both sides of the entire region 133R, so that the formation of the through holes and the injection of the liquid metal are facilitated.
By nature, the melting point of the liquid metal 140 ranges between 60 ℃ and 70 ℃, or lower or higher. The melting point range of the liquid metal 140 can be freely adjusted according to requirements, for example, the composition ratio of the liquid metal is changed, and the liquid metal can comprise gallium and other metals. During the injection of the liquid metal 140, the liquid metal 140 is preheated to a flowable state, injected into the space between the cap body 130 and the electronic component 120 through the first through hole 131a1, and then solidified; without cooling or cooling to achieve solidification. In addition, the thermal conductivity of the liquid metal 140 is between 70W/m-K and 80W/m-K, or higher. The thermal conductivity of the liquid metal 140 is higher than the thermal conductivity of the thermal interface material (Thermal Interface Material, TIM). Typically, the thermal conductivity of TIMs is between 2W/m-K and 5W/m-K.
As shown in fig. 1B, a liquid metal 140 is formed between the cover 130 and the electronic component 120 as a heat transfer medium. Further, a first receiving portion SP1 is formed between adjacent two columns 133, a second receiving portion SP2 is formed between the terminal 133b of each column 133 and the electronic component 120, and a third receiving portion SP3 is formed between the first surrounding portion 132, the first surface 131s1, the outermost column 133, and the electronic component 120. The third receiving portion SP3 has a ring shape, for example, a closed ring shape, as viewed from the top of the third receiving portion SP3. The liquid metal 140 includes at least one first metal portion 141, at least one second metal portion 142, and at least one third metal portion 143. The first metal part 141 fills at least a portion of each of the first receiving parts SP1, the second metal part 142 fills at least a portion of the second receiving part SP2, and the third metal part 143 fills at least a portion of the third receiving part SP3. Therefore, even though the liquid metal 140 has at least one void (or air layer) 140a, heat generated from the electronic component 120 can be dissipated through other heat conductive portions, such as the first, second and third metal portions 141, 142 and 143 connecting the cap plate body 130 and the electronic component 120. In one embodiment, the liquid metal 140 is in a horizontal state (or the semiconductor device is in a horizontal state), and the upper surface of the liquid metal 140 should be at the same level, so that the gap or the clearance 140a will not generally occur when the liquid metal 140 reaches or is higher than the first surface 131s1. When the gap (or air layer) 140a is formed, the upper surface of the liquid metal 140 may not contact the first surface 131s1 (but a gap or clearance exists), but the liquid metal 140 remains in contact with the post 133, so that the heat generated by the electronic component 120 can still be transferred through the liquid metal 140 and the post 133. In one embodiment, the cover 130 has a plurality of columns 133, thereby having a larger contact area with the liquid metal 140 and increasing the heat dissipation area. The columns 133 may be arranged in a regular array on the cover 130 to uniformly dissipate heat. Compared to the conventional thermal interface material used on the electronic component 120 in the prior art, the liquid metal used on the electronic component 120 in the embodiment of the present invention can still dissipate heat with high efficiency even when there is a gap or clearance between the liquid metal and the cover 130 (the conventional thermal interface material has a significantly reduced heat dissipation efficiency when there is a gap or clearance between the liquid metal and the cover 130); wherein liquid metal 140 contacts at least the upper surface (surface near and facing electronic component 120) of post 133 or terminal 133b, or may be higher than the upper surface of post 133 or terminal 133b. In one embodiment, liquid metal 140 reaches first surface 131s1 and contacts first surface 131s1. In another embodiment, liquid metal 140 is above first surface 131s1. Therefore, in the embodiment of the present invention, by using the liquid metal 140, a gap or clearance between the liquid metal 140 and the column 133 can be avoided (as much as possible), so as to avoid affecting the heat dissipation efficiency; also, even if a gap or clearance 140a as shown in fig. 1B occurs, since the liquid metal 140 is kept in contact with the cylinder 133, a high heat dissipation efficiency can be maintained. In the embodiment of the present invention, the liquid metal 140 is (as much as possible) made to reach or be higher than the first surface 131s1 (when the semiconductor device is in the horizontal state), so that the occurrence of the gap or the clearance 140a is (as much as possible) avoided, and the higher heat dissipation efficiency is achieved.
Further, as shown in fig. 1B, a space SP4 is formed between the plate body 131, the first surrounding portion 132, and the second surrounding portion 134. For example, no physical material is formed in the space SP4. For example, the space SP4 has a lean air therein, or the space SP4 is in a vacuum state or the like.
As shown in fig. 1B, the first adhesive layer 150 is disposed between the terminals 132B of the first surrounding portion 132 and the electronic component 120, so as to fix the relative position between the first surrounding portion 132 and the electronic component 120. In one embodiment, the first adhesive layer 150 is annular, such as a closed annular, when viewed from above the first adhesive layer 150, to close the gap (if any) between the first surrounding portion 132 and the electronic component 120. Therefore, the liquid metal 140 can be prevented from leaking (leaking) through the first surrounding portion 132 and the electronic component 120. In addition, the terminal 132b has at least one groove 132b1 for accommodating a portion of the first adhesive layer 150, so that the adhesive force between the first surrounding portion 132 and the electronic component 120 can be increased, and the groove 132b1 can be used for placing the leakage of the liquid metal 140.
As shown in fig. 1B, the second adhesive layer 160 is disposed between the terminal 134B of the second surrounding portion 134 and the substrate 110, so as to fix the relative positions of the cover 130 and the substrate 110. In one embodiment, the second adhesive layer 160 is annular, e.g., closed annular, when viewed from above the second adhesive layer 160, to close the gap (if any) between the second surrounding portion 134 and the substrate 110. Accordingly, the intrusion of external impurities into the inside of the semiconductor device 100 through the second surrounding portion 134 and the substrate 110 is prevented.
As shown in fig. 1B, the first seal 170 closes the first through hole 131a1. Accordingly, the liquid metal 140 is prevented from leaking through the first through hole 131a1, and external impurities are prevented from invading into the inside of the semiconductor device 100 through the first through hole 131a1. In addition, there is a space between the first seal 170 and the third metal part 143 of the liquid metal 140, in which no physical material is formed, and thus the space can endure thermal expansion of the third metal part 143.
As shown in fig. 1B, the second seal 180 closes the second through hole 131a2. Accordingly, the liquid metal 140 is prevented from leaking through the second through hole 131a2, and external impurities are prevented from invading into the inside of the semiconductor device 100 through the second through hole 131a2. In addition, there is a space between the second seal 180 and the third metal part 143 of the liquid metal 140, in which no physical material is formed, and thus the space can withstand thermal expansion of the third metal part 143.
As shown in fig. 1B, the first adhesive layer 150, the second adhesive layer 160, the first seal 170, and the second seal 180 seal the accommodating portion between the cover 130 and the electronic component 120 therein.
As shown in fig. 1B, the conductive portion 190 is formed on the lower surface 110B of the substrate 110. The conductive portions 190 are, for example, bumps, solder balls, or the like. The semiconductor device 100 is bonded and electrically connected to an external electronic device (e.g., PCB, etc.) through the conductive portion 190 of the semiconductor device 100.
Referring to fig. 2A to 2E, fig. 2A to 2E illustrate a manufacturing process of the semiconductor device 100 of fig. 1B.
As shown in fig. 2A, the electronic component 120 is disposed on the substrate 110, wherein the electronic component 120 includes at least one conductive portion 121, and wherein the electronic component 120 is bonded to the substrate 110 through the at least one conductive portion 121. In addition, an underfill 122 is formed between the lower surface 120b of the electronic component 120 and the upper surface 110u of the substrate 110 to encapsulate the conductive portion 121.
As shown in fig. 2B, the first adhesive layer 150 is formed on the upper surface 120u of the electronic component 120, wherein the first adhesive layer 150 is formed on a peripheral region of the upper surface 120 u. The first adhesive layer 150 is annular, for example, closed annular, as viewed from above the first adhesive layer 150.
As shown in fig. 2B, the second adhesive layer 160 is formed on the upper surface 110u of the substrate 110, wherein the second adhesive layer 160 is formed on a peripheral region of the upper surface 110 u. The second adhesive layer 160 is annular, for example, a closed annular, as viewed from above the second adhesive layer 160.
In addition, the embodiment of the present invention is not limited to the order of formation of the first adhesive layer (adhesive layer) 150 and the second adhesive layer (adhesive layer) 160.
As shown in fig. 2C, the cover 130 is disposed on the substrate 110 to cover the electronic component 120. The cover 130 includes a plate 131, a first surrounding portion 132, at least one pillar 133, and a second surrounding portion 134. The cover 130 has a first through hole 131a1 and a second through hole 131a2, wherein the first through hole 131a1 and the second through hole 131a2 extend from the first surface 131s1 of the plate 131 to the second surface 131s2 of the plate 131.
In fig. 2C, the first surrounding portion 132 of the cover 130 is adhered to the electronic component 120 through the first adhesive layer 150, and the second surrounding portion 134 of the cover 130 is adhered to the substrate 110 through the second adhesive layer (adhesive layer) 160, so as to fix the relative positions of the substrate 110 and the cover 130. For fixing the relative position between the substrate 110 and the cover 130. The first adhesive layer (adhesive layer) 150 may close the gap (if any) between the first surrounding portion 132 and the electronic component 120, and the second adhesive layer (adhesive layer) 160 may close the gap (if any) between the second surrounding portion 134 and the substrate 110.
In fig. 2C, a first receiving portion SP1 is formed between two adjacent columns 133, a second receiving portion SP2 is formed between a terminal 133b of each column 133 and the electronic component 120, and a third receiving portion SP3 is formed between the first surrounding portion 132, the first surface 131s1, the outermost column 133, and the electronic component 120. The third housing portion (housing portion) SP3 is annular, for example, a closed annular shape, as viewed from above the third housing portion (housing portion) SP3.
As shown in fig. 2D, at least one conductive portion 190 is formed on the lower portion 110b of the substrate 110.
As shown in fig. 2E, a liquid metal 140 is formed between the cover 130 and the electronic component 120 by using the injector 10. For example, the liquid metal 140 is injected into the first, second and third receiving parts SP1, SP2 and SP3 through the first through holes 131A1, and the gas (e.g., air) A1 is discharged through the second through holes 131a2.
In fig. 2E, the liquid metal 140 includes at least one first metal part 141, a second metal part 142, and a third metal part 143. The first metal part 141 fills at least a portion of each first receiving part SPl, the second metal part 142 fills at least a portion of the second receiving part SP2, and the third metal part 143 fills at least a portion of the third receiving part SP3. Since the cover 130 is connected to the electronic component 120 (e.g., the first metal portion 141, the second metal portion 142, and the third metal portion 143), even if the liquid metal 140 has at least one void (or air layer)) 140a, the heat generated by the electronic component 120 can be dissipated through other heat conductive portions such as the first metal portion 141, the second metal portion 142, and the third metal portion 143 that connect the cover 130 to the electronic component 120.
Then, as shown in fig. 1B, a first seal 170 is formed in the first through hole 131a1 to seal the first through hole 131a1. Accordingly, the liquid metal 140 is prevented from leaking through the first through hole 131a1, and external impurities are prevented from invading into the inside of the semiconductor device 100 through the first through hole 131a1. In addition, there is a space between the first seal 170 and the third metal part 143 of the liquid metal 140, in which no physical material is formed, and thus the space can endure thermal expansion of the third metal part 143.
Then, a second seal 180 is formed in the second through hole 131a2 to seal the second through hole 131a2, as shown in fig. 1B. Accordingly, the liquid metal 140 is prevented from leaking through the second through hole 131a2, and external impurities are prevented from invading into the inside of the semiconductor device 100 through the second through hole 131a2. In addition, there is a space between the second seal 180 and the third metal part 143 of the liquid metal 140, in which no physical material is formed, and thus the space can withstand thermal expansion of the third metal part 143.
In addition, the embodiment of the present invention does not limit the order of formation of the first and second seals 170 and 180.
Referring to fig. 3A and 3B, fig. 3A is a top view of a semiconductor device 300 according to an embodiment of the invention, and fig. 3B is a cross-sectional view of the semiconductor device 300 of fig. 3A along a direction 3B-3B'.
The semiconductor device 300 is, for example, a High Performance (FCBGA) such as a FCBGA (Flip Chip Ball Grid Array ); however, such examples are not meant to be limiting.
As shown in fig. 3A and 3B, the semiconductor device 300 includes a substrate 110, an electronic component 120, a cover 330, a thermally conductive component 340, a dam (dam) 350, a second adhesive layer 160, and at least one conductive portion 190. The electronic device 120 may be, for example, a semiconductor device (active device) such as a semiconductor die or a semiconductor chip.
As shown in fig. 3B, the electronic component 120 is disposed on the substrate 110. The cover 130 is disposed on the substrate 110 and covers the electronic component 120. The heat conducting element 340 is disposed between the cover 330 and the electronic element 120. The dam 350 is disposed between the electronic device 120 and the cover 330, and surrounds the heat conductive device 340. Accordingly, the conductive portion 190 may prevent the thermally conductive element 340 from overflowing the dam 350 during the reflow process and, accordingly, prevent the thermally conductive element 340 from contaminating the substrate 110 or other elements, such as passive (not shown) elements disposed adjacent to the electronic element 120. Specifically, when the semiconductor device is mounted on the PCB, the conductive portion 190 needs to be soldered to mount the semiconductor device on the PCB, and the entire semiconductor device needs to be warmed or heated during this process, so that the heat conductive member 340 may melt, resulting in that the heat conductive member 340 is not in the correct or original position after the mounting, which affects the normal operation. In the embodiment of the present invention, the dam 350 is provided to surround the heat conductive element 340, so that the position of the heat conductive element 340 is not changed even if the heat conductive element 340 melts, and thus, the heat conductive element 340 and the semiconductor device can work normally after being mounted.
In addition, the conductive portion 190 has a first melting point, and the dam 350 has a second melting point that is higher than the first melting point. As such, the dam 350 remains in a solid state (solid state) during the reflow process of the conductive portion 190 to block the overflow of the thermally conductive element 340. In one embodiment, the conductive portion 190 is a solder ball having a first melting point of 230 ℃ to 270 ℃ and the second melting point of the dam 350 ranges from 280 ℃ to 300 ℃. The second melting point of the dam is also higher than the temperature at which reflow is performed so that the dam does not melt when reflow is performed (conductive portion 190) to keep the dam substantially solid.
As shown in fig. 3B, the cover 330 is made of metal, such as copper, aluminum, iron, or a combination thereof. The cover 330 may conduct heat and increase the strength (e.g., mechanical strength) of the semiconductor device 300 to reduce warpage of the semiconductor device 300.
As shown in fig. 3B, the cover 330 includes a plate 131 and a second surrounding portion 134, which are formed by the same process, such as stamping (stamp), pressing (compressing), etc. The plate body 131 has a first surface 131s1 facing the substrate 110. The second surrounding portion 134 is disposed on the plate body 131 and protrudes (or bulges) with respect to (or relative to) the first surface 131s1. The second surrounding portion 134 is in a closed ring shape when viewed from the Z-axis direction, and is configured to surround (or encircle) the electronic component 120 and the heat conducting element 340. The cover 330 may be integrally formed (or molded) or an integral part (the plate 131 and the second surrounding part 134 are integrally molded or an integral structure), thereby improving mechanical strength of the semiconductor device and improving heat dissipation efficiency. In one embodiment, the upper surface of the plate 131 is a flat plane without openings or irregularities. The lower surface (first surface 131s 1) of the plate body 131 is a flat plane (without openings or concave-convex portions). The upper surface of the electronic component 120 is a flat plane (without openings or concave-convex portions), and thus the dam 350 directly contacts the lower surface of the board 131 and the upper surface of the electronic component 120 to more tightly seal the heat conductive member 340.
For one embodiment, the thermally conductive element 340 is, for example, a TIM (Thermal Interface Material ), such as a liquid (liquid) TIM, a solid (solid) TIM, or a paste (paste) TIM. The thermally conductive element 340 comprises a similar or identical material and/or structure as the liquid metal 140 and/or the thermally conductive element 340 has similar or identical characteristics as the liquid metal 140. The heat conducting element 340 has a high heat dissipation performance, so the heat conducting element 340 disposed on the back of the electronic element 120 can help the electronic element 120 dissipate heat, and improve the heat dissipation efficiency. In one embodiment, after installation, the thermally conductive element 340 may have a gap with the cover 330 (or plate 131).
In one embodiment, the dam 350 includes a similar or identical material and/or structure as the first adhesive layer 150, and/or the dam 350 has similar or identical characteristics as the first adhesive layer 150. In one embodiment, the dam 350 is, for example, the first adhesive layer 150. In one embodiment, the material of the dam 350 may be a conventional adhesive material or bonding material (e.g., the same material as the second bonding layer 160), a filler material or underfill (e.g., the same material as the underfill 122), or a (paste) heat-dissipating glue or thermal interface material or heat-conducting material (TIM), etc. The dam 350 can be tightly attached to the lower surface (the first surface 131s 1) of the board 131 and the upper surface of the electronic component 120, and can maintain the structural stability at the reflow temperature and ensure that the heat conducting element 340 does not flow out.
As shown in fig. 3B, the second adhesive layer 160 is disposed between the substrate 110 and the cover 330. For example, the second adhesive layer 160 is disposed between the terminal 134b of the second surrounding portion 134 and the substrate 110, for fixing the relative position of the cover 330 and the substrate 110. In one embodiment, the second adhesive layer 160 is annular, such as a closed annular, as viewed from the top of the second adhesive layer 160, to close the gap (if any) between the second enclosure 134 and the substrate 110. Accordingly, intrusion of external impurities into the inside of the semiconductor device 300 through the second surrounding portion 134 and the substrate 110 is prevented.
In one embodiment, the second adhesive layer 160 and the dam 350 may be formed of the same material. The provision of the second adhesive layer 160 can also increase the heat dissipation performance and mechanical strength of the semiconductor package, and further prevent warpage of the substrate.
As shown in fig. 3B, the conductive portion 190 is formed on the lower surface 110B of the substrate 110. Any of the conductive portions 190 is, for example, a bump, a solder ball, or the like. The semiconductor device 300 is bonded and electrically connected to an external electronic device (e.g., PCB, etc.) through the conductive portion 190 of the semiconductor device 300.
Referring to fig. 4, fig. 4 is a cross-sectional view of a semiconductor device 400 according to another embodiment of the invention.
The semiconductor device 400 is, for example, a FCBGA such as a high-performance FCBGA; however, such examples are not meant to be limiting.
As shown in fig. 4, the semiconductor device 400 includes a substrate 110, an electronic component 420, a cover 330, a thermally conductive element 340, a third adhesive layer 455, a dam 450, a second adhesive layer 160, and at least one conductive portion 190. The electronic device 120 may be, for example, a semiconductor device (active device) such as a semiconductor die or a semiconductor chip.
As shown in fig. 4, the electronic component 420 is disposed on the substrate 110. The cover 330 is disposed on the substrate 110 and covers the electronic component 420. The heat conducting element 340 is disposed between the cover 330 and the electronic element 420. The dam 450 is disposed between the electronic component 420 and the cover 330, and surrounds the heat conductive element 340. Accordingly, the conductive portion 190 may be prevented from overflowing the thermally conductive member 340 out of the dam 350 during reflow and, accordingly, the thermally conductive member 340 may be prevented from contaminating the substrate 110 or other components, such as passive components (not shown) disposed adjacent to the electronic component 420, for example.
Semiconductor device 400 includes similar or identical features as semiconductor device 300 except that electronic component 420 includes a different structure.
Furthermore, as shown in fig. 4, the dam 450 and the electronic component 120 are integrated (or integrated) as one piece (i.e., the dam 450 and the electronic component 120 are integrally formed, for example, as one piece). For example, the dam 450 and the electronic component 120 are fabricated in the same process. The electronic component 420 has an upper surface (top surface) 420u and a recess (or groove, depression) 420r recessed relative to the upper surface 420u to form a dam 450 surrounding the recess (or groove, depression) 420r. The heat conductive element 340 is formed in the recess 420r. At least one circuit is formed within the dam 450. Alternatively, no circuit is formed within the dam 450. The third adhesive layer 455 is disposed between the cover 330 and the dam 450 of the electronic device 420 for sealing the recess 420r. The third adhesive layer 455 is ring-shaped, such as a closed ring-shaped, as viewed from the top of the third adhesive layer 455. The material (or material) of the third adhesive layer 455 may be the same as that of the second adhesive layer 160. In one embodiment, the upper surface of the plate 131 is a flat plane without openings or irregularities. The lower surface of the plate 131 is a flat plane, and has no opening or concave-convex portion. The third adhesive layer 455 may be in close contact with the lower surface of the plate body 131. In one embodiment, the heat conductive member 340 may be solid or paste at normal temperature, so that the cover 330 may be mounted after the heat conductive member 340 is placed in the recess (or groove, depression) 420r.
Referring to fig. 5, fig. 5 is a cross-sectional view of a semiconductor device 500 according to another embodiment of the invention.
The semiconductor device 500 is, for example, a FCBGA such as a high-performance FCBGA; however, such examples are not meant to be limiting.
As shown in fig. 5, the semiconductor device 500 includes a substrate 110, an electronic component 120, a cover 530, a thermally conductive element 340, a third adhesive layer 455, a dam 550, a second adhesive layer 160, and at least one conductive portion 190.
As shown in fig. 5, the electronic component 120 is disposed on the substrate 110. The cover 530 is disposed on the substrate 110 and covers the electronic component 120. The heat conducting element 340 is disposed between the cover 330 and the electronic element 120. The dam 550 is disposed between the electronic device 120 and the cover 530 and surrounds the heat conductive device 340. Accordingly, the conductive portion 190 may prevent the thermally conductive element 340 from overflowing the dam 350 during reflow and, accordingly, prevent the thermally conductive element 340 from contaminating the substrate 110 or other components, such as passive components (not shown) disposed adjacent to the electronic component 120.
The semiconductor device 500 includes similar or identical features as the semiconductor device 400 except that the cover 530 includes a different structure.
Furthermore, as shown in fig. 5, the dam 550 and the cover 330 are integrated (or integrated) as one piece (i.e., the dam 450 and the electronic component 120 are integrally formed, for example, as one piece). For example, the cover 530 includes the plate 131, the second surrounding portion 134, and the dam 550, which are formed by the same process of stamping, pressing, and the like. The dam 550 protrudes relative to the first surface 131s1 to form a recess 530r. The heat conductive element 340 is formed in the groove (or recess) 530r. The dam 550 may be formed as a closed loop structure. The third adhesive layer 455 is disposed between the dam 550 of the cover 530 and the electronic component 120, and is used for fixing the relative positions of the cover 530 and the electronic component 120. The third adhesive layer 455 may seal the groove 420r to prevent the thermally conductive member 340 from overflowing the dam 550. In one embodiment, the upper surface of the plate 131 is a flat plane without openings or irregularities. The lower surface of the plate 131 has a flat surface (without openings or concave-convex portions) except for the dam 550. The upper surface of the electronic component 120 is a flat surface, and has no openings or irregularities. The third adhesive layer 455 may be in close contact with the upper surface of the electronic component 120 and the dam 550. In one embodiment, the heat conductive member 340 may be solid or paste at normal temperature, so that the cover 530 may be mounted after the heat conductive member 340 is placed on the upper surface of the electronic component 120.
Referring to fig. 6A to 6C, fig. 6A to 6C illustrate a manufacturing process of the semiconductor device 300 of fig. 3B.
As shown in fig. 6A, the electronic component 120 is disposed on the substrate 110, wherein the electronic component 120 includes at least one conductive portion 121, and wherein the electronic component 120 is bonded to the substrate 110 through the at least one conductive portion 121. In addition, an underfill (underfill) 122 is formed between the lower surface 120b of the electronic component 120 and the upper surface 110u of the substrate 110 to encapsulate the conductive portion 121.
As shown in fig. 6B, the dam 350 is formed on the upper surface 120u of the electronic component 120, wherein the dam 350 is formed on a peripheral region of the upper surface 120 u. The dam 350 is annular, such as a closed loop, as viewed from the top of the dam 350.
As shown in fig. 6B, the heat conducting element 340 is formed in an area surrounded by the dam 350.
As shown in fig. 6B, a second adhesive layer 160 is formed on the upper surface 110u of the substrate 110, wherein the second adhesive layer 160 is formed on the peripheral region of the upper surface 110 u. The second glue layer 160 is ring-shaped, e.g. closed ring-shaped, seen from the top of the second glue layer 160.
In addition, the forming sequence of the dam 350, the heat conducting element 340 and the second adhesive layer 160 is not limited in the embodiment of the present invention.
As shown in fig. 6C, the cover 330 is disposed on the substrate 110 to cover the electronic component 120, the heat conductive element 340 and the dam 350 by the second adhesive layer 160. The second adhesive layer 160 connects the cover 330 to the substrate 110 to fix the relative positions of the cover 330 and the substrate 110. The cover 330 is disposed on the electronic component 120 through the dam 350. The dam 350 connects the cover 330 and the electronic device 120 to fix the relative position between the cover 330 and the electronic device 120.
Next, at least one conductive portion 190 is formed on the lower layer 110b of the substrate 110 through a reflow (reflow soldering) process. Because the dam 350 retains the thermally conductive member 340, the electrically conductive portion 190 prevents the thermally conductive member 340 from overflowing the dam 350 during reflow and, accordingly, prevents the thermally conductive member 340 from contaminating the substrate 110 or other components, such as passive components (not shown) disposed adjacent to the electronic component 120.
In addition, the conductive portion 190 has a first melting point, and the dam 350 has a second melting point that is higher than the first melting point. As such, the dam 350 remains solid during the reflow process of the conductive portion 190 to block the overflow of the thermally conductive element 340.
Referring to fig. 7A to 7C, fig. 7A to 7C illustrate a manufacturing process of the semiconductor device 400 of fig. 4.
As shown in fig. 7A, the electronic component 420 is disposed on the substrate 110, wherein the electronic component 420 includes at least one conductive portion 121, and wherein the electronic component 420 is bonded to the substrate 110 through the at least one conductive portion 121. In addition, an underfill 122 is formed between the lower surface 120b of the electronic component 420 and the upper surface 110u of the substrate 110 to encapsulate the conductive portion 121. In addition, the electronic component 420 has an upper surface 420u and a recess (or depression) 420r recessed relative to the upper surface 420u to form a dam 450 surrounding the recess 420r.
As shown in fig. 7B, a third adhesive layer 455 is disposed on the dam 450 of the electronic component 420. In another embodiment, the third adhesive layer 455 may be disposed on the cover 330.
As shown in fig. 7B, the heat conducting element 340 is formed in a groove 420r surrounded by the dam 350.
As shown in fig. 7B, a second adhesive layer 160 is formed on the upper surface 110u of the substrate 110, wherein the second adhesive layer 160 is formed on the peripheral region of the upper surface 110 u. The second glue layer 160 is ring-shaped, e.g. closed ring-shaped, seen from the top of the second glue layer 160.
In addition, the embodiment of the present invention does not limit the formation order of the heat conductive member 340, the third adhesive layer 455, and the second adhesive layer 160.
As shown in fig. 7C, the cover 330 is disposed on the substrate 110 to cover the electronic component 420, the heat conductive element 340 and the dam 450 through the second adhesive layer 160. The second adhesive layer 160 connects the cover 330 and the substrate 110 to fix the relative positions of the cover 330 and the substrate 110. The cover 330 is disposed on the electronic component 420 through the third adhesive layer 455. The third adhesive layer 455 connects the cover 330 and the electronic component 420 to fix the relative position between the cover 330 and the electronic component 420. The third adhesive layer 455 may close the groove 420r to prevent the thermally conductive member 340 from overflowing the dam 450.
Next, at least one conductive portion 190 is formed on the lower layer 110b of the substrate 110 through a reflow process. Because the dam 450 blocks the thermally conductive member 340, the electrically conductive portion 190 may prevent the thermally conductive member 340 from overflowing the dam 350 during reflow and, accordingly, prevent the thermally conductive member 340 from contaminating the substrate 110 or other components, such as passive (not shown) components disposed adjacent to the electronic component 120.
In addition, the conductive portion 190 has a first melting point, and the dam 450 has a second melting point that is higher than the first melting point. As such, during the reflow process (process) of the conductive portion 190, the dam 450 remains solid to block the overflow of the thermally conductive element 340.
Referring to fig. 8A to 8C, fig. 8A to 8C illustrate a manufacturing process of the semiconductor device 500 of fig. 5.
As shown in fig. 8A, the electronic component 120 is disposed on the substrate 110, wherein the electronic component 120 includes at least one conductive portion 121, and wherein the electronic component 120 is bonded to the substrate 110 through the at least one conductive portion 121. In addition, an underfill 122 is formed between the lower surface 120b of the electronic component 120 and the upper surface 110u of the substrate 110 to encapsulate the conductive portion 121.
As shown in fig. 8B, a third adhesive layer 455 is formed on the upper surface 120u of the electronic component 120, wherein the third adhesive layer 455 is formed on a peripheral region of the upper surface 120 u. The third adhesive layer 455 is ring-shaped, such as a closed ring-shaped, as viewed from the top of the third adhesive layer 455. In another embodiment, the third adhesive layer 455 may be disposed on the cover 330. For example, the third adhesion layer 455 may be disposed on the dam 550 of the cap 530 in fig. 8C.
As shown in fig. 8B, a second adhesive layer 160 is formed on the upper surface 110u of the substrate 110, wherein the second adhesive layer 160 is formed on the peripheral region of the upper surface 110 u. The second glue layer 160 is ring-shaped, e.g. closed ring-shaped, seen from the top of the second glue layer 160.
As shown in fig. 8C, the heat conductive element 340 is formed in a groove (or recess) 530r surrounded by the dam 530. The cover 530 includes a plate 131, a second surrounding portion 134, and a dam 550. The dam 550 is opposite the first surface 131s1. In one embodiment, the thermally conductive member 340 may be preformed on the cover 530, or the thermally conductive member 340 may be preformed on the electronic component 120.
In addition, the embodiment of the present invention does not limit the formation order of the heat conductive member 340, the third adhesive layer 455, and the second adhesive layer 160.
As shown in fig. 8C, the cover 530 is disposed on the substrate 110 to cover the electronic component 120 and the heat conductive component 340 through the second adhesive layer 160. The second adhesive layer 160 connects the cover 330 and the substrate 110, and is used for fixing the cover 530 and the substrate 110 at the opposite position between the cover plates. The cover 530 is disposed on the electronic component 120 through the third adhesive layer 455. The third adhesive layer 455 connects the cover 530 and the electronic component 120 to fix a relative position between the cover 530 and the electronic component 120. The third adhesive layer 455 may seal the groove (or recess) 530r of the cover 530 to prevent the thermally conductive member 340 from overflowing the dam 550.
Next, at least one conductive portion 190 is formed on the lower portion 110b of the substrate 110 through a reflow process. Since the dam 550 blocks the heat conductive element 340, the heat conductive element 340 is prevented from overflowing the dam 550 during reflow soldering of the heat conductive portion 190, thereby preventing the heat conductive element 340 from contaminating the substrate 110 or other components (parts), such as passive components (not shown) disposed adjacent to the electronic component 120.
In addition, the conductive portion 190 has a first melting point, and the dam 550 has a second melting point that is higher than the first melting point. Thus, during reflow (soldering) of the conductive portion 190, the dam 550 remains solid to block overflow of the thermally conductive element 340. Although the invention has been described in what is presently considered to be the most practical and practical form. Preferred embodiments it is to be understood that the invention is not necessarily limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.
Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (11)
1. A semiconductor device, comprising:
a substrate;
an electronic element disposed on the substrate;
the cover body is arranged on the substrate and covers the electronic element; and
the heat conducting element is arranged between the electronic element and the cover body; and
the dam body is arranged between the electronic element and the cover body and surrounds the heat conducting element.
2. The semiconductor device of claim 1, wherein the dam is a first adhesion layer.
3. The semiconductor device of claim 1, wherein the thermally conductive element is a solid thermally conductive material (TIM).
4. The semiconductor device of claim 1, wherein the electronic component is integrally formed with the dam.
5. The semiconductor device according to claim 1, further comprising:
the second adhesive layer is arranged between the substrate and the cover body;
wherein, the material of the dam body is the same as that of the second bonding layer.
6. The semiconductor device of claim 1, wherein the electronic component has an upper surface and a recess recessed relative to the upper surface to form the dam.
7. The semiconductor device according to claim 6, further comprising:
the third bonding layer is arranged between the dam body and the cover body.
8. The semiconductor device according to claim 1, wherein the cover comprises:
the dam body; and
a plate body having a first surface;
wherein the dam protrudes relative to the first surface.
9. The semiconductor device according to claim 8, further comprising:
the third bonding layer is arranged between the dam body and the electronic element.
10. The semiconductor device according to claim 1, further comprising:
the solder ball is arranged below the substrate and has a first melting point;
wherein the dam has a second melting point that is higher than the first melting point.
11. A method for manufacturing a semiconductor device, comprising:
disposing an electronic component on a substrate;
a cover body is arranged on the substrate and covers the electronic element; and
a heat conducting element is provided, the heat conducting element being surrounded by the dam.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/700,571 | 2022-03-22 | ||
| US63/381,573 | 2022-10-31 | ||
| US18/172,409 | 2023-02-22 | ||
| US18/172,409 US20230197667A1 (en) | 2021-04-08 | 2023-02-22 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116798969A true CN116798969A (en) | 2023-09-22 |
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ID=88045812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310231154.0A Pending CN116798969A (en) | 2022-03-22 | 2023-03-10 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116798969A (en) |
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2023
- 2023-03-10 CN CN202310231154.0A patent/CN116798969A/en active Pending
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