CN116736344A - Method for realizing pulse interference detection and elimination circuit - Google Patents
Method for realizing pulse interference detection and elimination circuit Download PDFInfo
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- CN116736344A CN116736344A CN202310775243.1A CN202310775243A CN116736344A CN 116736344 A CN116736344 A CN 116736344A CN 202310775243 A CN202310775243 A CN 202310775243A CN 116736344 A CN116736344 A CN 116736344A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000001514 detection method Methods 0.000 title claims abstract description 24
- 230000008030 elimination Effects 0.000 title claims abstract description 19
- 238000003379 elimination reaction Methods 0.000 title claims abstract description 19
- 230000003139 buffering effect Effects 0.000 claims description 8
- 238000012935 Averaging Methods 0.000 claims description 3
- 238000013500 data storage Methods 0.000 claims description 3
- 238000013479 data entry Methods 0.000 claims 1
- 230000002776 aggregation Effects 0.000 abstract description 4
- 238000004220 aggregation Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 4
- 230000001960 triggered effect Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/21—Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention aims to provide a method for realizing a pulse interference detection and elimination circuit, which comprises the following steps: s1: the data of the analog-digital converter is input to a data buffer circuit; s2: the data of the analog-digital converter are simultaneously input into a numerical value judging and counting circuit; s3: the numerical value judging and counting circuit is used for detecting and counting the interference of the data of the analog-digital converter; s4: the data buffer circuit outputs the delay data to the data clear selection circuit; and S5, outputting the data by the data clear selection circuit. The invention can realize the detection and elimination of the pulse interference, the aggregation of the pulse interference in the time domain is usually much higher than that of background noise, the amplitude of the sample data subjected to the pulse interference is obviously higher than that of other positions, and the method can be realized without delay and can be triggered to process only when the interference exists.
Description
Technical Field
The invention relates to the technical field of navigation receivers, in particular to a method for realizing a pulse interference detection and elimination circuit.
Background
In a satellite navigation system, pulse signals and navigation signals are in the same frequency band, so that the performance of the navigation system is affected to a certain extent, and even a receiver cannot work normally. The magnitude of this effect is related to the intensity, duty cycle, and period of the pulse signal. The satellite navigation receiver is a typical direct sequence spread spectrum receiver, and the received signal is weak and is easily affected by pulse interference. Therefore, a special set of circuits is required to detect and eliminate the impulse interference.
Disclosure of Invention
Aiming at the problem that a satellite is interfered by pulses, the invention provides a method for realizing a pulse interference detection and elimination circuit.
A method for realizing a pulse interference detection and elimination circuit comprises the following steps:
s1: the data of the analog-digital converter is input to a data buffer circuit;
s2: the data of the analog-digital converter are simultaneously input into a numerical value judging and counting circuit;
s3: the numerical value judging and counting circuit is used for detecting and counting the interference of the data of the analog-digital converter;
s4: the data buffer circuit outputs the delay data to the data clear selection circuit;
and S5, outputting the data by the data clear selection circuit.
Furthermore, in the implementation method of the pulse interference detection and elimination circuit, the S1 further comprises a shift register for buffering the data entering depth in the data storage circuit, and the buffering depth is influenced by the application scene.
Further, a method for implementing a pulse interference detection and cancellation circuit, the step S2 further includes the following substeps:
s21: averaging the energy of the length of the analog-to-digital converter data;
s22: calculating an interference threshold value;
s23: the threshold is equal to the average energy plus 6dB;
s24: interference judgment:
if the energy of two points in the counted length is larger than the threshold value, naturally judging that pulse interference exists in the time period;
if the energy of the two points in the counted length is not more than the threshold value, naturally judging that no pulse interference exists in the time period;
s25: the data buffer circuit generates a data zero clearing mark and a data selecting mark;
S26:
the generated data clear mark is output to a data buffer circuit;
the generated data selection flag is output to a data selection clear circuit.
Further, in the implementation method of the pulse interference detection and elimination circuit, S26 further includes clearing all data and subsequent data of the shift register by the data clear flag.
Further, the circuit of the method for realizing the pulse interference detection and elimination circuit comprises a data buffer circuit, a numerical value judgment and statistics circuit and a data zero clearing selection circuit.
Furthermore, the data buffer circuit is used for storing the analog-digital converter data and is realized through a shift register.
Further, the numerical judgment and statistics circuit functions as the setting of the interference threshold, and the statistics of the interference points and the output of the zero clearing mark in the fixed time.
Further, the data zero clearing selection circuit function comprises output of delay data or zero setting output of delay data.
The invention has the beneficial effects that: the method can realize the pulse interference detection and elimination, the aggregation property of the pulse interference in the time domain is usually far higher than that of background noise, the amplitude of the sample data subjected to the pulse interference is obviously higher than that of other positions, and the method can be realized without delay and can be triggered to process only when the interference exists.
Drawings
Fig. 1 is a schematic diagram of an implementation of impulse interference detection and cancellation.
Fig. 2 is a flow chart of the present invention.
Description of the embodiments
For a clearer understanding of technical features, objects, and effects of the present invention, a specific embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in fig. 1, a method for implementing a pulse interference detection and elimination circuit includes the following steps:
s1: the data of the analog-digital converter is input to a data buffer circuit;
s2: the data of the analog-digital converter are simultaneously input into a numerical value judging and counting circuit;
s3: the numerical value judging and counting circuit is used for detecting and counting the interference of the data of the analog-digital converter;
s4: the data buffer circuit outputs the delay data to the data clear selection circuit;
and S5, outputting the data by the data clear selection circuit.
Furthermore, in the implementation method of the pulse interference detection and elimination circuit, the S1 further comprises a shift register for buffering the data entering depth in the data storage circuit, and the buffering depth is influenced by the application scene.
Further, a method for implementing a pulse interference detection and cancellation circuit, the step S2 further includes the following substeps:
s21: averaging the energy of the length of the analog-to-digital converter data;
s22: calculating an interference threshold value;
s23: the threshold is equal to the average energy plus 6dB;
s24: interference judgment:
if the energy of two points in the counted length is larger than the threshold value, naturally judging that pulse interference exists in the time period;
if the energy of the two points in the counted length is not more than the threshold value, naturally judging that no pulse interference exists in the time period;
s25: the data buffer circuit generates a data zero clearing mark and a data selecting mark;
S26:
the generated data clear mark is output to a data buffer circuit;
the generated data selection flag is output to a data selection clear circuit.
Further, in the implementation method of the pulse interference detection and elimination circuit, S26 further includes clearing all data and subsequent data of the shift register by the data clear flag.
Further, the circuit of the method for realizing the pulse interference detection and elimination circuit comprises a data buffer circuit, a numerical value judgment and statistics circuit and a data zero clearing selection circuit.
Furthermore, the data buffer circuit is used for storing the analog-digital converter data and is realized through a shift register.
Further, the numerical judgment and statistics circuit functions are the setting of an interference threshold, the statistics of interference points in a fixed time and the output of a zero clearing mark.
Further, the data zero clearing selection circuit function comprises output of delay data or zero setting output of delay data.
As shown in fig. 2, the specific operation flow of the embodiment 1 is as follows:
(a) Inputting the ADC data with the width of 16 bits into a data buffer circuit, and enabling the data to enter a shift register with the depth of 256 for buffering, wherein the buffering depth can be changed according to different application scenes;
(b) The data of the ADC enter a numerical judgment and statistics circuit to detect and count interference;
further, the step (b) includes the steps of:
(b1) And carrying out average energy statistics on the ADC data with 256-point length, wherein the length can be set differently according to different application scenes.
(b2) Calculation of the interference threshold, the average energy plus 6dB is taken as the threshold, for example, the average energy is 2500, and the threshold is 4125.
(b3) And judging interference, wherein if the energy of more than or equal to 2 points in the 256 points counted is greater than the threshold 4125, pulse interference is considered to exist in the time period.
(b4) After the interference is detected, a clear mark and a data selection mark are generated, and due to the tailing phenomenon of pulse interference, all data of the mark clearing shift register and subsequent 256-point data are generated.
(c) And the data zero clearing selection circuit receives the data selection mark and selects whether the cached data or zero clearing data is output.
After repeating the steps (a), (b) and (c), pulse interference detection and elimination can be realized, the aggregation property of pulse interference in the time domain is usually far higher than that of background noise, the amplitude of sample data subjected to pulse interference is obviously higher than that of other positions, and the method can be realized without delay and can be triggered to process only when interference exists.
The method can realize the pulse interference detection and elimination, the aggregation property of the pulse interference in the time domain is usually far higher than that of background noise, the amplitude of sample data subjected to the pulse interference is obviously higher than that of other positions, and the method can be realized without delay and can be triggered to process only when the interference exists.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. The method for realizing the pulse interference detection and elimination circuit is characterized by comprising the following steps:
s1: the data of the analog-digital converter is input to a data buffer circuit;
s2: the data of the analog-digital converter are simultaneously input into a numerical value judging and counting circuit;
s3: the numerical value judging and counting circuit is used for detecting and counting the interference of the data of the analog-digital converter;
s4: the data buffer circuit outputs the delay data to the data clear selection circuit;
and S5, outputting the data by the data clear selection circuit.
2. The method for implementing the pulse interference detection and elimination circuit according to claim 1, wherein S1 further comprises a shift register for buffering a data entry depth in the data storage circuit, and the buffering depth is affected by an application scene.
3. The method for implementing a pulse interference detection and cancellation circuit according to claim 1, wherein S2 further comprises the substeps of:
s21: averaging the energy of the length of the analog-to-digital converter data;
s22: calculating an interference threshold value;
s23: the threshold is equal to the average energy plus 6dB;
s24: interference judgment:
if the energy of two points in the counted length is larger than the threshold value, naturally judging that pulse interference exists in the time period;
if the energy of the two points in the counted length is not more than the threshold value, naturally judging that no pulse interference exists in the time period;
s25: the data buffer circuit generates a data zero clearing mark and a data selecting mark;
S26:
the generated data clear mark is output to a data buffer circuit;
the generated data selection flag is output to a data selection clear circuit.
4. A method for implementing a pulse interference detection and cancellation circuit according to claim 3, wherein S26 further comprises clearing all data and subsequent data of the shift register with a data clear flag.
5. The method of claim 1, wherein the circuits of the method comprise a data buffer circuit, a value judgment and statistics circuit, and a data clear selection circuit.
6. The method according to claim 5, wherein the data buffer circuit is implemented by a shift register for storing analog-to-digital converter data.
7. The method of claim 5, wherein the value determining and counting circuit functions as setting an interference threshold, counting interference points in a fixed time, and outputting a clear flag.
8. The method of claim 5, wherein the data clear select circuit function includes an output of delay data or a zero output of delay data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310775243.1A CN116736344A (en) | 2023-06-28 | 2023-06-28 | Method for realizing pulse interference detection and elimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310775243.1A CN116736344A (en) | 2023-06-28 | 2023-06-28 | Method for realizing pulse interference detection and elimination circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116736344A true CN116736344A (en) | 2023-09-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310775243.1A Pending CN116736344A (en) | 2023-06-28 | 2023-06-28 | Method for realizing pulse interference detection and elimination circuit |
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| Country | Link |
|---|---|
| CN (1) | CN116736344A (en) |
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2023
- 2023-06-28 CN CN202310775243.1A patent/CN116736344A/en active Pending
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