CN116701041B - Memory data retention method, retention device and related equipment - Google Patents
Memory data retention method, retention device and related equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a memory data retention method, a retention device and related equipment, wherein the memory data retention method comprises the following steps: before the reset and restart of the processor, the preset memory particles are controlled to enter a self-refreshing state, after the reset and restart of the processor, the preset memory particles are controlled to exit the self-refreshing state, the preset interval of the preset memory particles is set as a reserved interval, zero clearing of the reserved interval is skipped, and the processor avoids the reserved interval in the running process, wherein the preset memory particles are continuously powered in the resetting process, so that data in the preset interval, namely the reserved interval, is reserved in the resetting process of the processor, and data loss in the preset interval, namely the reserved interval, is avoided.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a memory data retention method, a memory data retention device, and related devices.
Background
When the processor goes wrong such as downtime, the fault can be eliminated through resetting. However, if the processor fails or resets for too long, the amount of charge stored in the capacitor of the memory will change with the leakage field of the memory, resulting in data loss in the memory.
Disclosure of Invention
The application discloses a memory data retention method, a retention device and related equipment, which are used for solving the problem of data loss in a memory caused by overlong processor fault or resetting time.
In a first aspect, the present application discloses a memory data retention method, applied to a processor, where the processor is connected to a memory, the memory includes at least one memory granule, and the memory data retention method includes: before the reset and restart of the processor, controlling the preset memory particles to enter a self-refresh state; after the reset and restart of the processor, controlling the preset memory particles to exit from a self-refresh state, setting a preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the operation process; wherein, the preset memory particles are continuously powered in the resetting process.
In some optional examples, before the setting the preset interval of the preset memory granule to the reserved interval, the method further includes: determining whether the preset interval of the preset memory particles stores data to be reserved or not; under the condition that the preset interval of the preset memory particles is determined to store data to be reserved, executing the steps of setting the preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the running process; and executing the step of resetting the preset interval of the preset memory particles under the condition that the preset interval of the preset memory particles is determined to not store the data needing to be reserved.
In some optional examples, before the controlling the preset memory granule to enter the self-refresh state, the method further includes: and storing the data to be reserved into a preset interval of the preset memory granule.
In some optional examples, after the storing the data to be retained in the preset interval of the preset memory granule, the method further includes: and sending a reset reservation signal to a power management chip so that the power management chip controls the preset memory particles to be continuously powered in the resetting process, and setting a reset reservation mark after the power management chip is powered off and restarted, so that the processor can determine that the preset interval of the preset memory particles stores data to be reserved according to the reset reservation mark.
In some alternative examples, the processor includes a plurality of processor cores, and the controlling the preset memory particles to enter the self-refresh state includes: and under the condition that other processor cores are closed, the last processor core or a preset processor core is not closed, sending a self-refreshing instruction to the preset memory particle through the last processor core or the preset processor core, and controlling the preset memory particle to enter a self-refreshing state.
In some optional examples, the skipping clearing the reserved interval and causing the processor to avoid the reserved interval during operation includes: the firmware of the processor skips clearing the reserved interval and reports the reserved interval to the operating system of the processor, so that the operating system of the processor avoids the reserved interval in the running process.
In some alternative examples, further comprising: determining whether the data stored in the reserved interval comprises fault information; and under the condition that the data stored in the reserved interval comprises fault information, carrying out fault analysis according to the fault information.
In a second aspect, the application discloses a memory data retention device, which is applied to a processor, wherein the processor is connected with a memory, the memory comprises at least one memory particle, and the memory data retention device comprises a first processing unit and a second processing unit; the first processing unit is used for storing data to be reserved into a preset interval of preset memory particles before the reset and restart of the processor, and controlling the preset memory particles to enter a self-refresh state; the second processing unit is used for controlling the preset memory particles to return to a self-refreshing state after the reset and restart of the processor, setting a preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the operation process; wherein, the preset memory particles are continuously powered in the resetting process.
In a third aspect, the present application discloses an electronic device, comprising: a memory for storing instructions; the processor is configured to execute the memory data retention method according to any one of the above claims according to the instructions stored in the memory.
In a fourth aspect, the present application discloses a computer readable storage medium having stored thereon instructions for performing the memory data retention method according to any one of the above.
The application discloses a memory data retention method, a retention device and related equipment, wherein before a processor is reset and restarted, preset memory particles are controlled to enter a self-refresh state, in the process of resetting the processor, the preset memory particles of a memory are continuously powered, after the processor is reset and restarted, the preset memory particles are controlled to exit the self-refresh state, a preset interval of the preset memory particles is set as a retention interval, zero clearing of the retention interval is skipped, and the processor avoids the retention interval in the operation process, so that the retention time of data in the preset interval of the preset memory particles in the process of resetting the processor is prolonged, and the data loss in the preset interval of the preset memory particles is avoided.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
Fig. 1 is a schematic diagram of a processor and a memory according to the present disclosure.
Fig. 2 is a flowchart of a memory data retention method according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a memory data retention device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
With the increasing progress of science and technology, rapid localization of faults in computer devices is increasingly required. And when the computer equipment such as a processor is in a breakdown and other faults, the retention of fault information and other data in the memory is the key for locating the faults. However, the reset is usually performed after the processor is down, if the processor is down or the reset time is too long, the charge amount stored in the capacitor in the memory will also change along with the leakage field of the memory, resulting in the data loss in the memory.
Based on the scheme, the application discloses a memory data retention scheme, wherein before a reset and restart of a processor, preset memory particles are controlled to enter a self-refresh state, in the process of resetting the processor, the preset memory particles of a memory are continuously powered, after the reset and restart of the processor, the preset memory particles are controlled to exit the self-refresh state, a preset interval of the preset memory particles is set as a retention interval, zero clearing of the retention interval is skipped, and the processor avoids the retention interval in the running process, so that data loss in the preset interval is avoided.
As an optional implementation of the disclosure, an embodiment of the present application discloses a memory data retention method, where the memory data retention method is applied to a processor, or the memory data retention method is executed by the processor.
As shown in fig. 1, the processor 10 is connected to the memory 11 through an address bus, the memory 11 includes at least one memory granule 110, the processor 10 includes at least one processor core 100 and a memory controller 101, and the at least one processor core 100 reads or writes data of the memory 11 through the memory controller 101. Of course, the above-described configuration is merely an example in the embodiment of the present application, and is not limited thereto.
As shown in fig. 2, a memory data retention method disclosed in an embodiment of the present application includes:
s101: before resetting and restarting the processor, controlling the preset memory particles to enter a self-refreshing state;
before the reset of the processor 10 or after the failure, the memory data retention method may include: the preset memory granule 110 is controlled to enter a self-refresh state to prolong the storage time of the data in the preset interval of the preset memory granule 110 in the resetting process of the processor 10, and avoid the data loss in the preset interval of the preset memory granule 110.
It will be appreciated that during normal operation of the processor 10, the processor 10 will input a refresh command to the memory 11 to maintain the refresh state of the memory 11, so as to avoid the loss of data in the memory 11 due to leakage. However, during the failure or reset of the processor 10, the processor 10 cannot continuously maintain the refresh state of the memory 11, so that if the processor fails or resets for too long, the data in the memory 11 is easily lost. Before the reset of the processor 10 or after the fault, the preset memory particles 110 are controlled to enter the self-refresh state, so that the data in the preset memory particles 110 can be prevented from being lost due to electric leakage.
S102: after the reset and restart of the processor, controlling the preset memory particles to exit the self-refresh state, setting the preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the running process.
After the reset and restart of the processor 10, or after the power-up of the processor 10, the firmware is started first, and the step of initializing the memory 11 is performed by the firmware of the processor 10, where the process of initializing the memory 11 includes address, training of data lines, clearing of the memory 11, and the like. In the process of initializing the memory 11 by the firmware, the firmware controls the preset memory granule 110 to exit the self-refresh state, sets the preset interval of the preset memory granule 110 as a reserved interval, skips clearing the reserved interval, reports the starting address and the size of the reserved interval to the operating system of the processor 10 through ACPI description or DTB file, and the like, and then normally guides the operating system to start, so that the operating system avoids the reserved interval or does not use the reserved interval in the running process of the processor 10, and the data of the reserved interval is prevented from being covered.
The predetermined memory granule 110 may be one or more memory granules 110 of the memory 11, and the predetermined interval may be a part or all of storage intervals of the memory granule 110. After the preset memory granule 110 is controlled to exit the self-refresh state, the processor 10 may enter a state of maintaining memory data refresh to normally access the data of the memory 11.
Of course, in order to ensure that the data in the preset interval of the preset memory particles 110 is not lost, the preset memory particles 110 are continuously powered during the reset process of the processor 10, i.e. during the power-off and power-on processes of the processor 10. The power of the preset memory particles 110 may be continuously supplied to the preset memory particles 110 by a dc power supply, so as to ensure that the preset memory particles 110 are not powered off in the process, or may be supplied to the preset memory particles 110 by an additional power supply such as a battery, so as to ensure that the preset memory particles 110 are not powered off in the process.
Based on the method, before the reset and restart of the processor, the preset memory particles are controlled to enter the self-refresh state, after the reset and restart of the processor, the preset memory particles are controlled to exit the self-refresh state, so that the storage time of data in a preset interval of the preset memory particles in the reset process of the processor can be prolonged, and the data loss in the preset interval of the preset memory particles is avoided. In addition, after the preset interval of the preset memory granule 110 is set as the reserved interval and the clearing of the reserved interval is skipped, the data of the preset interval, that is, the reserved interval, can be reserved in the resetting process of the processor 10, so that the processor 10 can avoid the data in the preset interval, that is, the reserved interval, from being covered in the operation process of the processor 10 after the processor 10 avoids the reserved interval, and the data stored in the preset interval, that is, the reserved interval, can be further reserved.
Although the data may be retained by storing the data in other memories, the data is retained less and occupies more reset time because the storage rate is smaller than that of the memory 11. In the application, the data is directly reserved in the memory 11, so that more data can be reserved, more reset time is not occupied, quick reset can be realized, and the influence on operation is reduced.
In some embodiments of the present application, whether the preset interval of the preset memory granule 110 stores data to be reserved or not, the preset memory granule 110 is controlled to enter a self-refresh state before each reset and restart of the processor 10, the preset memory granule 110 is controlled to exit the self-refresh state after each reset and restart of the processor 10, the preset interval of the preset memory granule 110 is set as a reserved interval, zero clearing of the reserved interval is skipped, and the processor 10 avoids the reserved interval in the running process.
However, the present application is not limited thereto, and in other embodiments, after the reset restart of the processor 10, further includes: determining whether a preset interval of the preset memory particles 110 stores data to be reserved; under the condition that the preset interval of the preset memory particles 110 is determined to store data to be reserved, executing the steps of setting the preset interval of the preset memory particles 110 as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor 10 to avoid the reserved interval in the running process; in the case that it is determined that the preset section of the preset memory granule 110 does not store the data to be reserved, the step of resetting the preset section of the preset memory granule is performed, or that is, the step of setting the preset section of the preset memory granule 110 as the reserved section is not performed any more, the step of resetting the reserved section is skipped, and the processor 10 is caused to avoid the reserved section in the running process.
In some embodiments of the present application, an abort may be triggered in the event of a fault such as a downtime of the processor 10. In response to the abnormal interrupt, the processor 10 stores fault information corresponding to the fault condition such as downtime, etc. into a preset interval of the preset memory granule 110 of the memory 11, and resets. Of course, the present application is not limited thereto, and in other embodiments, the processor 10 may store the data desired to be retained by the user into the preset section of the preset memory granule 110 in response to the abort generated based on the user operation.
That is, before the reset restart of the processor 10, it further includes: the data to be retained is stored in a predetermined interval of the predetermined memory granule 110. The data to be reserved may include fault information, and may also include operation information of a key application in the operation process of the processor 10 that the user desires to reserve. The fault information may include register information, context information, core dump information (coredump), and other fault information such as a function call stack (call trace) when a program goes wrong of the processor core 100, where the core dump information is a snapshot when a process is abnormal, and stores data such as a memory, a register, and a stack when the process is abnormal.
In some embodiments of the present application, the electronic device where the processor 10 and the memory 11 are located further includes a power management chip, where the power management chip is configured to control a power state of the electronic device where the processor 10 and the memory 11 are located, where the power state includes a normal power-off state, a restart state, a sleep state, and the like. When the processor 10 is reset, the power management chip controls the power state to be in a restarting state, so that the electronic devices in which the processor 10 and the memory 11 are located are reset after being powered off and restarted.
In some embodiments of the present application, before the reset and restart of the processor 10, or after the processor 10 stores the data to be retained in the preset interval of the preset memory granule 110, the memory data retention method may further include: and sending a reset reservation signal to the power management chip so that the power management chip controls the preset memory particles 110 to be continuously powered in the resetting process, and enables the power management chip to set a reset reservation mark after power-off restarting or reset restarting. Wherein the reset reservation signal includes a pulse signal, a high level signal, a low level signal, a register signal, or the like.
It can be understood that if the power management chip receives the reset reservation signal before the power-off restart, the power management chip sets the reset reservation flag after the power-off restart of the power management chip, and if the power management chip does not receive the reset reservation signal before the power-off restart, the power management chip does not set the reset reservation flag after the power-off restart of the power management chip.
After the reset restart of the processor 10, it may be determined whether the preset interval of the preset memory granule 110 stores data to be reserved by detecting whether a reset reservation flag is present. That is, after the reset restart of the processor 10, it may be detected whether a reset reservation flag is present, if the reset reservation flag is present, it is determined that the preset section of the preset memory granule 110 stores data to be reserved, and if the reset reservation flag is not present, it is determined that the preset section of the preset memory granule 110 does not store data to be reserved.
Of course, the present application is not limited thereto, and in other embodiments, the power management chip may set the reset reservation flag after power-off restart according to other signals, which is not described herein. The power management chip may set the reset reserved flag through a pull-up level, or may set the reset reserved flag through an output pulse signal, a set register, or RAM, which will not be described herein.
In some embodiments of the present application, the processor 10 includes a plurality of processor cores 100, and controlling the default memory granule 110 to enter the self-refresh state includes: in the case that the other processor core 100 is turned off, the last processor core 100 or the preset processor core 100 is not turned off, a self-refresh instruction is sent to the preset memory granule 110 through the last processor core 100 or the preset processor core 100, so as to control the preset memory granule 110 to enter a self-refresh state.
In some embodiments, it may be preset that one processor core 100 sends a self-refresh instruction to the preset memory granule 110, and then the other processor cores 100 are turned off, and the self-refresh instruction is sent to the preset memory granule 110 through the preset processor core 100, so as to prevent the other processor cores 100 from accessing the memory 11, and influence the preset memory granule 110 to enter the self-refresh state.
Of course, the present application is not limited thereto, and in other embodiments, the self-refresh instruction may be sent to the preset memory granule 110 through the last processor core 100 in the case that the other processor cores 100 are turned off and only the last processor core 100 is left to be turned off.
The processor core 100 may connect to the memory controller 101 by calling a preset SMC interface, and send a self-refresh instruction to the preset memory granule 110 through the memory controller 101. Of course, the present application is not limited thereto, and in other embodiments, the processor core 100 may also send the self-refresh instruction to the preset memory granule 110 by calling other interfaces, which will not be described herein.
In some embodiments of the present application, the memory data retention method may further include: determining whether the data stored in the reserved interval includes fault information; and in the case that the data stored in the reserved section comprises fault information, carrying out fault analysis according to the fault information.
In some embodiments, after the processor 10 stores the fault information in the predetermined interval of the predetermined memory granule 110, a fault information flag is added. After the reset and restart of the processor 10, the firmware will firstly execute the operations of initializing the control memory 11, setting the preset interval of the preset memory granule 110 as a reserved interval, skipping the actions such as clearing the reserved interval, and the like, then after the firmware guides the operating system to start, the operating system will detect whether a fault information mark exists, if the fault information mark exists, the fault information is indicated to be stored in the reserved interval, the fault information is dumped into a file in the hard disk, the fault analysis is performed according to the fault information, and the fault information mark is cleared; if the fault information mark does not exist, the fact that the fault information is not stored in the reserved interval is indicated, the operating system operates normally, and key application operation information is stored in the reserved interval. Of course, in other embodiments, the fault information may not be dumped into a file in the hard disk, but the fault information may be directly analyzed, which is not described herein.
As an optional implementation of the disclosure, an embodiment of the present application discloses a memory data retention device, where the memory data retention device is applied to a processor, or the processor includes the memory data retention device. As shown in fig. 1, the processor 10 is connected to a memory 11, the memory 11 includes at least one memory granule 110, and as shown in fig. 3, the memory data retention device includes a first processing unit 20 and a second processing unit 30.
The first processing unit 20 is configured to control the preset memory granule to enter a self-refresh state before the reset and restart of the processor;
the second processing unit 30 is configured to control the preset memory granule to exit the self-refresh state after the reset restart of the processor, set the preset interval of the preset memory granule as a reserved interval, skip the zero clearing of the reserved interval, and enable the processor to avoid the reserved interval during the operation; wherein, the preset memory particles are continuously powered in the resetting process.
In some embodiments of the present application, the second processing unit 30 is further configured to: after resetting and restarting the processor, determining whether a preset interval of preset memory particles stores data to be reserved or not; under the condition that the preset interval of the preset memory particles is determined to store data to be reserved, executing the steps of setting the preset interval of the preset memory particles as a reserved interval, skipping zero clearing of the reserved interval and enabling the processor to avoid the reserved interval in the running process; and executing the step of resetting the preset interval of the preset memory particles under the condition that the preset interval of the preset memory particles is determined to not store the data needing to be reserved.
In some embodiments of the present application, the first processing unit 20 is further configured to: before the preset memory grain is controlled to enter the self-refreshing state, the data needing to be reserved are stored in a preset interval of the preset memory grain.
In some embodiments of the present application, the first processing unit 20 is further configured to: after the data to be reserved is stored in the preset interval of the preset memory particles, a reset reservation signal is sent to the power management chip, so that the power management chip can control the preset memory particles to be continuously powered in the resetting process, and the power management chip can set a reset reservation mark after power-off restarting, and the processor can conveniently determine that the preset interval of the preset memory particles stores the data to be reserved according to the reset reservation mark.
In some embodiments of the present application, the processor includes a plurality of processor cores, and the first processing unit 20 controlling the predetermined memory granule to enter the self-refresh state includes: and under the conditions that other processor cores are closed and the last processor core or the preset processor core is not closed, sending a self-refreshing instruction to the preset memory particles through the last processor core or the preset processor core, and controlling the preset memory particles to enter a self-refreshing state.
In some embodiments of the present application, the second processing unit 30 skips clearing the reserved interval, and makes the processor avoid the reserved interval during the operation process include: the firmware of the processor skips clearing the reserved interval and reports the reserved interval to the operating system of the processor, so that the operating system of the processor avoids the reserved interval in the running process.
In some embodiments of the present application, the second processing unit 30 is further configured to: determining whether the data stored in the reserved interval includes fault information; and in the case that the data stored in the reserved section comprises fault information, carrying out fault analysis according to the fault information.
As another alternative implementation of the disclosure, an embodiment of the present disclosure discloses a computer-readable storage medium having stored thereon instructions for performing the memory data retention method disclosed in any of the embodiments above.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
As another optional implementation of the disclosure, an embodiment of the present disclosure discloses an electronic device, where the electronic device includes a memory and a processor, where the memory is configured to store instructions, and the memory may be a memory, and the processor is configured to execute, according to the instructions stored in the memory, a memory data retention method disclosed in any one of the foregoing embodiments. It is to be understood that the electronic device may include other components as desired.
The electronic device may be loaded and thus include one or more applications. These applications are sets of instructions (e.g., computer program code) that, when read by a processor, control the operation of the electronic device. To this end, the memory may include instructions/data executable by the processor whereby the electronic device may perform a method in accordance with at least one embodiment of the present application as disclosed.
As an alternative implementation of the present disclosure, an embodiment of the present disclosure discloses a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the memory data retention method as disclosed in any of the embodiments above.
The computer program product may include program code for carrying out operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as python, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.
Claims (9)
1. A memory data retention method applied to a processor, the processor being connected to a memory, the memory including at least one memory granule, the memory data retention method comprising:
before resetting and restarting the processor, a reset reservation signal is sent to a power management chip, so that the power management chip controls preset memory particles to be continuously powered in the resetting process, and the power management chip sets a reset reservation mark after power-off and restarting, so that the processor determines whether the preset interval of the preset memory particles stores data to be reserved or not according to the reset reservation mark, and controls the preset memory particles to enter a self-refreshing state;
after the reset and restart of the processor, controlling the preset memory particles to exit from a self-refresh state, setting a preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the operation process; wherein, the preset memory particles are continuously powered in the resetting process.
2. The memory data retention method of claim 1, further comprising, after the processor reset reboot:
determining whether the preset interval of the preset memory particles stores data to be reserved or not;
under the condition that the preset interval of the preset memory particles is determined to store data to be reserved, executing the steps of setting the preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the running process;
and executing the step of resetting the preset interval of the preset memory particles under the condition that the preset interval of the preset memory particles is determined to not store the data needing to be reserved.
3. The memory data retention method according to claim 1 or 2, wherein before the sending the reset retention signal to the power management chip, the method further comprises:
and storing the data to be reserved into a preset interval of the preset memory granule.
4. The memory data retention method of claim 1, wherein the processor comprises a plurality of processor cores, and wherein controlling the predetermined memory granule to enter the self-refresh state comprises:
and under the condition that other processor cores are closed, the last processor core or a preset processor core is not closed, sending a self-refreshing instruction to the preset memory particle through the last processor core or the preset processor core, and controlling the preset memory particle to enter a self-refreshing state.
5. The memory data retention method according to claim 1 or 2, wherein the skipping the clearing of the retention interval and causing the processor to avoid the retention interval during operation comprises:
the firmware of the processor skips clearing the reserved interval and reports the reserved interval to the operating system of the processor, so that the operating system of the processor avoids the reserved interval in the running process.
6. The memory data retention method according to claim 1 or 2, further comprising:
determining whether the data stored in the reserved interval comprises fault information;
and under the condition that the data stored in the reserved interval comprises fault information, carrying out fault analysis according to the fault information.
7. A memory data retention device applied to a processor, wherein the processor is connected with a memory, the memory comprises at least one memory particle, and the memory data retention device is characterized by comprising a first processing unit and a second processing unit;
the first processing unit is used for sending a reset reservation signal to the power management chip before resetting and restarting the processor, so that the power management chip controls preset memory particles to be continuously powered in the resetting process, and sets a reset reservation mark after the power management chip is powered off and restarted, so that the processor determines whether the preset interval of the preset memory particles stores data to be reserved or not according to the reset reservation mark, and controls the preset memory particles to enter a self-refreshing state;
the second processing unit is used for controlling the preset memory particles to exit from the self-refreshing state after the reset and restart of the processor, setting a preset interval of the preset memory particles as a reserved interval, skipping the zero clearing of the reserved interval, and enabling the processor to avoid the reserved interval in the operation process;
wherein, the preset memory particles are continuously powered in the resetting process.
8. An electronic device, comprising:
a memory for storing instructions;
a processor, configured to execute the memory data retention method according to any one of claims 1 to 6 according to the instructions stored in the memory.
9. A computer readable storage medium having stored thereon instructions for performing the memory data retention method according to any one of claims 1 to 6.
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