CN116647119A - Common-ground type switched capacitor inverter with continuous input current and control method thereof - Google Patents

Common-ground type switched capacitor inverter with continuous input current and control method thereof Download PDF

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Publication number
CN116647119A
CN116647119A CN202310315077.7A CN202310315077A CN116647119A CN 116647119 A CN116647119 A CN 116647119A CN 202310315077 A CN202310315077 A CN 202310315077A CN 116647119 A CN116647119 A CN 116647119A
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China
Prior art keywords
switch tube
power switch
capacitor
unit
power
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CN202310315077.7A
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Chinese (zh)
Inventor
姚佳
张建栋
嵇保健
张泽宇
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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Priority to CN202310315077.7A priority Critical patent/CN116647119A/en
Publication of CN116647119A publication Critical patent/CN116647119A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses a common-ground type switched capacitor inverter with continuous input current and a control method thereof, wherein the inverter comprises a basic boosting unit M1, an expandable switched capacitor unit M2 and an output unit M3. The basic boosting unit M1 can realize continuous input current, reduce input current ripple and modulate capacitor voltage; the expandable switch capacitor unit M2 can be composed of multiple types of switch capacitor units, and the multiple expandable switch capacitors M2 are used for improving the voltage gain and the level number of the converter through cascading. The basic boosting unit M1 and the expandable switch capacitance unit M2 can realize multi-level output through series connection. The invention has the advantages of common input and output ground, high gain, wide voltage input support, expansibility, continuous input current, smaller ripple wave and lower total harmonic distortion rate of output.

Description

Common-ground type switched capacitor inverter with continuous input current and control method thereof
Technical Field
The invention belongs to the field of multi-level inverters and new energy distributed grid-connected power generation, and particularly relates to a common-ground type switched capacitor inverter with continuous input current and a switching control method thereof.
Background
In the application of renewable energy grid-connected systems, electric automobiles, flexible alternating current transmission systems or other alternating current distributed power generation systems, compared with a two-level inverter, the multi-level inverter (MLI) has the advantages of low Total Harmonic Distortion (THD), modularization, high fault tolerance and the like.
In the application of the photovoltaic power generation system, the common-ground type switch capacitor multi-level inverter can effectively eliminate leakage current, obtain high gain and reduce THD.
The voltage modulation range of the common switched capacitor inverter is very small, the input current is discontinuous, the photovoltaic panel cannot be directly connected, and the control of maximum power tracking and the like is finished by the front-stage direct current converter, so that extra cost is increased. How to achieve continuous control of input current ripple and provide voltage gain modulation capability for switched capacitor inverter input currents is critical to current research.
Disclosure of Invention
The invention aims to provide a novel common-ground type switch capacitor multi-level inverter topology aiming at the defects of the existing switch capacitor type multi-level inverter topology. The topology basic boosting unit (M1) realizes continuous input current, reduces ripple waves of the input current and supports wide voltage input; the expandable switch capacitor unit (M2) can be formed by cascading a plurality of expandable switch capacitors, and the basic boosting unit (M1) and the expandable switch capacitor unit (M2) can realize multi-level output through serial connection.
A common-ground switched capacitor inverter with continuous input current, characterized in that: the device comprises a basic boosting unit (M1), a scalable switched capacitor unit (M2) and an output unit (M3);
the basic boosting unit (M1) is composed of an input inductor (L), a first power switch tube (S1), a second power switch tube (S2), a fifth power switch tube (S5) and a first capacitor (C1). Wherein the positive end of the input inductor (L) is connected with the positive output end of the direct current power supply (Vdc); the drain electrode of the fifth power switch tube (S5) is connected with the negative end of the input inductance (L) and the source electrode of the first power switch tube (S1), and the fifth powerThe source electrode of the rate switching tube (S5) is connected with the negative end of the direct current power supply (Vdc), the drain electrode of the second power switching tube (S2) and the ground; the positive end of the first capacitor (C1) is connected with the drain electrode of the first power switch tube (S1) and the port 1 of the expandable switch capacitor unit (M2), and the negative end of the first capacitor (C1) is connected with the source electrode of the second power switch tube (S2) and the port 2 of the expandable switch capacitor unit (M2); the basic boosting unit (M1) can output +V c ，0，-V c Three levels, where V c For modulating the voltage of the capacitor, V c ＝V dc /(1-D), where d=t on Ts, ts is the switching period, t on The inductor charge time is for each switching cycle of the inductor.
The expandable switch capacitor unit (M2) consists of a plurality of switch capacitor units (K1-Kn), each switch capacitor unit (Kn) comprises four ports, namely a port 1, a port 2, a port 3 and a port 4, and each switch capacitor unit (Kn) can output +V c ，0，-V c Three levels; and when the number of the units is n, the number of the expandable switch capacitor units (M2) is 2n+3, and n is a natural number greater than or equal to 1.
The output unit (M3) comprises a third power switch tube (S3) and a fourth power switch tube (S4). The drain electrode of the third power switch tube (S3) is connected with the port 3 of the expandable switch capacitor unit (M2), and the source electrode of the fourth power switch tube (S4) is connected with the port 4 of the expandable switch capacitor unit (M2); the source electrode of the third power switch tube (S3) is connected with the drain electrode of the fourth power switch tube (S4) and the ground to form an output port V o 。
Further the switched capacitor scalable unit (M2) may be, but is not limited to, a series-parallel type, a cascade type, a ladder type switched capacitor topology.
The unidirectional voltage-resistant power switch tube adopts a fully-controlled power electronic device, and can be, but is not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT); the bidirectional voltage-resistant power switch tube can be formed by connecting two Metal Oxide Semiconductor Field Effect Transistors (MOSFET) in series;
further said input powerThe switching control method of the common-ground type switched capacitor inverter with continuous flow is characterized in that: the capacitors in the basic boosting unit (M1) and the expandable switch capacitor unit (M2) can output multi-level alternating voltage in a series-parallel connection mode, and the common-ground switch capacitor inverter can be controlled in a sine pulse width modulation mode. When the peak value of the alternating current output voltage is (n+1) V c In this case, n switched capacitor units (K1 to Kn) are required. The specific control time sequence is as follows:
when the output voltage is at zero level (V o =0), the circuit has two modes of operation, the first mode of operation being: the first power switch tube (S1), the second power switch tube (S2) and the fourth power switch tube (S4) are turned on, the third power switch tube (S3) and the fifth power switch tube (S5) are turned off, all the expandable switch capacitance units (M2) output zero level, at the moment, the basic boosting unit (M1) charges the first capacitor (C1) and the capacitors in the switch capacitance expandable units (M2) to V c The duration of this state is t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the third power switch tube (S3) are turned off, the expandable switch capacitance unit (M2) outputs zero level, and at the moment, the basic boosting unit (M1) charges the first capacitor (C1) and the capacitor in the switch capacitance expandable unit (M2) to V c The duration of this state is t on_0 ；
When the output voltage is at positive level (V o ＝+V c ) When the circuit has two working modes, the first working mode is as follows: the first power switch tube (S1), the second power switch tube (S2) and the third power switch tube (S3) are turned on, the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned off, the expandable switch capacitance unit (M2) outputs a level, and at the moment, the basic boosting unit (M1) charges the first capacitor (C1) and the capacitor in the switch capacitance expandable unit (M2) to V c At the same time give the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, and the first power switch tube (S1) and the fourth power switch tube (S)4) The switch-off, expandable switch capacitor unit (M2) outputs a level, at this time, the DC power supply (V dc ) Charging the input inductance (L), the first capacitor (C1) and the capacitor in the switched capacitor scalable unit (M2) being connected in parallel to the load Z o Power is supplied for a period of time t on_P1 ；
When the output voltage is positive j level (V o ＝+jV c ) When (1 < j < n+1, and j is an integer), the circuit has two working modes, and when in a first working mode: the first power switch tube (S1), the second power switch tube (S2) and the third power switch tube (S3) are turned on, the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned off, the output j level of the switch capacitor unit (M2) can be expanded, at the moment, the capacitors in the switch capacitor unit (K1) to the switch capacitor unit (K (j-1)) are connected with the first capacitor (C1) in parallel, and the basic boost unit (M1) is charged to V c The capacitor in the switch capacitor unit (Kj) to the switch capacitor unit (Kn) and the basic boosting unit (M1) are connected in series to the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs j level, and at the moment, the direct current power supply (V dc ) Charging the input inductor (L), connecting the capacitor in the switch capacitor unit (K1) to the switch capacitor unit (K (j-1)) in parallel with the first capacitor (C1), and connecting the capacitor in the switch capacitor unit (Kj) to the switch capacitor unit (Kn) in series to the load Z o Power is supplied for a period of time t on_Pj ；
When the output voltage is at positive (n+1) level (V o ＝+(n+1)V c ) When the circuit has an operating mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs n level, at the moment, the direct current power supply (V dc ) Charging an input inductance (L), and connecting the capacitances in the switched capacitor units (K1) to (Kn) in series with the first capacitance (C1) to a load Z o Power is supplied for a period of time t on_P(n+1) ；
When the output voltage is negative one level (V o ＝-V c ) When the circuit has two working modes, the first working mode is as follows: the first power switch tube (S1), the second power switch tube (S2) and the fourth power switch tube (S4) are turned on, the third power switch tube (S3) and the fifth power switch tube (S5) are turned off, the expandable switch capacitance unit (M2) outputs a negative level, at the moment, the capacitance in the switch capacitance unit (K1) to the switch capacitance unit (K (n-1)) is connected in parallel with the first capacitance (C1), and the basic boost unit (M1) is charged to V c The switched capacitor unit (Kn) gives the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs a negative level, and at the moment, the direct current power supply (V dc ) Charging the input inductance (L), the capacitance in the switched capacitor unit (K1) to the switched capacitor unit (K (n-1)) and the first capacitance (C1) are not operated, and the switched capacitor unit (Kn) gives the load Z o Power is supplied for a period of time t on_N1 ；
When the output voltage is negative j level (V o ＝-jV c ) When (1 < j < n+1, and j is an integer), the circuit has two working modes, and when in a first working mode: the first power switch tube (S1), the second power switch tube (S2) and the fourth power switch tube (S4) are turned on, the third power switch tube (S3) and the fifth power switch tube (S5) are turned off, the expandable switch capacitance unit (M2) outputs negative j level, at the moment, the capacitance in the switch capacitance unit (K1) to the switch capacitance unit (K (n-j)) is connected in parallel with the first capacitance (C1), and the basic boost unit (M1) is charged to V c The capacitors in the switch capacitor units (K (n-j+1)) -switch capacitor units (Kn) are serially connected to the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs negative j level, and at the moment, the direct current power supply (V dc ) To input electricityThe inductor (L) is charged, the switch capacitor units (K1) to (K (n-j)) and the first capacitor (C1) do not work, and the capacitors in the switch capacitor units (K (n-j+1)) to (Kn) are connected in series to the load Z o Power is supplied for a period of time t on_Nj ；
When the output voltage is negative (n+1) level (V o ＝-(n+1)V c ) When the circuit has an operating mode: the first power switch tube (S1), the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned on, the second power switch tube (S2) and the third power switch tube (S3) are turned off, the expandable switch capacitor unit (M2) outputs negative n level, and at the moment, the direct current power supply (V dc ) Charging an input inductance (L), and connecting the capacitances in the switched capacitor units (K1) to (Kn) in series with the first capacitance (C1) to a load Z o Power is supplied for a period of time t on_N(n+1) ；
Further, the switching control method of the common-ground type switched capacitor inverter with continuous input current, wherein t on ＝DTs、t off = (1-D) Ts, which contains the turn-on time t of the respective level input inductance (L) on_0 、t on_P1 、t on_Pj 、t on_P(n+1) 、t on_N1 、t on_Nj And t on_N(n+1) The relationship between these is shown in Table I below.
Table I relationship of the on time of the various level input inductors (L)
Where Vm is the modulated carrier, vm=msin (100 pi t), M is the modulation index, ac is the triangular carrier amplitude, ac=1/(n+1), to is the output period.
The beneficial effects are that: according to the invention, an input inductor (L) is added to the direct current input side of the common-ground type switch capacitor inverter, a basic boosting unit (M1) is formed by multiplexing a first power switching tube (S1), a second power switching tube (S2) and a fifth power switching tube (S5), so that the instantaneous current of the direct current side of the switch capacitor inverter is reduced, the current is continuous, the wide voltage input is supported, and the cost is reduced; more level outputs can be realized through the first capacitor (C1) and the expandable switch capacitor unit (M2), and the total harmonic distortion rate of the outputs is reduced.
Drawings
FIG. 1 is a circuit diagram of a novel common-ground switched capacitor multi-level inverter provided by the invention;
FIGS. 2 (a) to 2 (c) are circuit diagrams of a novel common-ground type switched-capacitor multilevel inverter formed by three different switched-capacitor scalable units (M2) according to the present invention;
FIG. 3 is an output waveform in a sinusoidal pulse width modulation mode of the circuit topology of the present invention;
fig. 4 is a schematic circuit diagram of a common-ground type switched capacitor five-level inverter according to an embodiment of the present invention;
FIGS. 5 (a) to 5 (h) are eight special equivalent operating mode diagrams according to the embodiment of the present invention, wherein FIGS. 5 (a) and 5 (b) show the output voltage at zero level (V o =0) schematic diagrams of two modalities; FIGS. 5 (c) and 5 (d) show the output voltage at positive one level (V o ＝+V c ) Schematic diagrams of two modalities; FIG. 5 (e) shows the output voltage at positive two levels (V o ＝+2V c ) Schematic of (2); FIGS. 5 (f) and 5 (g) show the output voltage at negative one level (V o ＝-V c ) Schematic diagrams of two modalities; FIG. 5 (h) shows the output voltage at negative two level (V o ＝-2V c ) Schematic of (2);
fig. 6 is a waveform diagram of an input current of an inverter in an embodiment of the present invention;
fig. 7 is a waveform diagram of an output voltage of an inverter in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
FIG. 4 depicts a main circuit configuration of an embodiment of the present inventionIs a common-ground type switch capacitor five-level inverter circuit. The main circuit comprises a basic boosting unit (M1), a scalable switched capacitor unit (M2) and an output unit (M3). The basic boosting unit (M1) is composed of an input inductor (L), a first power switch tube (S1), a second power switch tube (S2), a fifth power switch tube (S5) and a first capacitor (C1); the switch capacitor expandable unit (M2) is composed of a module, and the module is composed of a first expansion power switch tube (Sa 1), a second expansion power switch tube (Sa 2), a third expansion power switch tube (Sa 3), a fourth expansion power switch tube (Sa 4), a fifth expansion power switch tube (Sa 5) and a second capacitor (C2); the output unit (M3) is composed of a third power switch tube (S3), a fourth power switch tube (S4) and a load Z o The composition is formed.
As shown in fig. 3, the present example employs a sinusoidal pulse width modulation scheme, wherein the solid-line loop with arrows represents a capacitive or inductive charging loop and the dashed-line loop with arrows represents a load current loop. During each voltage level output period, two switching modes are switched, so that input current continuity is realized. The detailed working principle is analyzed as follows:
when the output voltage is at zero level (V o =0), first mode of operation: as shown in fig. 5 (a), the power switching transistors (S1, S2, S4, sa1, sa2, sa3, sa 4) are in on state, and the dc power supply (V dc ) The input inductor (L) is connected in series and then connected in parallel with the capacitors (C1, C2), and the charging voltage of the capacitors (C1, C2) is V c The power switching tubes (S2, S4, sa2, sa 4) form a closed loop and are used as a load Z o Providing a follow current path to realize zero level output; and in the second working mode: as shown in fig. 5 (b), the power switching transistors (S2, S4, S5, sa2, sa 4) are in on state, and the dc power supply (V dc ) Charging the input inductance (L), the power switching transistors (S2, S4, sa2, sa 4) form a closed loop for the load Z o Providing a follow current path to realize zero level output;
when the output voltage is at positive level (V o ＝+V c ) In a first working mode: as shown in fig. 5 (c), the power switching transistors (S1, S2, S3, sa1, sa2, sa3, sa 4) are in on state, and the dc power supply (V dc ) Connected in series with an input inductance (L) and then connected in parallel with the capacitances (C1, C2), and is electrically connected with the input inductance (L)The charging voltage of the capacitor (C1, C2) is V c DC power supply (V) dc ) For the load Z o Power is supplied to realize positive one-level output; and in the second working mode: as shown in fig. 5 (d), the power switching transistors (S2, S3, S5, sa1, sa2, sa3, sa 4) are in on state, and the dc power supply (V dc ) Charging an input inductance (L), the capacitors (C1, C2) being connected in parallel to a load Z o Power is supplied to realize positive one-level output;
when the output voltage is positive two level (V o ＝+V c ) In a first working mode: as shown in fig. 5 (e), the power switching transistors (S2, S3, S5, sa1, sa4, sa 5) are in on state, and the dc power supply (V dc ) Charging an input inductance (L), the capacitors (C1, C2) being connected in series to a load Z o Power is supplied, and positive two-level output is realized;
when the output voltage is negative one level (V o ＝-V c ) In a first working mode: as shown in fig. 5 (f), the power switching transistors (S1, S2, S4, sa2, sa3, sa 5) are in on state, and the dc power supply (V dc ) The capacitor (C1) is connected in parallel with the input inductor (L) after being connected in series, and the charging voltage of the capacitor (C1) is V c Capacitor (C2) gives load Z o Power is supplied to realize negative one-level output; and in the second working mode: as shown in fig. 5 (g), the power switching transistors (S1, S2, S3Sa2, sa3, sa 5) are in on state, and the dc power supply (V dc ) Charging an input inductance (L), a capacitor (C2) charging a load Z o Power is supplied to realize negative one-level output;
when the output voltage is negative two level (V o ＝-2V c ) In a first working mode: as shown in fig. 5 (h), the power switching transistors (S1, S4, S5, sa2, sa3, sa 5) are in on state, and the dc power supply (V dc ) Charging an input inductance (L), the capacitors (C1, C2) being connected in series to a load Z o Power is supplied, and negative two-level output is realized;
the following results were obtained using PSIM simulation. FIG. 6 is a waveform of an input current, with current fluctuating between 3A and 4.5A, without significant transient current, verifying that the topology reduces transient current, making the input current continuous. Fig. 7 shows waveforms of output voltages, wherein the square root value is 220V, the output frequency is 50Hz, and the structure has certain boosting capability according to theoretical analysis, so that the feasibility of the structure is verified.
The above description is only of the preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention is described in terms of the preferred embodiments, it is not limited thereto. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the technical solution scope of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (5)

1. A common-ground switched capacitor inverter with continuous input current, characterized in that: the device comprises a basic boosting unit (M1), a scalable switched capacitor unit (M2) and an output unit (M3);
the basic boosting unit (M1) is composed of an input inductor (L), a first power switch tube (S1), a second power switch tube (S2), a fifth power switch tube (S5) and a first capacitor (C1). Wherein the positive end of the input inductor (L) is connected with the positive output end of the direct current power supply (Vdc); the drain electrode of the fifth power switch tube (S5) is connected with the negative end of the input inductor (L) and the source electrode of the first power switch tube (S1), and the source electrode of the fifth power switch tube (S5) is connected with the negative end of the direct current power supply (Vdc), the drain electrode of the second power switch tube (S2) and the ground; the positive end of the first capacitor (C1) is connected with the drain electrode of the first power switch tube (S1) and the port 1 of the expandable switch capacitor unit (M2), and the negative end of the first capacitor (C1) is connected with the source electrode of the second power switch tube (S2) and the port 2 of the expandable switch capacitor unit (M2); the basic boosting unit (M1) can output +V c ，0，-V c Three levels, where V c For modulating the voltage of the capacitor, V c ＝V dc /(1-D), where d=t on Ts, ts is the switching period, t on The inductor charge time is for each switching cycle of the inductor.
The expandable switch capacitance unit (M2) is formed by a plurality of switch capacitance units(K1-Kn), each switched capacitor unit (Kn) comprises four ports, namely port 1, port 2, port 3 and port 4, each switched capacitor unit (Kn) can output +V c ，0，-V c Three levels; and when the number of the units is n, the number of the expandable switch capacitor units (M2) is 2n+3, and n is a natural number greater than or equal to 1.
The output unit (M3) comprises a third power switch tube (S3) and a fourth power switch tube (S4). The drain electrode of the third power switch tube (S3) is connected with the port 3 of the expandable switch capacitor unit (M2), and the source electrode of the fourth power switch tube (S4) is connected with the port 4 of the expandable switch capacitor unit (M2); the source electrode of the third power switch tube (S3) is connected with the drain electrode of the fourth power switch tube (S4) and the ground to form an output port V o 。
2. The common-ground type switched-capacitor multilevel inverter according to claim 1, wherein the switched-capacitor scalable unit (M2) may be, but is not limited to, a series-parallel type, a cascade type, a ladder type switched-capacitor topology.
3. The common-ground type switched capacitor multi-level inverter according to claim 1, wherein the unidirectional voltage-withstanding power switch tube adopts a fully-controlled power electronic device, which can be, but is not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT); the bi-directional voltage-resistant power switch tube can be formed by, but not limited to, two Metal Oxide Semiconductor Field Effect Transistor (MOSFET) common source electrode in series connection.
4. A method of switching control of a common-mode switched capacitor inverter based on continuous input current as claimed in claim 1, characterized by:
the capacitors in the basic boosting unit (M1) and the expandable switch capacitor unit (M2) can output multi-level alternating voltage in a series-parallel connection mode, and the common-ground switch capacitor inverter can be controlled in a sine pulse width modulation mode. When the peak value of the alternating current output voltage is (n+1) V c In this case, n switched capacitor units (K1 to Kn) are required. The specific control time sequence is as follows:
when the output voltage is at zero level (V o =0), the circuit has two modes of operation, the first mode of operation being: the first power switch tube (S1), the second power switch tube (S2) and the fourth power switch tube (S4) are turned on, the third power switch tube (S3) and the fifth power switch tube (S5) are turned off, all the expandable switch capacitance units (M2) output zero level, at the moment, the basic boosting unit (M1) charges the first capacitor (C1) and the capacitors in the switch capacitance expandable units (M2) to V c The duration of this state is t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the third power switch tube (S3) are turned off, the expandable switch capacitance unit (M2) outputs zero level, and at the moment, the basic boosting unit (M1) charges the first capacitor (C1) and the capacitor in the switch capacitance expandable unit (M2) to V c The duration of this state is t on_0 ；
When the output voltage is at positive level (V o ＝+V c ) When the circuit has two working modes, the first working mode is as follows: the first power switch tube (S1), the second power switch tube (S2) and the third power switch tube (S3) are turned on, the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned off, the expandable switch capacitance unit (M2) outputs a level, and at the moment, the basic boosting unit (M1) charges the first capacitor (C1) and the capacitor in the switch capacitance expandable unit (M2) to V c At the same time give the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs a level, and at the moment, the direct current power supply (V dc ) Charging the input inductance (L), the first capacitor (C1) and the capacitor in the switched capacitor scalable unit (M2) being connected in parallel to the load Z o Power is supplied for a period of time t on_P1 ；
When the output voltage is positive j level (V o ＝+jV c ) When (1 < j < n+1, and j is an integer), the circuit has two working modes, and when in a first working mode: the first power switch tube (S1), the second power switch tube (S2) and the third power switch tube (S3) are turned on, the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned off, the output j level of the switch capacitor unit (M2) can be expanded, at the moment, the capacitors in the switch capacitor unit (K1) to the switch capacitor unit (K (j-1)) are connected with the first capacitor (C1) in parallel, and the basic boost unit (M1) is charged to V c The capacitor in the switch capacitor unit (Kj) to the switch capacitor unit (Kn) and the basic boosting unit (M1) are connected in series to the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs j level, and at the moment, the direct current power supply (V dc ) Charging the input inductor (L), connecting the capacitor in the switch capacitor unit (K1) to the switch capacitor unit (K (j-1)) in parallel with the first capacitor (C1), and connecting the capacitor in the switch capacitor unit (Kj) to the switch capacitor unit (Kn) in series to the load Z o Power is supplied for a period of time t on_Pj ；
When the output voltage is at positive (n+1) level (V o ＝+(n+1)V c ) When the circuit has an operating mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs n level, at the moment, the direct current power supply (V dc ) Charging an input inductance (L), and connecting the capacitances in the switched capacitor units (K1) to (Kn) in series with the first capacitance (C1) to a load Z o Power is supplied for a period of time t on_P(n+1) ；
When the output voltage is negative one level (V o ＝-V c ) When the circuit has two working modes, the first working mode is as follows: the first power switch tube (S1), the second power switch tube (S2) and the fourth power switch tube (S4) are turned on, the third power switch tube (S3) and the fifth power switch tube (S5) are turned off, and the expandable switch capacitor unit (M2) outputs negative oneAt this time, the capacitor of the switch capacitor unit (K1) to the switch capacitor unit (K (n-1)) is connected in parallel with the first capacitor (C1), and is charged to V by the basic boosting unit (M1) c The switched capacitor unit (Kn) gives the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs a negative level, and at the moment, the direct current power supply (V dc ) Charging the input inductance (L), the capacitance in the switched capacitor unit (K1) to the switched capacitor unit (K (n-1)) and the first capacitance (C1) are not operated, and the switched capacitor unit (Kn) gives the load Z o Power is supplied for a period of time t on_N1 ；
When the output voltage is negative j level (V o ＝-jV c ) When (1 < j < n+1, and j is an integer), the circuit has two working modes, and when in a first working mode: the first power switch tube (S1), the second power switch tube (S2) and the fourth power switch tube (S4) are turned on, the third power switch tube (S3) and the fifth power switch tube (S5) are turned off, the expandable switch capacitance unit (M2) outputs negative j level, at the moment, the capacitance in the switch capacitance unit (K1) to the switch capacitance unit (K (n-j)) is connected in parallel with the first capacitance (C1), and the basic boost unit (M1) is charged to V c The capacitors in the switch capacitor units (K (n-j+1)) -switch capacitor units (Kn) are serially connected to the load Z o Power is supplied for a period of time t off The method comprises the steps of carrying out a first treatment on the surface of the And in the second working mode: the second power switch tube (S2), the third power switch tube (S3) and the fifth power switch tube (S5) are turned on, the first power switch tube (S1) and the fourth power switch tube (S4) are turned off, the expandable switch capacitor unit (M2) outputs negative j level, and at the moment, the direct current power supply (V dc ) The input inductor (L) is charged, the switch capacitor units (K1) to (K (n-j)) and the first capacitor (C1) do not work, and the capacitors in the switch capacitor units (K (n-j+1)) to (Kn) are connected in series to the load Z o Power is supplied for a period of time t on_Nj ；
When the output voltage is negative (n+1) level (V o ＝-(n+1)V c ) Circuit for time-consumingThere is one mode of operation: the first power switch tube (S1), the fourth power switch tube (S4) and the fifth power switch tube (S5) are turned on, the second power switch tube (S2) and the third power switch tube (S3) are turned off, the expandable switch capacitor unit (M2) outputs negative n level, and at the moment, the direct current power supply (V dc ) Charging an input inductance (L), and connecting the capacitances in the switched capacitor units (K1) to (Kn) in series with the first capacitance (C1) to a load Z o Power is supplied for a period of time t on_N(n+1) ；。
5. A method of switching control of a common-mode switched capacitor inverter based on continuous input current as claimed in claim 4, wherein t on ＝DTs、t off = (1-D) Ts, which contains the turn-on time t of the respective level input inductance (L) on_0 、t on_P1 、t on_Pj 、t on_P(n+1) 、t on_N1 、t on_Nj And t on_N(n+1) The relationship between these is shown in Table I below.
Table I relationship of the on time of the various level input inductors (L)
Where Vm is the modulated carrier, vm=msin (100 pi t), M is the modulation index, ac is the triangular carrier amplitude, ac=1/(n+1), to is the output period.
CN202310315077.7A 2023-03-28 2023-03-28 Common-ground type switched capacitor inverter with continuous input current and control method thereof Pending CN116647119A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117477975A (en) * 2023-12-27 2024-01-30 南京理工大学 Common-ground type switch capacitor multi-level inverter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117477975A (en) * 2023-12-27 2024-01-30 南京理工大学 Common-ground type switch capacitor multi-level inverter

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