CN116632000A - Field effect transistor layout structure with uniformly distributed charges and design method thereof - Google Patents
Field effect transistor layout structure with uniformly distributed charges and design method thereof Download PDFInfo
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- H01L27/0203—Particular design considerations for integrated circuits
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Abstract
The application belongs to the technical field of semiconductor integrated circuits, and discloses a field effect transistor layout structure with uniformly distributed charges and a design method thereof, wherein the layout structure comprises a first number of capacitive device units and a second number of field effect transistor units; the capacitive device unit and the field effect transistor unit are arranged side by side in an interdigital mode. The application can ensure uniform charge distribution in the field effect transistor, and avoid the condition of nonuniform charge distribution in the field effect transistor unit caused by the fact that the capacitive device unit is independently arranged on one side of the field effect transistor. And the method is applicable to chip manufacturing processes of any size, and is not limited by the chip manufacturing process size.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to a field effect transistor layout structure with uniformly distributed charges and a design method thereof.
Background
In a chip, a field effect transistor is a common device, and when a power supply supplies power to the field effect transistor through a wire, a voltage drop problem is unavoidable due to parasitic resistance and capacitance of the wire.
If the voltage drop on a certain field effect transistor is too large, the normal operation of the field effect transistor is affected, and the whole chip where the field effect transistor is located is disabled. The voltage drop of the field effect transistor is controlled within an acceptable range, typically by voltage drop simulation. Since the current on the fet is a time-varying curve, the voltage drop is generally severe only at the peak of the current, and the voltage drop is usually controlled by: first kind: the resistance is reduced by widening the field effect tube wire or increasing the contact hole, thereby achieving the purpose of reducing the voltage drop; second kind: and a plurality of capacitive devices are arranged near the field effect tube and connected to a power line, so that the charge capacity near the field effect tube is increased, and the transient voltage drop is relieved.
However, when the size of the chip manufacturing process is below 22nm, the width and the spacing of the wires cannot be increased or decreased at will, and the wires must be placed according to the fixed width and the spacing, so that the first mode cannot be applied to the field effect transistor in the chip manufacturing process below 22 nm; the second mode can lead to more charge distribution on one side of the field effect transistor close to the capacitive device and less charge on the other side of the field effect transistor far from the capacitor, so that the problem of uneven charge distribution on the field effect transistor occurs.
Disclosure of Invention
The application provides a field effect transistor layout structure with uniformly distributed charges and a design method thereof, which can ensure uniform charge distribution in a field effect transistor and avoid the condition of nonuniform charge distribution in the field effect transistor unit caused by the fact that a capacitive device unit is independently arranged at one side of the field effect transistor; and the method is applicable to chip manufacturing processes of any size, and is not limited by the chip manufacturing process size.
In a first aspect, an embodiment of the present application provides a field effect transistor layout structure with uniformly distributed charges, where the layout structure includes a first number of capacitive device units and a second number of field effect transistor units;
the capacitive device unit and the field effect transistor unit are arranged side by side in an interdigital mode.
Further, the field effect transistor unit includes a metal-oxide semiconductor field effect transistor and a fin field effect transistor.
The embodiment shows that the layout structure of the application is suitable for various field effect transistors, and the applicability of the application is improved.
Further, the ratio of the first amount to the second amount is N1, N comprising any integer from 1 to 5.
The embodiment enables the layout structure of the application to cope with different current changes and layout area requirements.
Further, when the first number is 4 and the second number is 2, the layout structure is sequentially from left to right:
the first capacitive device unit, the first field effect transistor unit, the second capacitive device unit, the third capacitive device unit, the second field effect transistor unit and the fourth capacitive device unit; the first, second, third and fourth capacitive device units have the same structure; the first field effect transistor unit and the second field effect transistor unit have the same structure.
The embodiment is a layout structure when the ratio of the first number to the second number is 2:1, and is suitable for more common situations.
Further, the capacitive device unit comprises a capacitive field effect transistor, and the capacitive field effect transistor comprises a first active region, a first grid electrode, a first power supply wire and a grounding wire; the first active region is connected with a first power wire, and the first grid electrode is connected with a grounding wire.
The embodiment shares the charge of the field effect transistor unit through the arrangement of the capacitance field effect transistor, and stabilizes the transient voltage fluctuation.
Further, the field effect transistor unit comprises a work field effect transistor; the work field effect transistor comprises a second active area, a second grid electrode, a second power supply wire, an input wire and an output wire;
the second active region is connected with the second power wire and the output wire respectively, and the second grid electrode is connected with the input wire.
According to the embodiment, the field effect transistor unit can receive the input signal through the connection of the input wire and the output wire, so that the working effect of amplifying the input signal is achieved and output.
Further, in the adjacent capacitor field effect transistor and the working field effect transistor, the first power supply wire and the second power supply wire are the same power supply wire.
The embodiment saves the number of power wires, reduces the power resistance and indirectly relieves the voltage drop of the field effect transistor.
Further, when the field effect transistor unit is a metal-oxide semiconductor field effect transistor, a plurality of contact holes are formed in the first power supply wire and the second power supply wire; the first power supply wire is connected with the first active region through a plurality of contact holes, and the second power supply wire is connected with the second active region through a plurality of contact holes.
According to the embodiment, the contact holes are added on the first power wire and the second power wire, so that the field effect transistor under the prior chip manufacturing process can further reduce the power resistance and relieve the voltage drop.
Further, the layout structure further comprises a substrate; the first power supply wire, the second power supply wire, the grounding wire, the input wire and the output wire in the layout structure are all arranged on the substrate.
The above embodiment locates each wire on the substrate, and plays the roles of physical support, heat conduction and electric conduction through the substrate.
In a second aspect, the present application further provides a method for designing a layout structure of a field effect transistor with uniformly distributed charges, where the method includes: providing an initial layout, wherein the initial layout comprises a capacitive device area and a field effect area which are adjacent;
splitting the capacitive device areas according to a first preset rule to obtain a first number of capacitive device units;
splitting the field effect tube region according to a second preset rule to obtain a second number of field effect tube units; and splicing the first number of the capacitive device units and the second number of the field effect transistor units in an interdigital mode to obtain a target layout.
In summary, compared with the prior art, the technical scheme provided by the embodiment of the application has the following beneficial effects:
according to the field effect transistor layout structure with the uniform charge distribution, the capacitive device units and the field effect transistor units are arranged side by side in an interdigital mode, so that the charge distribution in the field effect transistor units is ensured to be uniform while the voltage fluctuation is stabilized and the voltage drop of the field effect transistor is relieved by using the capacitive device units, and the condition that the charge distribution in the field effect transistor units is nonuniform due to the fact that the capacitive device units are all arranged on one side of the field effect transistor units is avoided; the interdigital arrangement can be applied to any chip manufacturing process without being limited by the chip manufacturing process.
Drawings
Fig. 1 is a layout of a layout structure of a field effect transistor with uniformly distributed charges when a field effect transistor unit provided by an embodiment of the present application is a metal-oxide semiconductor field effect transistor.
Fig. 2 is a cross-sectional view of a layout structure of a field effect transistor with uniformly distributed charges when the field effect transistor unit provided by the embodiment of the application is a metal-oxide semiconductor field effect transistor.
Fig. 3 is a layout diagram of a layout structure of a field effect transistor with uniformly distributed charges when a field effect transistor unit provided by an embodiment of the present application is a fin field effect transistor.
Fig. 4 is a single-core cross-sectional view of a field effect transistor layout structure with uniformly distributed charges when the field effect transistor unit provided by the embodiment of the application is a fin field effect transistor.
Fig. 5 is an evolution diagram of a layout structure of a field effect transistor with uniformly distributed charges when the field effect transistor unit provided by the embodiment of the application is a metal-oxide semiconductor field effect transistor.
Fig. 6 is an evolution diagram of a field effect transistor layout structure with uniformly distributed charges when the field effect transistor unit provided by the embodiment of the application is a metal-oxide semiconductor field effect transistor.
Fig. 7 is a flowchart of a design method of a field effect transistor layout structure with uniformly distributed charges according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a field effect transistor structure for alleviating voltage drop by using a method (method a) of widening a wire and increasing a contact hole in the prior art according to an embodiment of the present application.
Fig. 9 is a schematic diagram of a field effect transistor structure for alleviating voltage drop by using a method (method b) of placing a plurality of capacitive device units in the prior art according to an embodiment of the present application.
Reference numerals illustrate:
01. a capacitive device cell; 02. a field effect transistor unit; 03. a power supply wire; 04. a ground wire; 05. an input wire; 06. an output wire; 07. a first active region; 08. a contact hole; 09. a substrate.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, an embodiment of the present application provides a field effect transistor layout structure with uniformly distributed charges, where the layout structure includes a first number of capacitive device units 01 and a second number of field effect transistor units 02.
The capacitive device unit 01 and the field effect transistor unit 02 are arranged side by side in an interdigital manner.
According to the field effect transistor layout structure with the charges uniformly distributed, the capacitive device units 01 and the field effect transistor units 02 are arranged side by side in an interdigital mode, so that the voltage fluctuation can be stabilized by the capacitive device units 01, the voltage drop of the field effect transistor is relieved, the charges in the field effect transistor units 02 are uniformly distributed, and the condition that the charges in the field effect transistor units 02 are unevenly distributed due to the fact that all the capacitive device units 01 are arranged on one side of the field effect transistor units 02 is avoided; the interdigital arrangement can be applied to any chip manufacturing process without being limited by the chip manufacturing process.
Referring to fig. 1-4, in some embodiments, the fet cell 02 may include a metal-oxide semiconductor fet and a fin fet. The metal-oxide semiconductor field effect transistor is a MOSFET field effect transistor.
The fin field effect transistor is a FINFET field effect transistor; as can be seen from fig. 3, when the fet unit 02 is a finfet, n mandrels in the finfet are disposed perpendicular to the wires.
The embodiment shows that the layout structure of the application is suitable for various field effect transistors, and the applicability of the application is improved.
In some embodiments, the ratio of the first number to the second number is N1, N comprising any integer from 1 to 5.
The number of the capacitive device units 01 in the field effect transistor can be changed according to the actual current situation or the layout area requirement, and at the moment, the ratio of the first number to the second number needs to be adjusted.
For example, if the number ratio of the capacitive device units 01 to the field effect transistor units 02 in an embodiment is 1:1, 2 field effect transistor units 02 are sandwiched between 2 capacitive device units 01 and are placed alternately on the layout.
When the current peak is large, the first number of the capacitive device units in this embodiment may need to be increased, and the ratio of N to 1 may be changed to 2:1 or other, and the capacitive device units 01 and the field effect transistor units 02 in this embodiment may be changed to 4 capacitive device units 01 and 2 field effect transistor units 02; and vice versa.
The embodiment enables the layout structure of the application to cope with different current changes and layout area requirements.
Referring to fig. 1, in some embodiments, when the first number is 4 and the second number is 2, the layout structure is: the first capacitive device unit, the first field effect transistor unit, the second capacitive device unit, the third capacitive device unit, the second field effect transistor unit and the fourth capacitive device unit; the first, second, third and fourth capacitive device units have the same structure; the first field effect transistor unit and the second field effect transistor unit have the same structure.
Specifically, when the first number and the second number are both 4, the layout structure arranged side by side in the interdigital manner sequentially comprises, from left to right: the first capacitive device unit, the first field effect transistor unit, the second capacitive device unit, the third field effect transistor unit, the fourth field effect transistor unit and the fourth capacitive device unit.
Further, when the first number is larger and the second number is smaller, for example: when the first number is 6 and the second number is 2, the field effect transistor layout structure arranged side by side in an interdigital mode sequentially comprises the following components from left to right:
the first, second, first, third, fourth, second, fifth and sixth capacitive device units.
In a specific implementation, the first number and the second number are set by the desired operating effect of the field effect transistor.
The embodiment is a layout structure when the ratio of the first number to the second number is 2:1, and is suitable for more common situations.
Referring to fig. 1-6, in some embodiments, a capacitive device cell 01 includes a capacitive field effect transistor including a first active region 07, a first gate, a first power supply lead, and a ground lead 04; the first active region 07 is connected to a first power supply line and the first gate is connected to a ground line 04.
The above embodiment shares the charge of the fet unit 02 by the arrangement of the capacitive fet, stabilizing the transient voltage fluctuations.
Referring to fig. 1-6, in some embodiments, fet unit 02 includes an active fet; the work field effect transistor comprises a second active area, a second grid electrode, a second power wire, an input wire 05 and an output wire 06; the second active region is connected to a second power supply line and output line 06, respectively, and the second gate is connected to input line 05.
Specifically, field effect transistor co-quadrupoles are typically operated: source, drain, second gate and substrate 09, both source and drain are in the second active region. In operation, the second gate applies an electric field to the second active region, forming a conductive channel between the source and drain.
The above embodiment ensures that the fet unit 02 can receive an input signal by connecting the input wire 05 and the output wire 06, and achieves the working effect of amplifying the input signal and outputting the amplified input signal.
Referring to fig. 1-6, in some embodiments, the first power conductor and the second power conductor are the same power conductor 03 in adjacent capacitive field effect transistors and active field effect transistors.
Specifically, when the first number is 4 and the second number is 2, the power supply wires 03 between the adjacent capacitive field effect transistors and the operating field effect transistor are the same.
The embodiment saves the number of the power wires 03, reduces the power resistance and indirectly relieves the voltage drop of the field effect transistor.
Referring to fig. 1 and 2, in some embodiments, when the fet unit 02 is a metal-oxide semiconductor fet, a plurality of contact holes 08 are formed in each of the first power supply line and the second power supply line; the first power supply wire is connected with the first active region 07 through a plurality of contact holes 08, and the second power supply wire is connected with the second active region through a plurality of contact holes 08.
In the embodiment, the contact holes 08 are added on the first power wire and the second power wire, so that the field effect transistor under the prior chip manufacturing process can further reduce the power resistance and relieve the voltage drop.
Referring to fig. 2 and 4, in some embodiments, the layout structure further includes a substrate 09; the first power supply wire, the second power supply wire, the ground wire 04, the input wire 05 and the output wire 06 in the layout structure are all arranged on the substrate 09.
The above embodiment locates each wire on the substrate 09, and performs the functions of physical support, heat conduction and electric conduction through the substrate 09.
Referring to fig. 5, fig. 6, and fig. 7, in some embodiments, the present application further provides a method for designing a layout structure of a field effect transistor with uniformly distributed charges, where the method includes:
step S1, providing an initial layout, wherein the initial layout comprises a capacitive device area and a field effect area which are adjacent;
step S2, splitting the capacitive device areas according to a first preset rule to obtain a first number of capacitive device units;
step S3, splitting the field effect tube areas according to a second preset rule to obtain a second number of field effect tube units;
and S4, splicing the first number of the capacitive device units and the second number of the field effect transistor units in an interdigital mode to obtain a target layout. Specifically, the first preset rule and the second preset rule are specified by a user, and the user can select the division mode of the capacitive device unit and the field effect transistor unit according to actual needs.
According to the design method of the field effect transistor layout structure with the uniform charge distribution, the split capacitive device units and the field effect transistor units are arranged side by side in an interdigital mode, so that the voltage fluctuation can be stabilized by the capacitive device units, the voltage drop of the field effect transistor can be relieved, the uniform charge distribution in the field effect transistor units is ensured, and the condition that the nonuniform charge distribution in the field effect transistor units is caused by the fact that all the capacitive device units are arranged on one side of the field effect transistor units is avoided; the interdigital arrangement can be applied to any chip manufacturing process without being limited by the chip manufacturing process.
The implementation process of the field effect transistor layout structure with uniformly distributed charges and the design method thereof is described by using the capacitive device unit 01 and the field effect transistor unit 02 as MOSFETs: in a chip, a MOSFET is a common device, and when a power supply is supplied to the MOSFET through a wire, a voltage drop problem will be unavoidable due to parasitic resistance and capacitance of the wire.
If the voltage drop across a MOSFET device is too large, it can affect the proper operation of the MOSFET and may cause the entire chip to fail. The MOSFET voltage drop is typically controlled to be within an acceptable range by voltage drop simulation.
As can be seen from the formula (voltage=current×resistance), the method of controlling voltage drop generally includes:
a. when the current of the MOSFET device is larger due to design requirements, the resistance can be reduced by widening the conductive line or increasing the contact hole, so as to achieve the purpose of reducing the voltage drop, as shown in fig. 8.
b. Since the current on a MOSFET is a time-varying curve, the voltage drop is typically only significant at the peak of the current. A capacitive device region may be placed near the field effect transistor region where the MOSFET is located and connected to the power line to increase the charge capacity near the MOSFET to mitigate the transient voltage drop, as shown in fig. 9.
When the advanced process of the chip is entered, the voltage drop problem becomes more serious, and the width and the spacing of the wires on the MOSFET cannot be increased or decreased at will due to the limitation of the process rule, and the wires must be placed according to the fixed width and spacing, which results in that the method a cannot be realized by simply widening the wires, and the method b has the problem of uneven distribution of the stored charges of the power supply.
Therefore, based on the above-mentioned problems, aiming at the purpose of controlling the voltage drop of the MOSFET in the advanced chip process, the MOSFET capacitor for increasing the power supply charge is spliced around the operating MOSFET in an interdigital manner, as shown in fig. 5 and 6, and the advantages of the methods a and b are considered, under the same layout area, the power supply side wire resistance is reduced in the foregoing method a, the power supply side charge with the same capacity is increased in the foregoing method b, and meanwhile, the problem of uneven distribution of the power supply storage charge capacity in the method b is avoided. Meanwhile, the power supply resistance is reduced, the charge capacity on the power supply is guaranteed, and the instantaneous voltage fluctuation during working is stabilized.
The layout structure of the application is simultaneously suitable for the FINFET technology, and when the capacitive device unit 01 and the field effect transistor unit 02 are FINFETs, the layout structure of the application is unchanged, and the difference is only the layout difference caused by the FINFET technology. As shown in fig. 3 and fig. 4, under the finfet process, the three-dimensional structure of the whole fet layout structure is different from that of the MOSFET, and becomes a fin type. It is understood that the contact hole under the first layer of metal is not required. Fig. 3 is a front view of a single mandrel in a FINFET (each FINFET would consist of multiple mandrels). As shown in fig. 5 to 6, when the capacitive device unit 01 and the field effect transistor unit 02 are MOSFETs, in the case that a contact hole 08 is provided on each power supply wire 03 and the capacitive device unit 01 is adjacent to the right side of the field effect transistor unit 02, the capacitive device unit 01 and the field effect transistor unit 02 are separated according to separation lines, so as to obtain 2 field effect transistor units 02 and 4 capacitive device units 01; and then splicing the adjacent power supply wires in an interdigital mode, and combining the adjacent power supply wires into one piece to obtain the field effect transistor layout structure with uniformly distributed charges.
Under the layout structure of the field effect transistor, when a plurality of field effect transistor units 02 which are MOSFETs are connected in series, the drain electrode of the MOSFET of the upper stage is the source electrode of the MOSFET of the lower stage.
The number of the capacitive device units 01 in the field effect transistor can be changed according to the actual current situation or the layout area requirement, and at the moment, the ratio of the first number to the second number needs to be adjusted. For example, if the number ratio of the capacitive device units 01 to the field effect transistor units 02 in an embodiment is 1:1, 2 field effect transistor units 02 are sandwiched between 2 capacitive device units 01 and are placed alternately on the layout. When the current peak is large, the first number of the capacitive device units 01 in this embodiment may need to be increased, the ratio of N to 1 may be changed to 2:1 or other, and the capacitive device units 01 and the field effect transistor units 02 in this embodiment may be changed to 4 capacitive device units 01 and 2 field effect transistor units 02; and vice versa.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description. The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. The field effect transistor layout structure with uniformly distributed charges is characterized by comprising a first number of capacitive device units and a second number of field effect transistor units;
the capacitive device unit and the field effect transistor unit are arranged side by side in an interdigital mode.
2. The layout structure of claim 1, wherein the fet cells comprise metal-oxide semiconductor field effect transistors and fin field effect transistors.
3. The layout structure according to claim 2, wherein the ratio of the first number to the second number is n:1, the N comprising any integer from 1 to 5.
4. A layout structure according to claim 3, wherein when the first number is 4 and the second number is 2, the layout structure is: the first capacitive device unit, the first field effect transistor unit, the second capacitive device unit, the third capacitive device unit, the second field effect transistor unit and the fourth capacitive device unit;
the first capacitive device unit, the second capacitive device unit, the third capacitive device unit and the fourth capacitive device unit have the same structure; the first field effect transistor unit and the second field effect transistor unit have the same structure.
5. The layout structure of claim 4, wherein the capacitive device cell comprises a capacitive field effect transistor comprising a first active region, a first gate, a first power conductor, and a ground conductor;
the first active region is connected with the first power supply wire, and the first grid electrode is connected with the grounding wire.
6. The layout structure of claim 5, wherein the fet unit comprises an active fet; the work field effect transistor comprises a second active area, a second grid electrode, a second power supply wire, an input wire and an output wire; the second active region is connected with the second power supply wire and the output wire respectively, and the second grid electrode is connected with the input wire.
7. The layout structure of claim 6 wherein said first power conductor and said second power conductor are the same power conductor in adjacent ones of said capacitive field effect transistor and said work field effect transistor.
8. The layout structure according to claim 7, wherein when the fet unit is the metal-oxide semiconductor fet, a plurality of contact holes are provided on both the first power supply wire and the second power supply wire;
the first power supply lead is connected with the first active area through a plurality of contact holes, and the second power supply lead is connected with the second active area through a plurality of contact holes.
9. The layout structure according to claim 7, further comprising a substrate;
the first power supply wire, the second power supply wire, the grounding wire, the input wire and the output wire in the layout structure are all arranged on the substrate.
10. A design method of a field effect transistor layout structure with uniformly distributed charges is characterized by comprising the following steps:
providing an initial layout, wherein the initial layout comprises a capacitive device area and a field effect area which are adjacent;
splitting the capacitive device region according to a first preset rule to obtain a first number of capacitive device units;
splitting the field effect tube region according to a second preset rule to obtain a second number of field effect tube units;
and splicing the first number of the capacitive device units and the second number of the field effect transistor units in an interdigital mode to obtain a target layout.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7600208B1 (en) * | 2007-01-31 | 2009-10-06 | Cadence Design Systems, Inc. | Automatic placement of decoupling capacitors |
| CN104426510A (en) * | 2013-08-07 | 2015-03-18 | 天工方案公司 | Field-effect transistor stack voltage compensation |
| CN105762134A (en) * | 2015-01-06 | 2016-07-13 | 联发科技股份有限公司 | Integrated Circuit Device And Method For Forming The Same |
| CN106656128A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Voltage homogenization method for radio frequency switch with multiple serially connected transistors and radio frequency switch |
| CN111916444A (en) * | 2020-08-14 | 2020-11-10 | 泉芯集成电路制造(济南)有限公司 | Electrical property analysis layout for finger-shaped structure fin field effect transistor |
| CN112241618A (en) * | 2019-07-19 | 2021-01-19 | 恩智浦有限公司 | Integrated circuit with functional cells and reconfigurable decoupling cells |
| CN114220798A (en) * | 2022-02-22 | 2022-03-22 | 苏州浪潮智能科技有限公司 | Method for filling redundant metal in chip, chip and semiconductor device |
| CN114492285A (en) * | 2022-01-09 | 2022-05-13 | 西北大学 | Layout design method for improving ESD protection capability of interdigital structure device |
-
2023
- 2023-05-25 CN CN202310596394.0A patent/CN116632000B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7600208B1 (en) * | 2007-01-31 | 2009-10-06 | Cadence Design Systems, Inc. | Automatic placement of decoupling capacitors |
| CN104426510A (en) * | 2013-08-07 | 2015-03-18 | 天工方案公司 | Field-effect transistor stack voltage compensation |
| CN105762134A (en) * | 2015-01-06 | 2016-07-13 | 联发科技股份有限公司 | Integrated Circuit Device And Method For Forming The Same |
| CN106656128A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Voltage homogenization method for radio frequency switch with multiple serially connected transistors and radio frequency switch |
| CN112241618A (en) * | 2019-07-19 | 2021-01-19 | 恩智浦有限公司 | Integrated circuit with functional cells and reconfigurable decoupling cells |
| CN111916444A (en) * | 2020-08-14 | 2020-11-10 | 泉芯集成电路制造(济南)有限公司 | Electrical property analysis layout for finger-shaped structure fin field effect transistor |
| CN114492285A (en) * | 2022-01-09 | 2022-05-13 | 西北大学 | Layout design method for improving ESD protection capability of interdigital structure device |
| CN114220798A (en) * | 2022-02-22 | 2022-03-22 | 苏州浪潮智能科技有限公司 | Method for filling redundant metal in chip, chip and semiconductor device |
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