CN116631944B - High-temperature pressure resistance characteristic sample and preparation method of special-shaped silicon adapter plate containing TSV - Google Patents
High-temperature pressure resistance characteristic sample and preparation method of special-shaped silicon adapter plate containing TSV Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 113
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 112
- 239000010703 silicon Substances 0.000 title claims abstract description 112
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000010936 titanium Substances 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 27
- 230000003287 optical effect Effects 0.000 claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052802 copper Inorganic materials 0.000 claims abstract description 22
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 45
- 239000010410 layer Substances 0.000 claims description 43
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- 238000004519 manufacturing process Methods 0.000 claims description 30
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
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- 229910052697 platinum Inorganic materials 0.000 claims description 9
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- 239000000126 substance Substances 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 6
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- 238000009792 diffusion process Methods 0.000 claims description 5
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- 238000011049 filling Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 239000003870 refractory metal Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000003631 wet chemical etching Methods 0.000 claims description 3
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- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021352 titanium disilicide Inorganic materials 0.000 abstract description 9
- 239000013307 optical fiber Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 61
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- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application discloses a high-temperature pressure resistance characteristic sample and a preparation method of a special-shaped silicon adapter plate containing TSV. Meanwhile, the application provides a high-temperature-resistant ohmic contact electrode structure silicon/titanium disilicide/titanium nitride/titanium/copper compatible with the TSV technology of the through silicon vias for high-temperature application, and can be used for measuring the high-temperature pressure resistance characteristics above 300 ℃. In addition, the special-shaped silicon adapter plate containing the TSV is beneficial to aligning an incident optical fiber with an end face coupler of a silicon optical device, and realizes an electric-optical-sensing three-dimensional heterogeneous integrated system.
Description
Technical Field
The application belongs to the technical field of electronics, and particularly relates to a high-temperature pressure resistance characteristic sample and a preparation method of a special-shaped silicon adapter plate containing TSV.
Background
Along with the moore's law followed by the development of the traditional silicon-based integrated circuit industry, the bottleneck is met, and advanced packaging technology represented by three-dimensional heterogeneous integration of Through Silicon Vias (TSVs) becomes an important technology for further improving the integrated circuit integration level and system functions. In recent years, in order to meet urgent demands of the internet of things, big data and artificial intelligence for stronger calculation power, higher transmission rate and more sensitive perception of electronic systems, people are not limited to just three-dimensional stacking of integrated circuit chips, and three-dimensional heterogeneous integration (EIC-PIC-MEMS) of integrated circuit chips, silicon-based optoelectronic chips, sensing chips and other chips with different functions, different structures and even different shapes on a Wafer is started, so that a System-on-chip (SOW) with more powerful functions is formed.
In the three-dimensional heterogeneous integration process of electro-optical-sensing, silicon adapter plates with different shapes are often designed according to the shape and working requirements of devices, but silicon is a crystal, so that the silicon is easily split along a cleavage plane. When manufacturing the special-shaped silicon adapter plate, if a mechanical knife or laser is directly used for carrying out scribing and cutting on the silicon wafer along an irregular shape, the silicon wafer is easily broken due to uneven defects and stress.
In addition to the need for special-shaped dicing of silicon wafers in three-dimensional isomerically integrated silicon interposer, special-shaped silicon structures are often required for the preparation of piezoresistive property samples of silicon. In order to prevent the specimen from breaking in the vicinity of the clamp port, the specimen is usually required to be dumbbell-shaped, referring to the specification of the tensile specimen in the national standards for tensile test of metals and rubbers, such as GB/T4338-2006 method for high temperature tensile test of metallic materials, GB/T528-2009 method for measuring tensile stress strain properties of vulcanized rubber or thermoplastic rubber. When the tensile method is used for measuring the piezoresistive property of silicon, the dumbbell-shaped sample can keep the wider stress at the two ends stable, and can ensure that the force-sensitive resistor strip at the middle narrow part generates larger strain under the condition of the same acting force, so that enough resistance value change is generated. However, the preparation of dumbbell-shaped samples of piezoresistive properties is also at risk of irregular cutting and cracking of the wafer.
Disclosure of Invention
The embodiment of the application aims to solve the problems in the prior art and provide a high-temperature pressure resistance characteristic sample and a preparation method of a special-shaped silicon adapter plate containing TSVs so as to realize special-shaped cutting of wafers.
According to a first aspect of an embodiment of the present application, there is provided a method for preparing a high-temperature pressure resistance characteristic sample, including:
the device manufacturing steps are as follows: photoetching and etching the shape of the force-sensitive resistor on a device layer on the upper surface of the wafer, and carrying out ion implantation and annealing based on the shape of the force-sensitive resistor to form the force-sensitive resistor;
a first high temperature resistant electrode and interconnection line manufacturing step: depositing a first passivation layer on the upper surface and the lower surface of the wafer, photoetching and etching the first passivation layer on the ohmic contact area of the force-sensitive resistor to expose silicon of the device layer, so as to grow a high-temperature-resistant ohmic contact electrode and an interconnection line;
a first upper surface profile groove deep etching step: photoetching and deeply etching a first external groove and a through hole on the upper surface of the wafer, wherein the depth of the first external groove and the through hole is the required sample depth;
a first lower surface thinning release step: and protecting the upper surface of the wafer, thinning the lower surface of the wafer until the high-temperature pressure resistance characteristic sample is released, and removing the protection of the upper surface to obtain the required high-temperature pressure resistance characteristic sample.
Further, a silicon dioxide/silicon nitride layer is deposited using a plasma enhanced chemical vapor deposition method to deposit the first passivation layer.
Further, in the manufacturing steps of the first high-temperature-resistant electrode and the interconnection line, photoetching and etching the silicon of the ohmic contact area of the first passivation layer exposing the force-sensitive resistor, heavily doping and annealing; growing refractory metal silicide on the silicon of the ohmic contact region by a self-alignment method; and growing the high-temperature-resistant metal electrode and the interconnection line by using a physical vapor deposition and stripping method.
Further, the material of the high temperature resistant metal electrode and the interconnection line comprises titanium/platinum/gold, titanium/titanium nitride/titanium/copper containing diffusion barrier material, wherein the diffusion barrier material is platinum or titanium nitride or tantalum nitride.
Further, the upper surface of the wafer is protected, specifically, a first protection layer is applied to the upper surface of the wafer, and the first protection layer is corrosion-resistant protection glue or a corrosion-resistant clamp.
Further, the lower surface of the wafer is thinned by wet chemical etching or chemical mechanical polishing.
According to a second aspect of the embodiment of the present application, there is provided a method for manufacturing a special-shaped silicon interposer including a TSV, including:
and a through silicon via TSV manufacturing step: photoetching and deeply etching vertical blind holes on the upper surface of the wafer, growing seed layer metal in the blind holes and electroplating and filling copper columns;
and a second high temperature resistant electrode and interconnection line manufacturing step: depositing a second passivation layer on the upper surface of the wafer, and manufacturing an electrode with a re-wiring function and an interconnection line to be communicated with the corresponding copper column;
the second upper surface profile groove deep etching step: photoetching and deeply etching a second outer groove of the special-shaped silicon adapter plate on the upper surface of the wafer;
a second lower surface thinning release step: and protecting the upper surface of the wafer, thinning the lower surface of the wafer to the bottom of the second outer groove, releasing and separating the special-shaped structure, and simultaneously opening and penetrating the blind end of the vertical blind hole vertically, wherein the depth of the second outer groove is equal to that of the vertical blind hole.
Further, the through silicon via TSV fabrication step includes:
photoetching and deeply etching vertical blind holes on the upper surface of the wafer, and depositing a silicon dioxide insulating layer on the side walls of the blind holes;
growing high temperature resistant seed layer metal in the blind hole;
and electroplating and filling copper columns in the blind holes, and leveling the upper surface of the wafer by using a chemical mechanical polishing method.
Further, the second lower surface thinning release step includes:
applying a second protective layer on the upper surface of the wafer;
thinning the lower surface of the wafer, when the lower surface of the wafer is thinned to the bottom of the outline groove, releasing the special-shaped silicon adapter plate, opening the blind end of the blind hole at the same time, and forming a TSV (through silicon via) penetrating from top to bottom by the copper column;
and removing the second protective layer to obtain the separated special-shaped silicon adapter plate containing the TSV.
According to a third aspect of the embodiment of the present application, there is provided a three-dimensional heterogeneous integrated system of a special-shaped silicon interposer containing TSVs, which is formed by packaging the special-shaped silicon interposer containing TSVs, and a silicon optical device and an electronic device, which are prepared by the method according to the second aspect, on a substrate, wherein the silicon optical device is fabricated on a wafer before the second refractory electrode and interconnection line fabrication step, or the silicon optical device is attached to the special-shaped silicon interposer containing TSVs by mounting or flip-chip bonding.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
firstly, the method avoids the possible breakage of the silicon wafer during the traditional mechanical scribing or laser scribing when manufacturing the special-shaped structure, and realizes the automatic release and separation of the special-shaped structure by combining the deep etching of the upper surface and the thinning of the lower surface;
secondly, the application provides a release process of the special-shaped structure, wherein release separation of a plurality of special-shaped high-temperature pressure resistance characteristic samples or blind hole opening of the silicon through hole and release separation of the special-shaped structure are simultaneously completed in one step in the thinning process of the lower surface of the wafer;
thirdly, the application provides a high temperature resistant ohmic contact electrode structure silicon/titanium disilicide/titanium nitride/titanium/copper (Si/TiSi) 2 Ti/TiN/Ti/Cu) and high temperature resistant interconnect structure titanium/titanium nitride/titanium/copper (Ti/TiN/Ti/Cu), can be used for measuring high temperature voltage resistance characteristics above 300 ℃ and preparing the special-shaped silicon adapter plate containing TSV.
Fourth, the special-shaped silicon adapter plate containing TSV provided by the application is beneficial to aligning an incident optical fiber with an end face coupler of a silicon optical device, and realizes an electric-optical-sensing three-dimensional heterogeneous integrated system.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a flow chart showing a method for preparing a high temperature pressure resistance characteristic sample, wherein (a) in FIG. 1- (h) in FIG. 1 are structural sectional views of each flow;
FIG. 2 is a flow chart of a method for preparing a high temperature pressure resistance characteristic sample, wherein (a) in FIG. 2- (h) in FIG. 2 are structural plan views of each flow;
FIG. 3 is a schematic diagram of a tensile test of high temperature pressure resistance characteristics of single crystal silicon based on dumbbell-shaped high temperature pressure resistance characteristics;
fig. 4 is a flow chart of a process for preparing and three-dimensionally integrating a shaped silicon interposer containing a silicon optical device and TSVs, wherein (a) in fig. 4- (g) are structural cross-sectional views of each flow in the preparation process, and (h) in fig. 4 is a cross-sectional view of an electric-optical-sensing three-dimensional heterogeneous integrated system of the shaped silicon interposer;
fig. 5 is a flow chart of a process for preparing and three-dimensionally integrating a special-shaped silicon interposer containing a silicon optical device and TSVs, wherein (a) in fig. 5- (g) are structural cross-sectional views of each flow in the preparation process, and (h) in fig. 5 is a cross-sectional view of an electric-optical-sensing three-dimensional heterogeneous integrated system of the special-shaped silicon interposer;
fig. 6 is a flow chart of preparation and three-dimensional integration of a shaped silicon interposer based on TSV, wherein (a) in fig. 6- (g) in fig. 6 are structural cross-sectional views of each flow in the preparation process, and (h) in fig. 6 is a cross-sectional view of an electro-optic-sensing three-dimensional heterogeneous integrated system of the shaped silicon interposer;
fig. 7 is a schematic three-dimensional structure of the three-dimensional heterogeneous integrated system of electro-optic-sense of (h) in fig. 6.
Reference numerals: the device layer 1, the shape 2 of the force sensitive resistor, the force sensitive resistor 3, the first passivation layer 4, the silicon 5, the first lead interconnection 6, the hole 7, the first outer groove 8, the first protection layer 9, the high-temperature voltage resistance characteristic sample 10, the high-low temperature box 11, the universal meter 12, the high-temperature resistant wire 13, the silicon wafer on insulator 14, the blind hole 15, the copper column 16, the silicon optical device 17, the second passivation layer 18, the second lead interconnection 19, the second outer groove 20, the second protection layer 21, the special-shaped silicon adapter plate 22, the electronic device 23, the substrate 24, the incident optical fiber 25 and the monocrystalline silicon wafer 26.
Description of the embodiments
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
In order that the above-recited objects, features and advantages of the present application will be readily understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Taking dumbbell-shaped samples for measuring the high-temperature pressure resistance coefficient of monocrystalline silicon as an example for description, the application range of the applicable materials of the application is not limited to the monocrystalline silicon wafer and silicon-on-insulator (SOI) wafer, and the applicable materials are also applicable to other materials such as silicon carbide, sapphire, ceramics, quartz glass and the like; the application range of the applicable shape of the application is not limited to dumbbell shape, and is also applicable to other arbitrary shapes.
The present application provides a method for preparing a sample with high temperature pressure resistance characteristics, as shown in fig. 1 and 2, wherein in one embodiment, the dumbbell-shaped sample is manufactured by using a Silicon On Insulator (SOI) wafer as a material (fig. 1 (a) and fig. 2 (a)).
(1) The device manufacturing steps are as follows: photoetching and etching the shape 2 of the force sensitive resistor on the device layer 1 on the upper surface of the SOI wafer ((b) in fig. 1 and (b) in fig. 2), and performing ion implantation and annealing based on the shape of the force sensitive resistor to form a force sensitive resistor 3 with a specific doping type and doping concentration ((c) in fig. 1 and (c) in fig. 3);
(2) A first high temperature resistant electrode and interconnection line manufacturing step: depositing a first passivation layer 4 on the upper surface and the lower surface of the wafer, photoetching and etching the first passivation layer 4 on the ohmic contact area of the force sensitive resistor, and exposing silicon 5 of the device layer so as to grow a high-temperature-resistant ohmic contact electrode and an interconnection line; the method specifically comprises the following steps:
(2.1) depositing a first passivation layer 4 on the upper and lower surfaces of the wafer, preferably by depositing a silicon dioxide/silicon nitride layer by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the first passivation layer 4 is isolated from the buried oxide layer silicon dioxide of the SOI wafer to encapsulate the force sensitive resistor 3, eliminating leakage current at high temperatures above 120 ℃ (fig. 1 (d), fig. 2 (d)).
(2.2) first, photolithography and etching of the silicon 5 of the first passivation layer 4 exposing the ohmic contact region of the force sensitive resistor 3, heavily doping and annealing; then, titanium disilicide (TiSi) is grown on the silicon 5 in the ohmic contact region, preferably by self-aligned method 2 ) A metal-semiconductor contact with good refractory metal silicide formation; finally, physical Vapor Deposition (PVD) and lift-off methods are preferred to grow high temperature resistant metal electrodes and interconnects (i.e., first lead interconnects 6). The materials of the high temperature resistant metal electrode and the interconnection line include, but are not limited to, titanium/platinum/gold (Ti/Pt/Au), titanium/titanium nitride/platinum/gold (Ti/TiN/Pt/Au), titanium/titanium nitride/titanium/copper (Ti/TiN/Ti/Cu), etc. containing diffusion barrier materials such as platinum (Pt) or titanium nitride (TiN) or tantalum nitride (TaN). In which silicon/titanium disilicide/titanium/platinum/gold (Si/TiSi) 2 The Ti/Pt/Au electrode is suitable for high-temperature application environment below 300 ℃, and silicon/titanium disilicide/titanium nitride/platinum/gold (Si/TiSi) 2 Ti/TiN/Pt/Au), si/TiSiSiTiSiTiSiTiSiTiSiTiSiTiSiTiSiTiSiTiSiTiSiTiSiTiSiSiSiTiSiSiAu (Si/Au 2 Ti/TiN/Ti/Cu) suitable for use in high temperature application environment (FIG. 1 (e) fig. 2 (e)).
(3) Deep etching of the first outer groove 8 on the first upper surface: photoetching and deeply etching a first external groove 8 and a hole 7 on the upper surface of the wafer, wherein the depth of the first external groove 8 and the hole 7 is the required sample depth;
specifically, the silicon on the upper surface of the SOI wafer is etched by photolithography and deep etching, so that the hole 7 and the first outer groove 8 in the dumbbell-shaped specimen are formed ((f) in fig. 1, and (f) in fig. 2), and the depths of the hole 7 and the first outer groove 8 should be the thickness of the final desired specimen.
(4) A first lower surface thinning release step: protecting the upper surface of the wafer, thinning the lower surface of the wafer until the high-temperature pressure resistance characteristic sample is released, and removing the protection of the upper surface to obtain a required high-temperature pressure resistance characteristic sample;
(4.1) a first protective layer 9 is applied to the upper surface of the silicon-on-insulator wafer (fig. 1 (g), fig. 2 (g)). The first protective layer 9 may be a corrosion-resistant protective adhesive or a corrosion-resistant clamp.
(4.2) thinning the lower surface of the wafer, when the lower surface of the wafer is thinned to the bottom of the first outer groove 8, the plurality of dumbbell-shaped high temperature pressure resistance characteristic samples 10 originally connected by the bottom silicon are released by losing the bottom silicon ((h) in fig. 1, h) in fig. 2), and finally the first protective layer 9 is removed, thereby obtaining a separated irregular structure. The method for thinning the lower surface of the wafer can be wet chemical etching, and etching liquid is preferably but not limited to potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH) solution and the like; the method of thinning the lower surface of the wafer may also be Chemical Mechanical Polishing (CMP) or the like.
Fig. 3 is a schematic diagram of a single crystal silicon high temperature pressure resistance characteristic tensile test based on a dumbbell-shaped high temperature pressure resistance characteristic sample, wherein the dumbbell-shaped high temperature pressure resistance characteristic sample 10 is suspended in a high and low temperature box 11 through a hole 7 at one end, and a tensile force F is applied at the other end, as shown in fig. 3. One end of the high-temperature resistant wire 13 is connected with the high-temperature resistant first lead interconnection 6 on the sample, and the other end is led out to the room temperature environment to be connected with the high-precision multimeter 12. When the piezoresistance characteristics at a specific temperature are measured by the test, firstly, the temperature in the high-low temperature box 11 is raised to a set temperature and kept constant; then, the initial resistance value R under the temperature condition is measured 0 The method comprises the steps of carrying out a first treatment on the surface of the Then, a tensile force F is applied, the stress sigma of the force sensitive resistor 3 is calculated and the resistance value R after being stressed is measured 1 The method comprises the steps of carrying out a first treatment on the surface of the And finally, calculating according to a formula (1) to obtain the piezoresistive coefficient pi of the monocrystalline silicon under the corresponding doping condition and temperature condition.
（1）
For initial resistivity, +.>，/>Is the resistivity of the force sensitive resistor 3 after being subjected to a tensile force F.
Fig. 4 is a flow chart of the preparation and three-dimensional integration of a shaped silicon interposer 22 containing silicon photonics devices 17 and TSVs in one embodiment. The method of the present application will be described by taking a shaped silicon interposer for an electro-optical-sensing three-dimensional heterogeneous integrated system as an example, but the method of the present application is not limited to an SOI wafer, and is also applicable to single crystal silicon, silicon carbide, sapphire, ceramic, quartz glass, etc. The special-shaped silicon interposer is dumbbell-shaped and comprises a silicon optical device 17 and a TSV structure, but the structure applicable to the application is not limited to the shape, and is also applicable to other arbitrary shapes.
And a through silicon via TSV manufacturing step: photoetching and deeply etching vertical blind holes on the upper surface of the silicon-on-insulator wafer 14, growing seed layer metal in the blind holes and electroplating to fill copper columns; the method specifically comprises the following steps:
vertical blind holes 15 are etched and etched back on the silicon-on-insulator wafer 14 (fig. 4 (a), fig. 4 (b)).
Firstly, depositing a silicon dioxide insulating layer on the side wall of the blind hole 15; then, a seed layer, preferably a sputtered titanium/titanium nitride/titanium/copper (Ti/TiN/Ti/Cu) seed layer, is grown on the sidewalls of the blind via 15; thereafter, the filled copper pillars 16 are electroplated in the blind holes 15 and the upper surface is planarized using a chemical mechanical polishing technique (Chemical Mechanical Polishing, CMP) (fig. 4 (c)).
The device manufacturing steps are as follows: fabricating a silicon optical device 17 on a silicon-on-insulator wafer 14;
and a second high temperature resistant electrode and interconnection line manufacturing step: depositing a second passivation layer 18 on the upper surface of the silicon-on-insulator wafer 14, and fabricating an electrode and an interconnection line (i.e., a second lead interconnection 19) having a re-wiring (RDL) function to communicate with the corresponding copper pillar 16 (fig. 4 (d)); as can be seen from fig. 4 (d), in this embodiment, a silicon-on-insulator optical device 17 is fabricated on the silicon-on-insulator wafer 14 prior to this step.
The second upper surface profile groove deep etching step: a second outer groove 20 of the profiled silicon interposer is etched on the upper surface of the silicon-on-insulator wafer 14 by photolithography and deep etching, the depth of the second outer groove 20 is preferably equal to the depth of the vertical blind hole 15 (fig. 4 (e));
a second lower surface thinning release step: the upper surface of the silicon wafer 14 on the insulator is protected, the lower surface of the silicon wafer 14 on the insulator is thinned to the bottom of the outline groove, the special-shaped structure is released and separated, and meanwhile, the blind end of the vertical blind hole is opened and penetrates up and down; the method specifically comprises the following steps:
a second protective layer 21 is applied to the upper surface of the silicon-on-insulator wafer 14 (fig. 4 (f)).
When the lower surface of the soi wafer 14 is thinned to the bottom of the second outer groove 20, the profiled silicon interposer 22 is released, the blind end of the blind via 15 is opened at the same time, the copper pillar 16 forms a TSV penetrating up and down, and finally the second protective layer 21 is removed, thereby obtaining the separated profiled silicon interposer 22 including the silicon optical device 17 and the TSV (fig. 4 (g)). After the fabrication, the profiled silicon interposer 22 and the electronic device 23 (including the sensor device) are packaged on the substrate 24 to form a complete three-dimensional heterogeneous integrated system of electro-optic-sensing ((h) in fig. 4).
Fig. 5 is a flowchart of another embodiment of the preparation and three-dimensional integration of a shaped silicon interposer 22 including a silicon optical device 17 and TSVs, wherein when the silicon optical device 17 has a high temperature process step in the preparation, the blind holes 15 and the copper pillars 16 of the TSVs manufactured first in the embodiment shown in fig. 4 are susceptible to the subsequent high temperature process for preparing the silicon optical device, so that the silicon optical device 17 (fig. 5 (a) - (b)) can be manufactured first on the SOI wafer, the blind holes 15 and the copper pillars 16 of the TSVs are manufactured after the manufacturing is completed (fig. 5 (c) - (d)), and finally the second upper surface profile trench deep etching step (fig. 5 (e)), the second lower surface thinning release step (fig. 5 (f) - (g)), and finally the three-dimensional integration is performed, thereby forming a complete three-dimensional heterogeneous integrated system of electro-optic-sense (fig. 5 (h)).
Fig. 6 is a flow chart of a method of fabricating a shaped silicon interposer 22 including TSVs. The silicon optical device 17 and the electronic device 23 (including the sensor device) may be separately fabricated and then integrated on the TSV-containing profiled silicon interposer 22. The material of the shaped silicon interposer 22 may be an SOI wafer or a monocrystalline silicon wafer 26. The method of the present application will be described below by taking a monocrystalline silicon wafer as an example. First, a TSV structure is fabricated on a single crystal silicon wafer 26 (fig. 6 (a) - (d)); then, a second upper surface profile groove deep etching step ((e) in fig. 6) and a second lower surface thinning release step ((f) - (g) in fig. 6) are performed; finally, the silicon optical device 17 and the electronic device 23 are integrated on the shaped silicon interposer 22 containing TSVs ((h) in fig. 6).
Fig. 7 is a schematic three-dimensional structure diagram of the three-dimensional heterogeneous integrated system of electro-optic-sensing in fig. 6 (h), and as shown in fig. 7, the silicon optical device 17 and the electronic device 23 are integrated on the special-shaped silicon interposer 22 containing TSVs and then packaged on the substrate 24. The incident optical fiber 25 is aligned with the end-face coupler of the silicon optical device 17 from the narrow place of the dumbbell shaped silicon interposer 22.
The portions of the method for preparing the special-shaped silicon interposer containing the TSV, which are not described in detail, are identical to those of the method for preparing the high-temperature voltage resistance characteristic sample, and are not described here again.
The high-temperature pressure resistance characteristic sample and the preparation method of the special-shaped silicon adapter plate containing TSV provided by the application are described in detail, and specific examples are applied to illustrate the principle and the implementation mode of the application, and the description of the examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The preparation method of the high-temperature pressure resistance characteristic sample is characterized by comprising the following steps of:
the device manufacturing steps are as follows: photoetching and etching the shape of the force-sensitive resistor on a device layer on the upper surface of the wafer, and carrying out ion implantation and annealing based on the shape of the force-sensitive resistor to form the force-sensitive resistor;
a first high temperature resistant electrode and interconnection line manufacturing step: depositing a first passivation layer on the upper surface and the lower surface of the wafer, photoetching and etching the first passivation layer on the ohmic contact area of the force-sensitive resistor to expose silicon of the device layer, so as to grow a high-temperature-resistant ohmic contact electrode and an interconnection line;
a first upper surface profile groove deep etching step: photoetching and deeply etching first external grooves and holes on the upper surface of a wafer, wherein the depth of the first external grooves and holes is the required sample depth, and the holes are used for hanging and fixing the sample and applying external acting force during piezoresistance coefficient measurement;
a first lower surface thinning release step: and protecting the upper surface of the wafer, thinning the lower surface of the wafer until the high-temperature pressure resistance characteristic sample is released, and removing the protection of the upper surface to obtain the required high-temperature pressure resistance characteristic sample.
2. The method of claim 1, wherein the first passivation layer is deposited by depositing a silicon dioxide/silicon nitride layer using a plasma enhanced chemical vapor deposition process.
3. The method of claim 1, wherein in the first refractory electrode and interconnect line fabrication step, silicon of the first passivation layer exposing the ohmic contact region of the force sensitive resistor is lithographically etched, heavily doped and annealed; growing refractory metal silicide on the silicon of the ohmic contact region by a self-alignment method; and growing the high-temperature-resistant metal electrode and the interconnection line by using a physical vapor deposition and stripping method.
4. The method of claim 1, wherein the material of the refractory metal electrode and interconnect comprises titanium/platinum/gold, titanium/titanium nitride/titanium/copper, including a diffusion barrier material, wherein the diffusion barrier material is platinum or titanium nitride or tantalum nitride.
5. The method according to claim 1, characterized in that the upper surface of the wafer is protected, in particular a first protective layer is applied on the upper surface of the wafer, which first protective layer is a corrosion-resistant protective glue or a corrosion-resistant clamp.
6. The method of claim 1, wherein the lower surface of the wafer is thinned by wet chemical etching or chemical mechanical polishing.
7. The preparation method of the special-shaped silicon adapter plate containing the TSV is characterized by comprising the following steps of:
and a through silicon via TSV manufacturing step: photoetching and deeply etching vertical blind holes on the upper surface of the wafer, growing seed layer metal in the blind holes and electroplating and filling copper columns;
and a second high temperature resistant electrode and interconnection line manufacturing step: depositing a second passivation layer on the upper surface of the wafer, and manufacturing an electrode with a re-wiring function and an interconnection line to be communicated with the corresponding copper column;
the second upper surface profile groove deep etching step: photoetching and deeply etching a second outer groove of the special-shaped silicon adapter plate on the upper surface of the wafer;
a second lower surface thinning release step: and protecting the upper surface of the wafer, thinning the lower surface of the wafer to the bottom of the second outer groove, releasing and separating the special-shaped structure, and simultaneously opening and penetrating the blind end of the vertical blind hole vertically, wherein the depth of the second outer groove is equal to that of the vertical blind hole.
8. The method of claim 7, wherein the through silicon via TSV fabrication step comprises:
photoetching and deeply etching vertical blind holes on the upper surface of the wafer, and depositing a silicon dioxide insulating layer on the side walls of the blind holes;
growing high temperature resistant seed layer metal in the blind hole;
and electroplating and filling copper columns in the blind holes, and leveling the upper surface of the wafer by using a chemical mechanical polishing method.
9. The method of claim 7, wherein the second lower surface thinning release step comprises:
applying a second protective layer on the upper surface of the wafer;
thinning the lower surface of the wafer, when the lower surface of the wafer is thinned to the bottom of the outline groove, releasing the special-shaped silicon adapter plate, opening the blind end of the blind hole at the same time, and forming a TSV (through silicon via) penetrating from top to bottom by the copper column;
and removing the second protective layer to obtain the separated special-shaped silicon adapter plate containing the TSV.
10. A three-dimensional heterogeneous integrated system of a special-shaped silicon adapter plate containing TSVs, which is characterized in that the system is formed by packaging the special-shaped silicon adapter plate containing the TSVs, a silicon optical device and an electronic device which are prepared by the method of any one of claims 7-9 on a substrate, wherein the silicon optical device is manufactured on a wafer before the second high-temperature resistant electrode and interconnection line manufacturing step, or the silicon optical device is attached to the special-shaped silicon adapter plate containing the TSVs through mounting or flip-chip welding.
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| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
| CN108010853A (en) * | 2017-12-15 | 2018-05-08 | 西安科锐盛创新科技有限公司 | Pinboard based on silicon hole and preparation method thereof |
| CN113241300A (en) * | 2021-04-30 | 2021-08-10 | 武汉新芯集成电路制造有限公司 | Semiconductor and manufacturing method thereof |
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| US8691691B2 (en) * | 2011-07-29 | 2014-04-08 | International Business Machines Corporation | TSV pillar as an interconnecting structure |
| US9040349B2 (en) * | 2012-11-15 | 2015-05-26 | Amkor Technology, Inc. | Method and system for a semiconductor device package with a die to interposer wafer first bond |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
| CN108010853A (en) * | 2017-12-15 | 2018-05-08 | 西安科锐盛创新科技有限公司 | Pinboard based on silicon hole and preparation method thereof |
| CN113241300A (en) * | 2021-04-30 | 2021-08-10 | 武汉新芯集成电路制造有限公司 | Semiconductor and manufacturing method thereof |
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