CN116610597B - Storage device and garbage recycling control method thereof - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004064 recycling Methods 0.000 title claims abstract description 23
- 238000012545 processing Methods 0.000 claims description 39
- 230000008569 process Effects 0.000 claims description 30
- 230000004913 activation Effects 0.000 claims description 4
- 230000005055 memory storage Effects 0.000 claims 6
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 239000007787 solid Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
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- 238000012795 verification Methods 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7205—Cleaning, compaction, garbage collection, erase control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to the field of memory devices, in particular to a memory device and a garbage recycling control method thereof. A memory device, comprising: the flash memory comprises a plurality of physical blocks for storing storage data; the controller is electrically connected to the flash memory and is used for receiving the storage data of the host; on a flash memory, a controller selects a fixed number of logic units in each chip to be in an available state, and sets starting time of garbage collection treatment, wherein the starting time meets the following conditions: start time = initial time (fixed number/total number)/write speed factor. The invention saves data transmission time and firmware resources on the basis of ensuring the stable reserved space and service life after the garbage collection is started.
Description
Technical Field
The invention relates to the field of memory devices, in particular to a memory device and a garbage recycling control method thereof.
Background
In the using process of the flash memory, effective data and invalid data exist on some blocks at the same time, and the storage space of the flash memory is gradually used up. The garbage collection module is used for collecting the effective data, so that only invalid data are stored in some blocks. The block storing invalid data can be subjected to erasing data processing, and new data can be continuously written into the block after the erasing data processing. When verifying the problem related to garbage collection of the flash memory, if the reserved space is changed, the operation logic of garbage collection treatment is changed, and the speed and the writing operation of the flash memory are also affected. There is therefore a need for improvement.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a memory device and a method for controlling garbage collection thereof, which are used for solving the problem that the operation logic of garbage collection processing of the existing memory device is changed.
To achieve the above and other related objects, the present invention provides a memory device comprising:
the flash memory comprises a plurality of physical blocks for storing storage data; and
the controller is electrically connected with the flash memory and is used for receiving the storage data of the host;
on the flash memory, the controller selects a fixed number of logic units in each chip to be in an available state, and sets starting time of garbage collection processing, wherein the starting time meets the following conditions:
start time = initial time (fixed number/total number)/write speed factor;
the total quantity represents the quantity of all logic units on each chip, the initial time represents the time for garbage collection processing of the flash memory when the total quantity of logic units on each chip are in an available state, and the writing speed factor represents the speed of writing data into the flash memory by the controller.
In one embodiment of the present invention, the plurality of physical blocks includes an idle block and a usage block, and the controller adjusts a speed value of one garbage collection process every time an activation number is consumed is set by the controller, the activation number satisfying:
start number = initial number;
and when all the logic units on each chip are in an available state, the number of idle blocks consumed by the speed value of garbage collection processing is adjusted and recorded as the initial number.
In one embodiment of the present invention, the controller sets a speed of garbage collection processing of the flash memory, the speed of garbage collection processing satisfying:
garbage collection speed gear= (number of user blocks-number of user blocks×garbage collection ratio threshold)/initial number;
and when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is represented as the garbage collection proportion threshold value, and the number of the user blocks represents the number of all physical blocks operable by a user in the flash memory.
In one embodiment of the invention, the controller controls the start-up time of the waste reclamation process, the start-up time satisfying:
start time = full capacity × garbage collection ratio threshold × (fixed number/full number)/(write speed factor × write speed);
the full capacity characterizes a storage capacity of the flash memory when the full number of logic cells on each chip are in an available state, and the write speed characterizes a speed at which the controller writes the stored data to the flash memory.
In one embodiment of the present invention, the controller controls a reserved space on the flash memory, the reserved space satisfying:
reserved space= (total capacity-user capacity)/user capacity;
and on the flash memory, the user capacity represents the capacity corresponding to the physical block operable by the user, and the reserved space represents the ratio between the capacity corresponding to the physical block inoperable by the user and the user capacity.
The invention also provides a control method for garbage collection of the storage device, which comprises the following steps:
storing storage data through a plurality of physical blocks on the flash memory;
the flash memory is electrically connected with the controller;
receiving, by the controller, the stored data written by the host; and
selecting a fixed number of logic units in each chip to be in an available state through the controller on the flash memory, and setting starting time of garbage recycling treatment;
the start time satisfies: start time = initial time (fixed number/total number)/write speed factor;
the total quantity represents the quantity of all logic units on each chip, the initial time represents the time for garbage collection processing of the flash memory when the total quantity of logic units on each chip are in an available state, and the writing speed factor represents the speed of writing data into the flash memory by the controller.
In one embodiment of the present invention, after the step of selecting a fixed number of logic units in each chip to be in an available state, the method includes:
acquiring the number of idle blocks and the number of used blocks in the flash memory through the controller;
the controller is used for setting the speed value of garbage recycling treatment once when the idle blocks of the starting quantity are consumed;
the number of starts satisfies: start number = initial number;
and when all logic units on each chip are in an available state on the flash memory, the number of idle blocks consumed by adjusting the speed value of garbage collection processing is recorded as the initial number.
In one embodiment of the present invention, after the step of adjusting the speed value of the garbage collection process once when the controller sets the idle blocks of each consumption start number, the method includes:
setting a speed gear of garbage collection treatment of the flash memory through the controller;
the speed gear of the garbage recycling treatment meets the following conditions: garbage collection speed gear= (number of user blocks-number of user blocks×garbage collection ratio threshold)/initial number;
and when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is represented as the garbage collection proportion threshold value, and the number of the user blocks represents the number of all physical blocks operable by a user in the flash memory.
In one embodiment of the present invention, after the step of setting, by the controller, a speed gear of garbage collection processing of the flash memory, the method includes:
controlling the starting time of garbage recycling treatment through the controller;
the start time satisfies: start time = full capacity × garbage collection ratio threshold × (fixed number/full number)/(write speed factor × write speed);
wherein the full capacity characterizes a storage capacity of the flash memory when the full number of logic cells on each chip are in an available state, and the write speed characterizes a speed at which the controller writes the stored data to the flash memory.
In one embodiment of the present invention, after the step of selecting, by the controller, that a fixed number of logic units in each chip are in an available state and setting a start time of garbage collection processing on the flash memory, the method includes:
controlling a reserved space on the flash memory through the controller;
the reserved space satisfies the following conditions: reserved space= (total capacity-user capacity)/user capacity;
and the reserved space represents the ratio between the capacity corresponding to the physical block which is not operable by the user and the user capacity.
As described above, the memory device and the garbage collection control method thereof of the present invention have the following beneficial effects: the invention saves data transmission time and firmware resources on the basis of ensuring stable reserved space and usability after the garbage collection is started.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram showing a structure of a memory device according to the present invention.
Fig. 2 is a schematic diagram showing a logic unit structure in a memory device according to the present invention.
Fig. 3 is a schematic diagram of a super block in a memory device according to the present invention.
Fig. 4 is a schematic diagram showing steps of a method for controlling garbage collection of a memory device according to the present invention.
Fig. 5 is a schematic diagram illustrating a step of step S50 in fig. 4 according to the present invention.
Fig. 6 shows a further step of step S50 of fig. 4 according to the present invention.
Description of element reference numerals
100. A host; 200. a memory device; 300. a controller; 400. a flash memory;
310. a bus interface; 320. a processing unit; 330. an instruction buffer unit; 340. a static random access memory unit; 350. a flash memory interface; 360. a buffer storage unit; 370. a dynamic random access memory unit;
410. a chip; 420. a logic unit; 430. a noodle; 440. a physical block; 450. a page; 460. a page register; 470. a cache register; 480. super blocks.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. It is also to be understood that the terminology used in the examples of the invention is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the invention. The test methods in the following examples, in which specific conditions are not noted, are generally conducted under conventional conditions or under conditions recommended by the respective manufacturers.
It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the invention to the extent that it can be practiced, since modifications, changes in the proportions, or otherwise, used in the practice of the invention, are not intended to be critical to the essential characteristics of the invention, but are intended to fall within the spirit and scope of the invention. Also, the terms such as "upper," "lower," "left," "right," "middle," and "a" and the like recited in the present specification are merely for descriptive purposes and are not intended to limit the scope of the invention, but are intended to provide relative positional changes or modifications without materially altering the technical context in which the invention may be practiced.
Referring to fig. 1 to 5, in some embodiments, the present invention provides a storage device 200 and a method for controlling garbage collection thereof, which can be applied to the SSD (Solid State Disk or Solid State Drive) field. For example, the method can be applied to NAND flash (flash memory) of a solid state disk to control garbage collection of a plurality of blocks (blocks) 440 in the flash memory 400. The invention can make the garbage collection of the flash memory 400 earlier. The invention completely restores the firmware logic behavior of the storage device products such as the original solid state disk and the like on the premise of not influencing the service life after the garbage collection and the firmware logic, thereby saving a large amount of data transmission time and firmware resources. The following is a detailed description of specific embodiments.
Referring to fig. 1 and 2, in some embodiments of the present invention, a memory device 200 is provided, which may include a controller 300 and a flash memory 400. The controller 300 is electrically connected to the host 100, and the controller 300 is configured to receive the storage data written by the host 100. The controller 300 is electrically connected to the flash memory 400, and the controller 300 is used for transmitting the stored data to the flash memory 400. The flash memory 400 may include a plurality of physical blocks 440 thereon, and the plurality of physical blocks 440 may be used to store data. One physical block 440 may include a plurality of pages (pages) 450 thereon. The physical block 440 needs to perform an erase data (erase) process before writing data (program), the write data operation is performed in the minimum unit of the page 450, and the erase data operation is performed in the minimum unit of the physical block 440. When valid data exists in the physical block 440, the physical block 440 cannot be subjected to data erasure processing, i.e., the physical address where invalid data is located cannot be used to write new storage data. The plurality of physical blocks 440 may include a usage block (data block) and an idle block (free block). When the total number of the used blocks occupies the plurality of physical blocks 440 reaches the garbage collection processing condition, the garbage collection processing operation of the flash memory 400 is triggered. In the garbage collection operation of the flash memory 400, the ratio of the number of blocks to the number of user blocks is used to reach an upper limit value, which is characterized as a garbage collection ratio threshold. The number of user blocks characterizes the number of physical blocks 440 in the flash memory 400 that are operable by all users.
Referring to fig. 1 and 2, in some embodiments of the present invention, the controller 300 may select a fixed number of logic units 420 in each chip 410 to be in an available state and the remaining number of logic units 420 on each chip 410 to be in an unavailable state in the flash memory 400. The controller 300 may set a start time of the garbage collection process, where the start time satisfies: start time = initial time (fixed number/total number)/write speed factor. Wherein the total number represents the number of all logic units 420 on each chip 410, and the initial time represents the time for garbage collection processing of the flash memory 400 when the total number of logic units 420 on each chip 410 is in an available state. The write speed factor characterizes how fast the controller 300 writes data to the flash memory 400. When the entire number of logic cells 420 in each chip 410 is in an available state, the controller 300 writes data to the flash memory 400 faster, with a larger write speed factor. When a fixed number of logic cells 420 in each chip 410 are in an available state, the controller 300 writes data to the flash memory 400 slower, with a smaller write speed factor. That is, after the setting by the controller 300, the ratio of the start time to the initial time of the garbage collection process of the flash memory 400 is (fixed number/total number)/the writing speed factor, so that the garbage collection process is performed in advance. The method can save a large amount of data transmission time and firmware resources in terms of speed verification, service life verification and the like of the flash memory 400 after garbage collection is started.
Referring to fig. 1 and 2, in some embodiments of the present invention, the plurality of physical blocks 440 may include a free block (free block) and a used block (data block). The idle block represents a physical block 440 with zero valid data, and the physical block 440 can be subjected to data erasure processing. The block is used to represent the physical block 440 with non-zero valid data, i.e. the stored data is written on the physical block 440. The controller 300 can set the speed value of garbage collection and disposal once every time the starting number of idle blocks is consumed. The starting quantity is as follows: number of starts = initial number. In the flash memory 400, when the total number of logic units 420 on each chip 410 is in an available state, the number of idle blocks consumed by the garbage collection process is adjusted according to the speed value, and the number is recorded as an initial number.
Referring to fig. 1 and 2, in some embodiments of the present invention, the controller 300 may further set a speed of garbage collection in the flash memory 400, where the speed of garbage collection is defined as: regarding the number of times the speed value of the flash memory 400 regarding garbage collection processing is adjusted. The speed gear of garbage recycling treatment meets the following conditions: garbage collection speed gear= (number of user blocks-number of user blocks×garbage collection ratio threshold)/initial number. And when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is characterized as a garbage collection proportion threshold value. The number of user blocks characterizes the number of physical blocks 440 in the flash memory 400 that are operable by all users. In the case where a fixed number of logic units 420 are available in each chip 410 and the entire number of logic units 420 are available on each chip 410, the corresponding garbage collection process speed is the same in both cases. The invention does not influence the service life and firmware logic after the garbage collection and starting, completely restores the firmware logic behavior of storage device products such as the original solid state disk, and the like, thereby saving a large amount of data transmission time and firmware resources.
Referring to fig. 1 and 2, in some embodiments of the present invention, the writing speed is used to indicate the speed at which the controller 300 writes the stored data to the flash memory 400. The controller 300 may control the start time of the garbage collection process, where the start time satisfies: start time = full capacity × garbage collection ratio threshold × (fixed quantity/full quantity)/(write speed factor × write speed). Wherein the total capacity characterizes the storage capacity of the flash memory 400 when the total number of logic units 420 on each chip 410 is in an available state. The controller 300 can set the usage capacity of the flash memory 400, which satisfies the following conditions: use capacity = full capacity fixed quantity/full quantity. The usage capacity of the flash memory 400 should also be determined on the premise that a fixed number of logic units 420 are available in each chip 410 and the remaining number of logic units 420 are not available in each chip 410. The invention can lead the garbage collection of the flash memory 400 to be carried out in advance, and reduces the research and development consumption and the test consumption of the flash memory 400. The invention also reduces the hardware burden and prolongs the service life of the memory device.
Referring to fig. 1 and 2, in some embodiments of the present invention, the controller 300 may set a reserved space of the flash memory 400, where the reserved space satisfies: reserved space= (total capacity-user capacity)/user capacity = reserved capacity/user capacity. On the flash memory 400, the user capacity represents the capacity corresponding to the physical block 440 operable by the user, and the reserved space represents the ratio between the capacity corresponding to the physical block 440 inoperable by the user and the user capacity. In the case where a fixed number of logic units 420 are available in each chip 410 and the entire number of logic units 420 are available on each chip 410, the corresponding reserved space is the same in both cases. The invention does not influence the service life and firmware logic after the garbage collection and starting, completely restores the firmware logic behavior of storage device products such as the original solid state disk, and the like, thereby saving a large amount of data transmission time and firmware resources.
Referring to fig. 1 and 2, in some embodiments of the present invention, the controller 300 may include a bus interface 310, a processing unit 320, an instruction buffer unit 330, a static random access memory unit 340, a flash memory interface 350, a buffer memory unit 350, and a dynamic random access memory unit 360. The bus interface 310 is electrically connected between the host 100 and the controller 300. The processing unit 320 is an operation and control core of the controller 300, and is a final execution unit for information processing and program running. The static random access memory unit 340, the buffer memory unit 360, and the dynamic random access memory unit 370 are memory units for data in the controller 300. The flash memory interface 350 enables electrical connection between the controller 300 and the flash memory 400.
Referring to fig. 1 and 2, in some embodiments of the invention, the flash memory 400 may be a packaged NAND flash memory (package). One flash memory 400 may include a plurality of chips (targets) 410, and one chip 410 may include a plurality of logic units (luns or die) 420. One or more logic units 420 in one chip 410 share a set of data signals. Each chip 410 is controlled by a ce (chip enable) pin, i.e., a plurality of logic units 420 on one chip 410 share a chip select signal. The logic unit 420 is the smallest unit that performs read and write commands, and different logic units 420 may perform different command sequences. One logic unit 420 may include multiple planes (planes) 430, each plane 430 having independent page registers (page registers) 460 and cache registers (cache registers) 470 to optimize the access speed of the flash memory 400. The page register 460 is used to transfer data with the array of flash memory 400. Cache register 470 is used to transfer data with host 100. One plane 430 may include a plurality of physical blocks (blocks) 440, and the physical blocks 440 are the minimum units of erase data. One physical block 440 may include a plurality of pages (pages) 450, and the pages 450 are the minimum units of write data.
Referring to fig. 3, in some embodiments of the present invention, the physical blocks 440 with the same serial numbers corresponding to different logical units 420 are defined as super blocks (super blocks) 480, i.e., in fig. 3, the physical blocks 440 with different logical units 420 corresponding to the same row are positioned as super blocks 480, and each square is defined as a physical block (physical block) 440. When the entire number of logic cells 420 in each chip 410 is in an available state, the controller 300 writes data to the flash memory 400 faster, with a larger write speed factor. When a fixed number of logic cells 420 in each chip 410 are in an available state, the controller 300 writes data to the flash memory 400 slower, with a smaller write speed factor.
Referring to fig. 4, in some embodiments of the present invention, a method for controlling garbage collection of a storage device is further provided, which may include the following steps.
Step S10, storing the storage data through a plurality of physical blocks on the flash memory.
Step S20, electrically connecting to the flash memory through the controller.
Step S30, the storage data written by the host is received through the controller.
Step S40, selecting a fixed number of logic units in each chip to be in an available state on the flash memory through the controller.
Step S50, setting starting time of garbage recycling treatment on the flash memory through the controller. The starting time is as follows: start time = initial time (fixed number/total number)/write speed factor. The method comprises the steps of determining the number of all logic units on each chip, determining the time for garbage collection processing of a flash memory when the number of all logic units on each chip is in an available state, and determining the speed of writing data into the flash memory by a writing speed factor.
Step S10, storing the storage data through a plurality of physical blocks on the flash memory.
In some embodiments, the flash memory 400 may include a plurality of physical blocks 440 thereon, and the plurality of physical blocks 440 may be used to store data. One physical block 440 may include a plurality of pages (pages) 450 thereon. The physical block 440 needs to perform an erase data (erase) process before writing data (program), the write data operation is performed in the minimum unit of the page 450, and the erase data operation is performed in the minimum unit of the physical block 440.
Step S20, electrically connecting to the flash memory through the controller.
In some embodiments, the controller 300 may be electrically connected to the flash memory 400, and the controller 300 is used to transmit the stored data to the flash memory 400. When valid data exists in the physical block 440, the physical block 440 cannot be subjected to data erasure processing, i.e., the physical address where invalid data is located cannot be used to write new storage data. The plurality of physical blocks 440 may include a usage block (data block) and an idle block (free block). When the total number of the used blocks occupies the plurality of physical blocks 440 reaches the garbage collection processing condition, the garbage collection processing operation of the flash memory 400 is triggered. In the garbage collection operation of the flash memory 400, the ratio of the number of blocks to the number of user blocks is used to reach an upper limit value, which is characterized as a garbage collection ratio threshold. The number of user blocks characterizes the number of physical blocks 440 in the flash memory 400 that are operable by all users.
Step S30, the storage data written by the host is received through the controller.
In some embodiments, the controller 300 may be electrically connected to the host 100, and the controller 300 is configured to receive the storage data written by the host 100.
Step S40, selecting a fixed number of logic units in each chip to be in an available state on the flash memory through the controller.
In some embodiments, the controller 300 may select a fixed number of logic cells 420 in each chip 410 to be in an available state, and the remaining number of logic cells 420 in each chip 410 to be in an unavailable state. The capacity of the flash memory 400 is also determined on the premise that a fixed number of logic units 420 are available in each chip 410.
Step S50, setting starting time of garbage recycling treatment on the flash memory through the controller. The starting time is as follows: start time = initial time (fixed number/total number)/write speed factor. The method comprises the steps of determining the number of all logic units on each chip, determining the time for garbage collection processing of a flash memory when the number of all logic units on each chip is in an available state, and determining the speed of writing data into the flash memory by a writing speed factor.
In some embodiments, the controller 300 may set a start-up time for the garbage collection process, the start-up time satisfying: start time = initial time (fixed number/total number). Wherein the total number represents the number of all logic units 420 on each chip 410, and the initial time represents the time for garbage collection processing of the flash memory 400 when the total number of logic units 420 on each chip 410 is in an available state. That is, after the setting by the controller 300, the ratio of the start time to the initial time of the garbage collection process of the flash memory 400 is (fixed number/total number)/the writing speed factor, so that the garbage collection process is performed in advance. The method can save a large amount of data transmission time and firmware resources in terms of speed verification, service life verification and the like of the flash memory 400 after garbage collection is started.
Referring to fig. 5, in some embodiments of the present invention, the step S50 may include a step S510, a step S520, and a step S530. Step S510 may be expressed as obtaining, by the controller 300, the number of idle blocks and the number of used blocks in the plurality of physical blocks 440. Step S520 may be represented by adjusting the speed of garbage collection process once every time the controller 300 sets the starting number of idle blocks. The starting quantity is as follows: number of starts = initial number. When all logic units 420 in each chip 410 of the flash memory 400 are in an available state, the number of idle blocks consumed by the garbage collection process is adjusted by the speed value of the garbage collection process and is recorded as an initial number. Step S530 may be represented by setting, by the controller 300, a speed of garbage collection processing of the flash memory 400. The speed gear of garbage recycling treatment meets the following conditions: garbage collection speed gear= (number of user blocks-number of user blocks×garbage collection ratio threshold)/initial number. And when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is characterized as a garbage collection proportion threshold value. The number of user blocks characterizes the number of physical blocks 440 in the flash memory 400 that are all user operable.
Referring to fig. 6, in some embodiments of the present invention, step S50 may further include step S540 and step S550. Step S540 may be expressed as controlling, by the controller 300, a start time of the garbage collection process, the start time satisfying: start time = full capacity × garbage collection ratio threshold × (fixed quantity/full quantity)/(write speed factor × write speed). The full capacity characterizes the storage capacity of the flash memory 400 when the full number of logic cells 420 on each chip 410 are in an available state. The write speed factor characterizes how fast the controller 300 writes data to the flash memory 400. The write speed characterizes the speed at which the controller 300 writes stored data to the flash memory 400. Step S550 may be represented as setting, by the controller 300, a reserved space of the flash memory 400, where the reserved space satisfies: reserved space= (full capacity-user capacity)/user capacity. On the flash memory 400, the user capacity represents the capacity corresponding to the physical block 440 operable by the user, and the reserved space represents the ratio between the capacity corresponding to the physical block 440 inoperable by the user and the user capacity.
Referring to fig. 1, 2, 3, 4, 5 and 6, in some embodiments of the present invention, for example, the storage device 200 is an SSD (solid state disk), and the storage space is an a TB (terabyte) corresponding to B user blocks (blocks) and D reserved blocks. OP (Over Provisioning, reserved space) = (full capacity-user capacity)/user capacity = reserved capacity/user capacity = D/B. When the number of the logic units 420 on the memory device 200 is N, each logic unit 420 includes (b+d)/N physical blocks 440. The capacity of each super block 480 is a/B TB, and the capacity of each physical block 440 is a/B/N TB. When the entire number of logic units 420 on each chip 410 is in an available state, the controller 300 sets the garbage collection process to start when the usage block (data block) reaches the B/M super blocks 480, i.e., the memory device 200 starts to start garbage collection process when writing into the memory space of the a/M TB. And when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is characterized as a garbage collection proportion threshold value of 1/M. Namely triggering garbage recycling treatment when the ratio of the number of used blocks to the number of user blocks reaches a garbage recycling proportion threshold value of 1/M. The controller 300 can set the speed of garbage collection and disposal once every time X idle blocks (free blocks) are consumed, namely every time X usage blocks are increased correspondingly. Thus, there are (B-B/M)/X speed steps after the garbage collection process is started. Assuming that the writing speed of the memory device 200 is Y TB/s, the memory device 200 is writing A/M TB memory space, and the garbage collection process requires A/M/Y seconds.
Referring to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, and fig. 6, in some embodiments of the present invention, a product capacity of the storage device 200, which is an SSD (solid state disk), is set to be 1/N of an original capacity, i.e., a/N TB of a storage capacity. And 1/N of logic cells 420 are selected from each chip 410, denoted as a fixed number of logic cells 420. Only one physical block 440 in one super block 480 is used and has a capacity of a/B/N TB. In addition, since the number of logic units 420 is reduced, the writing speed becomes E/N, E being smaller than N, in which all logic units 420 are in use. The start time of garbage collection is set to be when the number of used blocks reaches B/M starts, that is, when the memory device 200 writes (B/M) × (a/B/N) =a/N/M TB of the memory space, the garbage collection starts. And the speed of garbage collection processing is adjusted when X idle blocks are consumed, namely when X using blocks are increased correspondingly, namely when X (A/B/N) TB capacity is written. Thus, the garbage recycling process still has (A/N-A/N/M)/(X (A/B/N)) = (B-B/M)/X gear stages. Assuming that the write speed of the memory device 200 is Y E/N TB/s, the start-up time for garbage collection is A/N/M/(Y E/N), scaled down to 1/E when the total number of logic cells 420 on each chip 410 is available.
Referring to fig. 1, 2, 3, 4, 5 and 6, in some embodiments of the present invention, for example, the storage device 200 is an SSD (solid state disk) with a storage space of 8TB (terabyte), corresponding to 4000 user blocks (blocks) and 80 reserved blocks. OP (Over Provisioning, reserved space) = (total capacity-user capacity)/user capacity = reserved capacity/user capacity = 1/50. When the number of the logic units 420 on the memory device 200 is 80, each logic unit 420 includes (4000+80)/80=51 physical blocks 480. The capacity of each super block 480 is 2000MB and the capacity of each physical block 440 is 2000/80=25 MB. When all logic units 420 on each chip 410 are in an available state, the controller 300 sets the garbage collection process to start when the usage block (data block) reaches 1000 blocks 440, i.e., the garbage collection process starts when the memory device 200 writes into the memory space of 2 TB. And when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is characterized as 1/4 of the garbage collection proportion threshold value. Namely triggering garbage recycling treatment when the ratio of the number of used blocks to the number of user blocks reaches 1/4 of the garbage recycling ratio threshold. The controller 300 can set the speed of garbage collection and disposal once every 100 free blocks (free blocks) are consumed, namely every 100 usage blocks are increased correspondingly. Thus, there are (4000-1000)/100=30 speed steps after the start of the waste reclamation process. Assuming that the writing speed of the memory device 200 is 200MB/s, the memory device 200 requires 10000 seconds for garbage collection processing when writing a memory space of 2 TB.
Referring to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, and fig. 6, in some embodiments of the present invention, a product capacity of the storage device 200, which is an SSD (solid state disk), is set to be 1/80 of an original capacity, that is, a storage capacity of 100 GB. And 1/80 of the logic cells 420 are selected from each chip 410, denoted as a fixed number of logic cells 420. Only one physical block 440 in one super block 480 is used and has a capacity of 25MB. In addition, since the number of logic units 420 is reduced, the writing speed becomes 40/80=1/2 in which all logic units 420 are in the use state. The start time of the garbage collection process is set to 1000 start using blocks, that is, the garbage collection process starts when the memory device 200 writes into the memory space of 20 GB. The garbage collection speed is adjusted once every 100 idle blocks are consumed, i.e. every 100 usage blocks are added, i.e. every writing amount is added by 100 x 25=2.5 GB. Therefore, the garbage recycling treatment still has 30 speed steps. Assuming a write speed of 100MB/s for the memory device 200, the start-up time for garbage collection is 250s, shrinking to 1/40 of the total number of logic cells on each chip that are available. The number of reserved blocks is 80, op=80/4000, which is the same as the OP when the total number of logic units 420 on each chip 410 is in the available state.
In summary, the invention provides a storage device and a garbage collection control method thereof, which saves data transmission time and firmware resources on the basis of guaranteeing service life and firmware logic after starting garbage collection. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A memory device, comprising:
the flash memory comprises a plurality of physical blocks for storing storage data; and
the controller is electrically connected with the flash memory and is used for receiving the storage data of the host;
on the flash memory, the controller selects a fixed number of logic units in each chip to be in an available state, and sets starting time of garbage collection processing, wherein the starting time meets the following conditions:
start time = initial time (fixed number/total number)/write speed factor;
the total quantity represents the quantity of all logic units on each chip, the initial time represents the time for garbage collection processing of the flash memory when the total quantity of logic units on each chip are in an available state, and the writing speed factor represents the speed of writing data into the flash memory by the controller;
the controller controls the starting time of garbage recycling treatment, and the starting time meets the following conditions:
start time = full capacity × garbage collection ratio threshold × (fixed number/full number)/(write speed factor × write speed);
the full capacity characterizes a storage capacity of the flash memory when the full number of logic cells on each chip are in an available state, and the write speed characterizes a speed at which the controller writes the stored data to the flash memory.
2. The memory device of claim 1, wherein the plurality of physical blocks includes an idle block and a use block, the controller adjusts a speed value of a garbage collection process per consumption of an activation number of the idle blocks, the activation number satisfying:
start number = initial number;
when all the logic units on each chip are in an available state, the number of idle blocks consumed by the speed value of garbage collection processing is adjusted and recorded as the initial number;
after the garbage collection is started, the garbage collection and the writing of the host computer need to share the total writing bandwidth of the flash memory, and the writing speed of the host computer is defined as a speed value.
3. The memory device of claim 2, wherein the controller sets a speed of garbage collection processing of the flash memory, the speed of garbage collection processing satisfying:
garbage collection speed gear= (number of user blocks-number of user blocks×garbage collection ratio threshold)/initial number;
when the ratio of the number of the used blocks to the number of the user blocks reaches an upper limit value, the upper limit value is represented as the garbage collection proportion threshold value, and the number of the user blocks represents the number of physical blocks operable by all users in the flash memory;
the method comprises the steps of storing a flash memory, storing the flash memory into a memory, and storing the flash memory into a memory storage device, wherein the memory storage device is used for storing the flash memory, and writing the flash memory into the memory storage device.
4. The memory device of claim 1, wherein the controller controls a headroom on the flash memory, the headroom satisfying:
reserved space= (total capacity-user capacity)/user capacity;
and on the flash memory, the user capacity represents the capacity corresponding to the physical block operable by the user, and the reserved space represents the ratio between the capacity corresponding to the physical block inoperable by the user and the user capacity.
5. A control method for garbage collection of a storage device, comprising:
storing storage data through a plurality of physical blocks on the flash memory;
the flash memory is electrically connected with the controller;
receiving, by the controller, the stored data written by the host; and
selecting a fixed number of logic units in each chip to be in an available state through the controller on the flash memory, and setting starting time of garbage recycling treatment;
the start time satisfies: start time = initial time (fixed number/total number)/write speed factor;
the total quantity represents the quantity of all logic units on each chip, the initial time represents the time for garbage collection processing of the flash memory when the total quantity of logic units on each chip are in an available state, and the writing speed factor represents the speed of writing data into the flash memory by the controller;
after the step of setting the speed gear of garbage collection treatment of the flash memory by the controller, the method comprises the following steps:
controlling the starting time of garbage recycling treatment through the controller;
the start time satisfies: start time = full capacity × garbage collection ratio threshold × (fixed number/full number)/(write speed factor × write speed);
wherein the full capacity characterizes a storage capacity of the flash memory when the full number of logic cells on each chip are in an available state, and the write speed characterizes a speed at which the controller writes the stored data to the flash memory.
6. The method for controlling garbage collection of a memory device according to claim 5, wherein after the step of selecting a fixed number of logic units in each chip to be in an available state, comprising:
acquiring the number of idle blocks and the number of used blocks in the flash memory through the controller;
the controller is used for setting the speed value of garbage recycling treatment once when the idle blocks of the starting quantity are consumed;
the number of starts satisfies: start number = initial number;
when all logic units on each chip are in an available state, the number of idle blocks consumed by the speed value of garbage collection processing is adjusted and recorded as the initial number;
after the garbage collection is started, the garbage collection and the writing of the host computer need to share the total writing bandwidth of the flash memory, and the writing speed of the host computer is defined as a speed value.
7. The method according to claim 6, wherein the step of adjusting a speed value of garbage collection processing for each consumption start-up number of the idle blocks by the controller comprises:
setting a speed gear of garbage collection treatment of the flash memory through the controller;
the speed gear of the garbage recycling treatment meets the following conditions: garbage collection speed gear= (number of user blocks-number of user blocks×garbage collection ratio threshold)/initial number;
wherein, when the ratio of the number of used blocks to the number of user blocks reaches an upper limit value, the upper limit value is represented as the garbage collection proportion threshold value, and the number of user blocks represents the number of physical blocks operable by all users in the flash memory;
the method comprises the steps of storing a flash memory, storing the flash memory into a memory, and storing the flash memory into a memory storage device, wherein the memory storage device is used for storing the flash memory, and writing the flash memory into the memory storage device.
8. The method for controlling garbage collection of a memory device according to claim 5, wherein after the step of selecting, by the controller, that a fixed number of logic units in each chip are in an available state and setting a start time of garbage collection processing on the flash memory, the method comprises:
controlling a reserved space on the flash memory through the controller;
the reserved space satisfies the following conditions: reserved space= (total capacity-user capacity)/user capacity;
and the reserved space represents the ratio between the capacity corresponding to the physical block which is not operable by the user and the user capacity.
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