CN116582126B

CN116582126B - Frequency band searching method based on phase-locked loop

Info

Publication number: CN116582126B
Application number: CN202310856780.9A
Authority: CN
Inventors: 黄裕钧; 蒋平; 张珍瑜; 王航; 吴茂林
Original assignee: Nanjing Qixin Semiconductor Co ltd
Current assignee: Nanjing Qixin Semiconductor Co ltd
Priority date: 2023-07-13
Filing date: 2023-07-13
Publication date: 2023-09-22
Anticipated expiration: 2043-07-13
Also published as: CN116582126A

Abstract

The invention discloses a frequency band searching method based on a phase-locked loop, which comprises the following steps: selecting a frequency band, setting a phase-locked loop for tracking, setting M output voltage reading points in tracking waiting time, recording the current frequency band and the last output voltage value when the continuous N output voltages read at the M output voltage reading points meet the condition, and ending the frequency band search; when the read output voltages do not have continuous N output voltages meeting the condition, the last output voltage confirmation is carried out after the tracking waiting time timing is finished, if the voltages meet the condition, the current frequency band and the last output voltage value are recorded, and if the voltages do not meet the condition, the frequency band searching is finished to the next frequency band searching. According to the invention, the plurality of output voltage reading points are arranged in the original longer waiting time, when a plurality of continuous output voltages meet the condition, namely the frequency band searching is stopped, the subsequent redundant waiting is avoided, the system resources are saved, and the overall efficiency is improved.

Description

Frequency band searching method based on phase-locked loop

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a frequency band searching method based on a phase-locked loop.

Background

Phase locked loop (Phase Locked Loops, PLL) technology has been widely used in communication carrier generation or microsystem internal clock applications for generating accurate timing pulses. The need for fast frequency synthesizers (synthesizers) is also increasing. This requires not only the VCO (voltage controlled oscillator) to quickly generate the oscillation frequency and the phase locked loop to adjust the settling time, but also a decision lock mechanism to ensure the accuracy of the generated frequency.

By designing the VCO supporting multiple frequency band ranges, the VCO has a wider frequency support range. This means that when different frequency BANDs (i.e. BAND) are selected, different frequencies can be generated. In a VCO with a more common frequency support range of 3GHz to 6GHz, 64 frequency bands are typically designed to cover the complete frequency range. Although each BAND is designed to support a certain frequency BAND, due to the temperature environment differences during circuit operation, the frequency offset is generated, so that each BAND is designed to Overlap (overlay) to ensure that the boundary frequency is supported by more than one BAND.

To generate a frequency quickly, the following operations are required: firstly, selecting the most suitable BAND, secondly, tracking by using a phase-locked loop, and then judging whether a tracking structure is locked or not, and if so, completing the generation of frequency; otherwise, selecting the next BAND, and repeating the above steps.

Whether the tracking result is locked or not is judged mainly by the output voltage (Kvco) provided by the phase-locked loop. This voltage provides the primary input to the VCO, which determines the oscillation frequency. If the voltage always assumes a high level or a low level, it represents the frequency to be locked, which is not within the BAND-supported range; if the voltage jumps in a certain interval, the phase-locked loop is still locked; if the voltage is stabilized within a certain interval, the frequency is locked. In circuit design, SAR ADC (ADC for short) is used for rapidly sampling Kvco voltage, and the voltage is converted into a numerical value for judgment. The flow of BAND SEARCH is shown in fig. 1, and the operations in the flow are described as follows:

WAIT0：

a PLL is set. If the time is set for the first time, the time is generally longer, and the time delay pll_timer_long is used; if not, using time delay pl_timer_short. PLL setup is followed by WAIT1.

WAIT1:

ADC analog-to-digital conversion is started using TIMER1 delay.

WAIT2:

The ADC analog-to-digital conversion process takes a number of clock cycles and when EOC is 1, the PLL phase locked output voltage Kvco is converted to a value.

CHECK:

And comparing the converted values, if the values are within the expected range, indicating that the BAND value can be used, and ending the search. If the BAND value is not within the expected range, the BAND value is adjusted according to the plus or minus setting, and if the adjustment times have exceeded the upper limit value (pl_max_iter), or the BAND value reaches the upper limit value (pl_max_iter), or the BAND value is subtracted to be 0, the 3 are regarded as search failures, and the search is also ended.

The BAND value search process typically repeats the WAIT 0-CHECK process multiple times, and determines whether the BAND value is appropriate by determining the PLL phase locked output voltage. Typically, in an unsuitable situation, the output voltage will be one of the two results, i.e. the maximum voltage or near 0V, for example, using an analog-to-digital conversion of an 8-bit ADC, the maximum voltage corresponds to a value of 255 and the minimum value of 0; if BAND is appropriate, the output voltage will tend to fall at half the maximum voltage, with an ADC reading of 128. However, the voltage will be shifted due to the chip process and environmental impact. Therefore, an acceptable upper and lower threshold interval is set in the voltage judgment, that is, when the converted value falls within the interval, such as between 30 and 240, the judgment is appropriate; otherwise, it is not appropriate.

Fig. 2 is a schematic diagram of the variation of PLL Kvco output voltage, and the process of setting a VCO BAND includes the following 5 judgment nodes or steps:

1: VCO BAND search start, after the judgment, entering WAIT0;

2: WAIT0 end, after the judgment, leave WAIT0 to enter WAIT1; the code is as follows:

end_wait 0= pll_timer event trigger

The pll_timer event contains:

pll_timer_long initial enable PLL

pll_timer_short non-initial enable PLL

3: WAIT1 end, after the judgment, leave WAIT1 to enter WAIT2; the code is as follows:

end_wait 1= timer1 event trigger

timer1 is the delay required for starting ADC, and analog-to-digital conversion is performed when the time is up

4: WAIT2 end, after the judgment, leave WAIT2 to enter CHECK; the code is as follows:

end_wait 2= EOC 1

Multiple crystal oscillator clocks are needed for ADC digital-to-analog conversion, and EOC is 1 after digital-to-analog conversion is completed and becomes a numerical value

5: CHECK; ending after the judgment; the code is as follows:

end_search= =1 search end

The search ends when any of the following conditions is satisfied:

selecting an appropriate VCO BAND

Exceeding the maximum number of searches (pll_max_iter)

Increment mode, exceeding maximum BAND upper limit

And a decrementing mode below a minimum BAND lower limit.

The time required for judging the section of the node 1-2 is long, the phase can be automatically adjusted by the circuit in the process, and the output voltage can also show an unstable jumping state; after the automatic adjustment of the circuit is finished, the output voltage is gradually stabilized. In order to wait for the output voltage to stabilize, a delay pll_timer is used to wait in step 1, and after the waiting is completed, it is further confirmed whether the voltage is appropriate. Since the output voltage stabilizing time is different under the condition of different frequency and different parameter settings, in order to avoid the problem of early reading caused by reading before the output voltage is stabilized, the waiting time is usually set to the maximum possible value of the system in practical application so as to avoid errors. As such, most of the waiting time is actually superfluous, resulting in waste of system resources.

Disclosure of Invention

In order to solve the problems, the invention discloses a frequency band searching method based on a phase-locked loop, which divides waiting time into a plurality of section waiting time lengths by setting a plurality of reading points, and stops the frequency band searching when the judging condition is met, so as to avoid redundant waiting time.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

a frequency band searching method based on phase-locked loop includes the following steps:

selecting a frequency band, setting a phase-locked loop for tracking, setting M output voltage reading points in tracking waiting time, and when N continuous output voltages read at the M output voltage reading points meet the condition, wherein N is more than or equal to 2 and less than or equal to M, the phase-locked loop is in a frequency locking state, recording the current frequency band and the last output voltage value, and ending the frequency band searching; when the read output voltages do not have continuous N output voltages meeting the condition, the last output voltage confirmation is carried out after the tracking waiting time timing is finished, if the voltage meeting the condition, the phase-locked loop is in a frequency locking state, the current frequency band and the last output voltage value are recorded, and if the voltage does not meet the condition, the frequency band searching is finished to the next frequency band searching.

Further, the step of reading the output voltage includes:

using a delay, starting ADC analog-to-digital conversion;

when EOC is 1, the PLL phase locked output voltage is converted to a value.

Further, the meeting condition means that: the output voltage is not higher than the upper threshold or not lower than the lower threshold or within the upper and lower threshold.

Further, when the voltage satisfies the condition, the BAND value is adjusted after the BAND search is finished, the steps in the BAND search method based on the phase-locked loop are repeatedly executed, when K continuous BANDs which enter the frequency locking state are selected, the BAND with the output voltage value closest to half of the maximum voltage is selected, and the search is finished, wherein K is more than 1.

Further, when the voltage does not meet the condition, the BAND value is adjusted after the current frequency BAND search is finished, the steps in the frequency BAND search method based on the phase-locked loop are repeatedly executed, and if the adjustment times exceed the upper limit or the BAND value exceeds the upper and lower limit ranges, the search is finished.

Further, the value of M is 4.

The beneficial effects of the invention are as follows:

according to the invention, the plurality of output voltage reading points are arranged in the original longer waiting time, and when a plurality of continuous output voltages meet the conditions, the frequency band searching is stopped, so that the subsequent redundant waiting is avoided, the system resources are saved, and the overall efficiency is improved. Experiments prove that the total time consumption of the case with 112us by the original method is 66us after the improvement by the method, and the time is saved by 46us.

Drawings

Fig. 1 is a schematic diagram of a VCO BAND SEARCH flow.

Fig. 2 is a diagram showing SAR ADC value change.

FIG. 3 is a graph showing SAR ADC value variation with increasing read points.

Fig. 4 is a complete BAND search embodiment.

Detailed Description

The technical scheme provided by the present invention will be described in detail with reference to the following specific examples, and it should be understood that the following specific examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.

Embodiment one: as shown in fig. 3, four points a, b, c, d are added to read the value of the current output voltage in the PLL setting step, and it is determined whether the current BAND is within the set range, and if the voltages of consecutive N points among the four points a, b, c, d satisfy the condition, the current BAND is considered to be appropriate. The time of each dot interval is set to be T1 (time interval waiting from the start point to the read point a), T2 (time interval reading point a to reading point b), T3 (time interval reading point b to reading point c), T4 (time interval reading point c to reading point d), respectively, in us, wherein the value of t1+t2+t3+t4 needs to be smaller than WAIT0 waiting time, i.e., pll_timer. It should be noted that T1 is a period from the start point of the PLL setting step to the read point a. N may be independently set, such as 2 or 3 or 4.

The 4-point value design is adopted, and the setting of continuous N-point inspection can be suitable for two extreme environment conditions with large voltage fluctuation or stability. When the voltage variation is large, a relatively large number of reading points are needed to confirm that the voltage is in a stable state; otherwise, if the voltage is stable, fewer reading points are used for judgment.

The 4-point value design is an optimized design made by combining the present invention with actual operation, and the number of read points in the PLL setting step can be adjusted up and down as needed or as technology progresses, for example, set to 3 points or more than 4. The number of the value points can be set as M, and N is more than or equal to 2 and less than or equal to M.

After the improvement of the invention, a plurality of segment waiting time periods are set through the inter-timer in the WAIT0 action, and the sum of the segment waiting time periods is smaller than the time period of the pll-timer. And reading the output voltage when the time of the T1 time is ended, namely an a point reading value, reading the output voltage when the time of the T2 time is ended, namely a b point reading value, reading the output voltage when the time of the T3 time is ended, namely a c point reading value, and reading the output voltage when the time of the T4 time is ended, namely a d point reading value.

Based on this, the complete steps of the band search in this embodiment are as follows:

step 1, selecting a frequency band, setting a phase-locked loop for tracking, and waiting according to the duration of a time delay pll_timer (usually pll_timer_long or pll_timer_short, two assignments can be defined by self); setting M output voltage reading points in the delay waiting time, and entering a subsequent step 2 when the time of each output voltage reading point is reached, and starting the ADC. The sum of the time interval between the output voltage reading points plus the time from the waiting starting point to the first output voltage reading point is less than or equal to the total waiting time; i.e. there is typically some time between the last output voltage reading point and the end of the delay latency. The reading points of the output voltages can be uniformly arranged or can be arranged according to the needs.

The code of the step is as follows:

end_wait 0= = pll_timer event+inter_timer event trigger

The time event comprises:

inter_timer (M detection points T1/T2/./ TM)

pll_timer_long (initial enable PLL)

pll_timer_short (not first enable PLL).

Step 2, using a TIMER1 delay to start an ADC to read the output voltage of the PLL phase lock; the code of the step is as follows:

end_wait 1= timer1 event trigger

timer1 is the delay required for starting the ADC, and the analog-to-digital conversion is performed when the time is up.

Step 3, when EOC is 1, ADC takes value;

end_wait 2= EOC 1

The ADC digital-to-analog conversion requires a plurality of crystal oscillator clocks, and EOC is 1 after the digital-to-analog conversion is finished to be a numerical value.

Step 4, reading the output voltage and judging that the output voltage is within an expected range (not higher than an upper threshold value or not lower than a lower threshold value or within the upper and lower threshold ranges), wherein the output voltage meets the condition; if the N output voltages are continuously read to meet the condition, the phase-locked loop is in a frequency locking state, the current frequency band and the last output voltage value are recorded, and the frequency band search is finished (early). Before the pll_timer is finished, returning to the step 1 when the output voltage meets the condition that N continuous voltages are not met, and waiting for the next voltage reading point; when the continuous N output voltages do not exist in the read output voltages and meet the conditions, i.e. the i-th output voltage is read to be still unsatisfied with the conditions, and when M-i is less than N (i is less than or equal to N), the rest reading points are insufficient to support the continuous reading of the N output voltages and meet the conditions, the judgment of the rest voltage reading points is not carried out, the final judgment is carried out after the pll_timer is finished, if the final output voltage meets the conditions, the BAND value can still be used, and the search is ended; if the final output voltage does not meet the condition, the BAND value is judged to be unusable, and the BAND search is ended. And (3) adjusting the BAND value according to a preset rule, returning to the step (1), searching for a new BAND value for tracking, repeating the steps, and if the adjustment times of the final BAND value exceeds an upper limit or the BAND value exceeds an upper limit and a lower limit, indicating that the search fails and ending the search. The code of the step is as follows:

end_search= =1 search end

The search ends when any of the following conditions is satisfied:

selecting an appropriate VCO BAND (adding M, N, K decisions)

Exceeding the maximum number of searches (pll_max_iter)

Increment mode, exceeding maximum BAND upper limit

And a decrementing mode below a minimum BAND lower limit.

It should be noted that other steps of the band searching may be changed in different application scenarios or requirements, and the innovation point of the present invention is mainly that in the phase-locked loop-based band searching process of step 1 and step 4, other steps may be adopted, abandoned and replaced as required.

The judgment as described in the background art is performed at the beginning or the end of the step, which belongs to the prior art, and is not described in detail in the embodiment of the present invention.

Embodiment two: in this example, N is set to 2, that is, if 2 continuous voltages in the four point readings of a, b, c, d satisfy the condition, it is determined that BAND is appropriate, for example: and if the conditions are met in the T1 and T2 segment waiting time periods or the conditions are met in the T2 and T3 segment waiting time periods or the conditions are met in the T3 and T4 segment waiting time periods, the current BAND is considered to be proper, the phase-locked loop is in a frequency locking state, and the current frequency BAND and the last output voltage value are recorded. Otherwise, enter and judge 2- >3- >4- >5 according to the normal order and enter the corresponding flow after judging. The decision truth table is as follows:

a	b	c	d	determination of
					N	N	N	X	N
N	N	Y	Y	Y
					N	Y	N	X	N
N	Y	Y	X	Y
					Y	N	N	X	N
Y	N	Y	N	N
					Y	N	Y	Y	Y
Y	Y	X	X	Y

TABLE 1

Embodiment III: when N is set to 3, then it indicates that there are consecutive 3 voltages satisfying the condition in a, b, c, d point reads, such as: and if the conditions are met in the T1, T2 and T3 segment waiting time periods or the conditions are met in the T2, T3 and T4 segment waiting time periods, the current BAND is considered to be proper, the phase-locked loop is in a frequency locking state, and the current frequency BAND and the last output voltage value are recorded. Otherwise, enter 2- >3- >4- >5 according to the normal sequence to judge and then enter the corresponding flow. The decision truth table is as follows:

a	b	c	d	determination of
					N	N	X	X	N
N	Y	N	X	N
					N	Y	Y	N	N
N	Y	Y	Y	Y
					Y	N	X	X	N
Y	Y	N	X	N
					Y	Y	Y	X	Y

TABLE 2

Embodiment four: when N is set to 4, the necessary 4 voltages in the a, b, c, d read value all meet the condition, then the current BAND is considered to be suitable, the phase-locked loop is in a frequency locking state, and the current frequency BAND and the last output voltage value are recorded. Otherwise, enter 2- >3- >4- >5 according to the normal sequence to judge and then enter the corresponding flow. The decision truth table is as follows:

a	b	c	d	determination of
					N	X	X	X	N
Y	N	X	X	N
					Y	Y	N	X	N
Y	Y	Y	N	N
					Y	Y	Y	Y	Y

TABLE 3 Table 3

Fifth embodiment: fig. 4 shows an embodiment of a complete BAND search, in which the upper thick line of channel 2 is the output voltage, the lower straight thick line of channel 1 is the BAND switch indication, and the horizontal thin line is the upper threshold of the voltage. It can be seen that after the search is started, each BAND uses a fixed delay of 28us, through a handover of 4 BANDs.

As can be seen from the above table, the first segment waiting time period is relatively long (10 us from the start time point), and the remaining segment waiting time periods are uniformly set at intervals of 2 us. The output voltages of BAND #1 are all above the threshold. When the output voltages read by the reading points a and b do not meet the condition, the remaining points c and d cannot meet the condition that the BAND search is successful n=3, so that the output voltages are not judged at the points c and d any more, the end of the pll_timer timing is waited to enter the final judgment, the BAND is unsuitable as a result, the search is ended after the BAND #1 passes through 28us, and the BAND is adjusted to #2 according to the preset rule (up-regulation in this case). The first half of the output voltage of BAND #2 is above the threshold, the voltage read at point a does not meet the condition, but after 10us passes below the upper threshold, the voltage read at three consecutive points b, c and d meets the condition, the BAND is suitable, and the BAND #2 ends the search after 16us passes. The output voltage of BAND #3 was stable over 8us and was all below the upper threshold, and BAND #3 was over 14us ending the search. The output voltage of BAND #4 was stable over 8us and was all below the upper threshold, and BAND #4 was over 14us ending the search. In the BAND #3 and BAND #4 searches, if the output voltages of the three points a, b and c are all satisfied, the BAND is appropriate, and the BAND search is ended after 14 us. In this example, band#2 search has satisfied the condition, and in order to improve the frequency BAND search accuracy, a number of BAND search processes is added, and after 3 consecutive BANDs (the number K may be adjusted as needed, K > 1) satisfying the condition are selected, the number K of BANDs is preferred therefrom. The preference rule is to select BAND where the value of the SAR ADC is closest to half the maximum voltage.

Judging for bands #1 to #4, wherein the total time consumption of the original method is 112us, and after M=4 and N=3 are adopted as parameters, the optimization result is 72us, so that 40us is saved. If m=4 and n=2 are used as parameters, b1=28us, b2=14us, b3=12 and b4=12, the total time consumption is 66us, and 46us is saved.

The invention designs M reading points capable of defining time, matches N times of reading logic with effective satisfying conditions and takes a mode of optimizing continuous K BAND, thereby achieving the purposes of configuration elasticity, shortening search time, obtaining optimal BAND value and the like. It should be noted that the foregoing merely illustrates the technical idea of the present invention and is not intended to limit the scope of the invention, and that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention, which fall within the scope of the claims of the present invention.

Claims

1. The frequency band searching method based on the phase-locked loop is characterized by comprising the following steps:

2. The phase-locked loop based frequency band searching method of claim 1, wherein the step of reading the output voltage comprises:

using a delay, starting ADC analog-to-digital conversion;

when EOC is 1 after the digital-to-analog conversion is completed, the PLL phase locked output voltage is converted to a value.

3. The phase-locked loop based frequency band searching method of claim 1, wherein the satisfaction condition is: the output voltage is not higher than the upper threshold.

4. The phase-locked loop based frequency band searching method of claim 1, wherein the satisfaction condition is: the output voltage is not lower than the lower threshold.

5. The phase-locked loop based frequency band searching method of claim 1, wherein the satisfaction condition is: the output voltage is within the upper and lower threshold ranges.

6. The phase-locked loop based BAND searching method of claim 1, wherein when the voltage satisfies the condition, BAND searching is finished and BAND value is adjusted, the steps in the phase-locked loop based BAND searching method are repeatedly performed, and when K consecutive frequency BANDs entering the frequency locked state are selected, a frequency BAND having an output voltage value closest to half of the maximum voltage is selected, and searching is finished, wherein K >1.

7. The phase-locked loop based BAND searching method of claim 1, wherein when the voltage does not satisfy the condition, the BAND value is adjusted after the current BAND searching is ended, the steps in the phase-locked loop based BAND searching method are repeatedly performed, and if the number of adjustments exceeds an upper limit or the BAND value exceeds an upper and lower limit range, the searching is ended.

8. The phase-locked loop based frequency band searching method of claim 1, wherein the M takes a value of 4.