CN116579354A

CN116579354A - Stacked PCB reflowable decoder module

Info

Publication number: CN116579354A
Application number: CN202310604279.3A
Authority: CN
Inventors: C.冯; L.王; J.卢; J-M.皮奇; T.仙; E.C.布雷默
Original assignee: Hand Held Products Inc
Current assignee: Hand Held Products Inc
Priority date: 2016-09-14
Filing date: 2016-09-14
Publication date: 2023-08-11
Also published as: CN107818274A

Abstract

A Surface Mount Technology (SMT) decoder assembly for an indicia reading device includes a main Printed Circuit Board (PCB), a processor chip, and a plurality of reflowable pads. The main PCB is a double sided PCB having a top side and a bottom side. The processor chip is located on the top side of the main PCB. The plurality of reflowable pads are located on the bottom side of the main PCB for surface mounting the decoder component.

Description

Stacked PCB reflowable decoder module

The application is a divisional application of an application patent application with the application date of 2016, 9 and 14, the application number of 201610823426.6 and the name of a 'stacked PCB reflowable decoder module'.

Technical Field

The present disclosure relates generally to indicia reading devices and, more particularly, to indicia reading devices and methods for producing indicia reading devices using stacked printed circuit board ("PCB") reflowable decoder modules.

Background

In general, an indicia reading device (also known as a scanner, laser scanner, image reader, indicia reader, mobile computer, terminal, etc.) typically reads data represented by printed or displayed information-bearing indicia (also known as symbols, symbologies, bar codes, etc.). Bar codes, such as UPC codes, use a pattern of thick and thin lines to represent data, while more complex decoding systems (known as 2D matrix codes) use a complex square pattern and arrangement to store information.

A one-dimensional (1D) or linear optical bar code reader is characterized by reading data encoded along a single axis in the presence of lines and spaces and/or widths of lines and spaces so that such symbols can be read from a single scan along the axis.

Two-dimensional (2D) or area optical bar code readers utilize lenses to focus an image of a bar code onto a multi-pixel image sensor array, which is typically provided by CMOS-based or CCD-based image sensor arrays that convert optical signals into electrical signals.

Conventional 1D and 2D indicia readers or bar code scanners/readers are known and come in many different shapes and sizes, like 1D and/or 2D wireless handheld bar code scanners for scanning codes. As will be readily appreciated by those skilled in the art, more reliable, cheaper and more compact, better. As such, there is a clear need or desire to produce an indicia reader or bar code scanner that is more reliable, less expensive to manufacture, and/or more compact.

The indicia reading device generally includes an imager and a memory in communication with the imager capable of storing image data from the imager. In addition, a processor is included to decode image data captured by the imager and stored in the memory. The processor is operable to decode the various forms of decodable indicia represented in the image data. These general-purpose components and any other various components included in the indicia reading device are typically connected together via a host system bus or Printed Circuit Board (PCB).

Conventional decoder modules are typically integrated into the host system PCB by means of flex cables or board-to-board connectors. Additional mechanical fasteners may be required to secure the cables or connectors of the decoder module. It has been determined that these flexible cables and board connectors are unreliable because they are a source of failure in the indicia reading device when it has been found that these cables and/or connectors become disconnected. In addition, these flex cables and board-to-board connectors take up space and require sufficient space inside the indicia reading device to include these components and make the necessary connections.

One alternative to flex cables and board-to-board connectors for decoder modules is a single chip decoder, like an Application Specific Integrated Circuit (ASIC) single chip solution. However, ASIC single chip decoders are costly and development and setup are long processes. The lack of flexibility is another concern for ASIC single chip solutions.

Accordingly, there is a need for a means to connect decoder modules that improves reliability, is relatively inexpensive to incorporate, and/or is more compact. The present disclosure is designed to address at least some or all of these problems by providing a stacked PCB reflowable decoder module.

Disclosure of Invention

Accordingly, in one aspect, the invention includes a Surface Mount Technology (SMT) decoder component. The SMT decoder assembly can be used in an indicia reading device. The SMT decoder component generally includes a main Printed Circuit Board (PCB), a processor chip, and a plurality of reflowable pads. The main PCB is a double sided PCB having a top side and a bottom side. The processor chip is located on top of the main PCB. A plurality of reflowable pads are located on an edge of the bottom side of the main PCB for surface mounting a decoder component.

In an exemplary embodiment, an SMT decoder assembly includes a cavity on a perimeter of the bottom side of the main PCB between a plurality of reflowable pads on the bottom side of the main PCB.

In alternative embodiments, the cavity may be formed by a bond pad ring PCB having a plurality of reflowable bond pads. The solder pad ring PCB may be a double sided ring PCB with connections to the main PCB on the front side and with connections for the reflowable solder pads on the back side. In alternative embodiments, the solder pad ring PCB may be a 2-sided ring with connectors (2-sided ring PCB), or the solder pad ring PCB may be a ring with connectors on all 4 sides (4-sided ring PCB).

In other alternative embodiments, the cavity may be formed by at least two pad edge PCBs having a plurality of reflowable pads. The pad edge PCB may be a double sided edge PCB with connections to the main PCB on the front side and with connections for the reflowable pads on the back side.

In another exemplary embodiment, the SMT decoder assembly can include other components. These other components may be located in the cavity on the bottom side of the main PCB and may also be located on the top side of the main PCB. These other components may include, but are not limited to, memory components, oscillator components, and/or passive components. For example, the memory component may be, but is not limited to, a Dynamic Random Access Memory (DRAM) chip and/or a flash memory chip. In alternative embodiments, the cavity may have a thickness that approximates the highest of the other components on the bottom side of the main PCB.

In another exemplary embodiment, the SMT decoder assembly may include a top seal and/or a bottom seal. A top seal may be located on top of the SMT decoder component, with a cutout configured to fit around the processor chip. A top seal may enclose the top side of the main PCB around a decoder module chip. A bottom seal may be located on the cavity of the SMT decoder component between the plurality of reflowable pads. A bottom seal may enclose the bottom side of the PCB, including any of the other components on the bottom side of the PCB. The top seal and/or the bottom seal may be configured to provide thermal conduction and/or structural protection to the SMT decoder component.

In another exemplary embodiment, the SMT decoder assembly may have dimensions with a length, width, and depth that may be about 20% greater or less than the dimensions of the decoder processor chip with a length, width, and depth.

In another aspect, the invention includes an indicia reading device with an SMT decoder module. In general, an indicia reading device includes a host system board and an SMT assembled decoder module connected to the host system board. The SMT decoder component may be surface mounted to a host system board.

In an exemplary embodiment, an indicia reading device includes an imaging subsystem and a memory component. The imaging subsystem may be connected to a motherboard. The memory component may be located in an SMT decoder component. The memory component may be in communication with the imaging subsystem and may be capable of storing one or more frames in image data representative of light incident on the imaging subsystem. The processor chip may be in communication with the memory component through the main PCB and may be operable to decode the decodable indicia represented in at least one of the frames of image data.

In alternative embodiments, the indicia reading device may be a handheld bar code scanner.

In another aspect, the present disclosure includes a method of assembling a Surface Mount Technology (SMT) decoder assembly for an indicia reading device. The method may generally comprise the steps of:

providing a double-sided main Printed Circuit Board (PCB) having a top side configured to receive a processor chip and a bottom side having a plurality of reflowable pads configured for surface mounting to a host system board; and

-mounting the processor chip on the top side of the main PCB.

In an exemplary embodiment, the method may further include the steps of:

-forming cavities between the plurality of reflowable pads on the bottom side of the main PCB; and

mounting other components in the cavity on the bottom side of the main PCB.

In yet another exemplary embodiment of a method of assembling a Surface Mount Technology (SMT) decoder component for an indicia reading device, the step of forming a cavity on the bottom side of the main PCB may comprise the steps of:

providing a solder pad ring PCB having the plurality of reflowable solder pads, wherein the solder pad ring PCB is a double-sided ring PCB having connections to the main PCB on a front side and connections for the reflowable solder pads on a back side; and

Mounting the solder pad ring PCB on the bottom side of the main PCB, thereby forming a cavity on the bottom side of the main PCB;

providing at least two pad edge PCBs with the plurality of reflowable pads, wherein the pad edge PCBs are double-sided edge PCBs with connections to the main PCB on a front side and with connections for the reflowable pads on a back side; and

mounting the pad edge PCB on the bottom side of the main PCB, forming a cavity on the bottom side of the main PCB.

In yet another exemplary embodiment of a method of assembling a Surface Mount Technology (SMT) decoder component for an indicia reading device, the step of providing a solder pad ring PCB with a plurality of reflowable solder pads may include providing tabs at an offset from the solder pad ring PCB, wherein the step of mounting the solder pad ring PCB on the bottom side of the main PCB comprises the steps of:

pick up the solder pad ring PCB via the tab; and

Placing the solder pad ring PCB on the main PCB via the tab;

in these embodiments, the tab may be connected between the solder pad ring PCB and an adjacent solder pad ring PCB.

In yet another exemplary embodiment of a method of assembling a Surface Mount Technology (SMT) decoder component for an indicia reading device, the step of mounting the solder pad ring PCB on the bottom side of the main PCB or the step of mounting a solder pad edge PCB on the bottom side of the main PCB comprises the steps of:

pick up the main PCB with the processor chip mounted on the top side and any other components mounted on the bottom side; and

placing the main PCB on the pad ring PCB or the pad edge PCB.

In alternative embodiments, the following steps may be included: a cover configured to be secured on the top side of the main PCB is utilized to pick up and place the main PCB on a solder pad ring PCB.

In still other exemplary embodiments, a method of assembling a Surface Mount Technology (SMT) decoder component for an indicia reading device may comprise the steps of:

closing the top side of the PCB around the processor chip with a top seal; and/or

-closing a cavity between the plurality of reflowable pads on the bottom side of the main PCB with a bottom seal; and

Heat conduction and/or structural protection is provided to the SMT decoder component via the top seal and/or the bottom seal.

The foregoing exemplary summary, as well as other exemplary objects and/or advantages of the invention, and the manner in which the same are accomplished, are further explained in the following detailed description and the accompanying drawings thereof.

Drawings

FIGS. 1A and 1B schematically illustrate a prior art decoder board subassembly with a flexible connector and a board-to-board connector;

2A, 2B, 2C, 2D, 2E, and 2F schematically illustrate a Surface Mount Technology (SMT) decoder assembly for an indicia reading device in perspective view (FIGS. 2A and 2B), front view (FIG. 2C), side view (FIG. 2D), rear view (FIG. 2E), and exploded view (FIG. 2F) in accordance with selected embodiments of the present disclosure;

FIGS. 3 and 4 schematically illustrate block diagrams of Surface Mount Technology (SMT) decoder assemblies for an indicia reading device according to selected embodiments of the disclosure;

FIGS. 5A and 5B schematically illustrate a top side (FIG. 5A) and a bottom side (FIG. 5B) of a double-sided main Printed Circuit Board (PCB) for a Surface Mount Technology (SMT) decoder assembly for an indicia reading device according to selected embodiments of the disclosure;

FIGS. 6A-6H schematically illustrate various layers of a main Printed Circuit Board (PCB) for a Surface Mount Technology (SMT) decoder assembly for an indicia reading device, including a top layer (FIG. 6A) and a bottom layer (FIG. 6H), according to selected embodiments of the present disclosure;

FIGS. 7A and 7B schematically illustrate a solder pad ring for a Surface Mount Technology (SMT) decoder assembly for an indicia reading device according to selected embodiments of the disclosure, including a front side (FIG. 7A) and a back side (FIG. 7B);

FIG. 8 schematically depicts a pad ring PCB or pad edge PCB for a Surface Mount Technology (SMT) decoder assembly for an indicia reading device according to an alternative embodiment of the disclosure;

FIG. 9 illustrates a table showing connections for a bond pad ring PCB or a bond pad edge PCB for a Surface Mount Technology (SMT) decoder assembly of an indicia reading device according to selected embodiments of the disclosure;

FIG. 10A schematically illustrates a Surface Mount Technology (SMT) decoder assembly for an indicia reading device having a 2-sided solder pad ring PCB with 2-sided connectors (i.e., 2-sided), according to an alternative embodiment of the present disclosure;

FIG. 10B schematically illustrates a Surface Mount Technology (SMT) decoder assembly for an indicia reading device having a solder pad ring PCB with all 4-sided connectors (i.e., 4-sided), according to an alternative embodiment of the present disclosure;

FIG. 10C schematically illustrates a Surface Mount Technology (SMT) decoder assembly for an indicia reading device having two pad edge PCBs on opposite sides according to an alternative embodiment of the disclosure;

FIG. 11 is a schematic physical form diagram of one embodiment of an imaging device (e.g., an indicia reading terminal) in accordance with aspects of the present disclosure;

fig. 12 and 13 illustrate other types of imaging devices according to aspects of the present disclosure;

FIG. 14 is a block diagram of one embodiment of the imaging device of FIG. 1;

FIGS. 15A and 15B schematically illustrate a Surface Mount Technology (SMT) decoder assembly for an indicia reading device surface mounted to a host system board with an imaging subsystem according to selected embodiments of the disclosure;

FIG. 16 schematically illustrates a flowchart of a method of assembling a Surface Mount Technology (SMT) decoder assembly for an indicia reading device according to selected embodiments of the disclosure;

17A, 17B and 17C schematically illustrate a solder pad ring PCB with tabs for picking up and placing a solder pad ring according to an alternative embodiment of a method for assembling a Surface Mount Technology (SMT) decoder assembly for an indicia reading device of the present disclosure;

18A, 18B and 18C schematically illustrate a method of assembling an SMT decoder assembly for an indicia reading device in which a main PCB with a processor chip is picked up and placed on a pad ring PCB or a pad edge PCB in accordance with selected embodiments of the present disclosure; and is also provided with

Fig. 19A, 19B and 19C schematically depict a cover for picking up and placing a main PCB with a processor chip according to an alternative embodiment of the present disclosure.

Detailed Description

Referring now to fig. 1A and 1B, a prior art decoder board subassembly 10 is shown. As shown in fig. 1A, the prior art decoder board subassembly includes a decoder board 11, a camera module 12, and a system board 13. As shown in fig. 1B, the prior art decoder board subassembly 10 includes fasteners 14, flexible PCB cables 15, and board-to-board connectors 16 for connecting the decoder board 11 to the system board 13. It has been determined that cables (like flexible PCB cable 15) and board connectors (like board-to-board connector 16) are unreliable because they can be a source of failure in the indicia reading device when it has been found that these cables and/or connectors become disconnected. For example, the screws (like fasteners 14) may become loose, allowing the decoder board 11 to become disconnected from the board-to-board connector 16 and/or flexible PCB cable 15. In addition, these flexible cables and board-to-board connectors occupy space and require sufficient space inside the indicia reading device.

The present disclosure includes surface-mount technology (SMT). SMT is a method for producing electronic circuits in which components are directly mounted or placed onto the surface of a Printed Circuit Board (PCB). The electronic device thus manufactured is called a Surface Mount Device (SMD). In the industry, it has largely replaced through-hole technology construction methods for fitting components with wire leads into holes in circuit boards. Both techniques can be used on the same board, with through-hole techniques for components unsuitable for surface mounting, such as large transformers and heat dissipating power semiconductors. SMT components are typically smaller than their through hole counterparts because they have smaller leads or no leads at all. It may have various styles of short pins or leads, flat contacts, a matrix of pads (BGA), or terminations on the body of the component. The present disclosure incorporates this SMT technology into the decoder module in order to connect the decoder module to the motherboard. The SMT technology may improve reliability, may be relatively inexpensive to incorporate, and/or may enable a more compact decoder assembly for an indicia reading device (like a bar code scanner, including a handheld bar code scanner).

Referring now to fig. 2-19, SMT decoder module 5000 is shown. The SMT decoder module 5000 may generally include a double sided main Printed Circuit Board (PCB) 5100 (hereinafter referred to as a main PCB 5100) and a processor chip 5200. The main PCB 5100 may be a double sided PCB having a top side 5102 configured to connect to the processor chip 5200 and a bottom side 5104 configured to connect to the plurality of reflowable pads 5300 (i.e., BGA) and any other components 5600 comprised by the SMT decoder module 5000. The processor chip 5200 on the top side 5102 of the main PCB 5100 may be a processor configured to decode the decodable indicia. The plurality of reflowable pads 5300 on the bottom side 5104 of the main PCB 5100 may be configured for surface mounting the decoder assembly 5000 to another circuit board or the like, including the host system board 1500 for application connection. A top seal 5700 can optionally be included on top of the SMT decoder assembly 5000 around the encoder processor chip 5200. The top seal 5700 may be used to enclose the exposed top side 5102 of the main PCB 5100 around the processor chip 5200. The top seal 5700 may provide a cutout around the processor chip 5200 for heat dissipation by the processor. A bottom seal 5800 may optionally be included on the cavity 5400 of the SMT decoder component 5000 between a plurality of reflowable pads 5300, like the solder pad ring PCB 5310 or inside the solder pad edge 5320 (see fig. 10C). The bottom seal 5800 may enclose the bottom side 5104 of the PCB, including any of the other components 5600 on the bottom side 5104 of the main PCB 5100. The top seal 5700 and/or the bottom seal 5800 can be configured to provide thermal conduction and/or structural protection to the SMT decoder component 5000.

The SMT decoder component 5000 may have dimensions 5010 including a length 5020, a width 5030 and a depth 5040, as shown in fig. 2C, 2D and 2E. These dimensions 5010 may be slightly larger than the decoder processor chip 5200, providing a relatively compact SMT decoder module assembly. For example, in one embodiment, the SMT decoder component may have a size 5010 that is greater than or less than about 50% of the size 5210 of the processor chip 5200 having a length 5220, a width 5230, and a depth 5240, or, possibly, preferably, the SMT decoder component may have a size 5010 that is greater than or less than about 30% of the size 5210 of the processor chip 5200 having a length 5220, a width 5230, and a depth 5240, or, possibly, most preferably, the SMT decoder component may have a size 5010 that is greater than or less than about 20% of the size 5210 of the processor chip 5200 having a length 5220, a width 5230, and a depth 5240. However, the present disclosure is not so limited, and the dimensions 5010 of the SMT decoder assembly 5000 may be configured for various applications as well as decoder module chips 5010 or other components 5600 of size and shape. For example, for using an IMX257-Plus decoder module chip provided by the holmivir scanning and movement technology department of Mi Erbao, south carolina, the size 5010 of the SMT decoder assembly 5000 may include a length 5020 of about or equal to 18mm, a width 5030 of about or equal to 15mm, and a depth 5040 of about or equal to 3.2 mm.

The cavity 5400 may be provided in the SMT decoder component 5000 on the bottom side 5104 of the main PCB 5100, as best shown in fig. 2F. The cavity 5400 may be disposed between the solder pads 5300, which may be located on one side, 2 sides, 3 sides, all sides, or anywhere on the perimeter 5106 of the bottom side 5104 of the main PCB 5100. The cavity 5400 may be used to include other components 5600 on the bottom side 5104 of the main PCB 5100. The other components 5600 included on the top side 5102 and/or the bottom side 5104 may be any desired component or chip for an indicia reading device including, but not limited to: memory component 5620, oscillator component 5630, and/or passive component 5640. In alternative embodiments, the memory component 5620 included in the cavity 5400 on the bottom side 5104 of the main PCB 5100 may include a Dynamic Random Access Memory (DRAM) chip 5622 and/or a flash memory chip 5624. The cavity 5400 may have a cavity thickness 5410 configured for the highest feature 5610 on the bottom side 5104 of the primary PCB 5100, as shown in fig. 2F.

Referring to fig. 2, 7, 8, 9, 10A, and 10B, in an alternative embodiment, the cavity 5400 may be formed on the bottom side 5104 of the main PCB 5100 via a solder pad ring PCB 5310. The solder pad ring PCB 5310 may be stacked onto the bottom side 5104 of the primary PCB 5100 by an SMT reflowable process. The bond pad ring PCB 5310 may include a plurality of reflowable bond pads 5300 on the back side 5316 for surface mounting the decoder assembly 5000. The solder pad ring PCB 5310 may be a double sided ring PCB 5311 having a front side 5312 with a connector 5314 for the bottom side 5104 of the main PCB board 5100 and a back side 5316 with a connector 5318 for the reflowable solder pad 5300. The solder pad ring PCB 5310 may have connectors on any or all sides of the ring, including as a ring 5313 with connectors on 2 sides (i.e., 2 sides), as shown in fig. 10A, or a ring 5315 with connectors on all 4 sides (i.e., 4 sides), as shown in fig. 10B.

Referring to fig. 8, 9, and 10C, in other alternative embodiments, the cavity 5400 may be formed on the bottom side 5104 of the main PCB 5100 via at least two pad edge PCBs 5320. The pad edge PCB 5320 may be stacked onto the bottom side 5104 of the primary PCB 5100 by an SMT reflowable process. The pad edge PCB 5320 may include a plurality of reflowable pads 5300 for the surface mount SMT decoder component 5000. Each pad edge PCB 5320 may be a double sided edge PCB 5321 having a front side 5322 with a connector 5324 for a bottom side 5104 of the main PCB board 5100 and a back side 5326 with a connector 5328 for a reflowable pad 5300. The pad edge PCB 5320 may be included on 2 or more edges, including on 2 opposite sides, of the main PCB 5100, as shown in fig. 10C. This may provide an open end on the bottom side of the SMT decoder component when it is connected to a circuit board (like the motherboard 1500), which may provide heat dissipation and improved thermal properties.

Referring to fig. 3 and 4, various example embodiments of block diagrams of SMT decoder components 5000 are shown. These block diagrams illustrate an example configuration for wire-connecting the processor chip 5200 to other components 5600 (including flash memory 5624, DDR RAM memory 5622, etc.). In addition, FIG. 4 illustrates an exemplary embodiment of connecting the image subassembly 900 to the SMT decoder assembly 5000.

Referring to fig. 5A and 5B, various example embodiments of the configuration of a primary PCB 5100 are shown, including a top side 5102 (fig. 5A) and a bottom side 5104 (fig. 5B) of the primary PCB 5100. The top side 5102 of the main PCB 5100 may be configured for surface mounting the processor chip 5200. The top side 5102 of the main PCB 5100 may also be configured for surface mounting other components 5600 as desired. The bottom side 5104 of the primary PCB 5100 may be configured for surface mounting reflowable solder pads 5300 to the solder pad ring PCB 5310 and/or the solder pad edge PCB 5320. In addition, the bottom side 5104 of the main PCB 5100 may be configured for other components 5600 within the surface mount cavity 5400 as desired.

Referring to fig. 6A-6H, various exemplary embodiments of configurations of various layers of a main PCB 5100 are shown. As shown herein, in one example embodiment, the primary PCB 5100 may include 8 printed layers for connecting the top side 5102 to the bottom side 5104. In this example, these 8 layers may be provided to obtain a sufficient EMC margin (margin) at 15mm x 17mm size with a main PCB 5100 thickness of 0.6 mm. However, the present disclosure is not so limited, and any desired number of printed layers may be included in the main PCB 5100 for connecting the top side 5102 to the bottom side 5104 in order to form the SMT decoder module 5000, including surface mounting the processor chip 5200 on the top side 5102, surface mounting the bond pad ring PCB 5310 and/or the bond pad edge PCB 5320 on the bottom side 5104, and/or surface mounting any other desired component 5600 on the top side 5102 and/or the bottom side 5104.

Referring now to fig. 7A and 7B, an example embodiment of a solder pad ring PCB 5310 is shown. As shown, the solder pad ring PCB 5310 is a double sided ring PCB 5311. Fig. 7A shows a front side 5312 of a connector 5314 with a bottom side 5104 for a main PCB 5100. Fig. 7B shows the back side 5316 with connectors 5318 that are reflowable pads 5300 for the surface mount SMT decoder module 5000.

Referring now to fig. 8 and 9, an example schematic pad 5300 pin arrangement is shown for the back side 5316 of the pad ring PCB 5310 (as noted, the same configuration may be used for the back side 5326 of the pad edge PCB 5320). However, the present disclosure is not so limited and any of a variety of pin arrangements may be used as desired.

Referring now to fig. 11-15, various embodiments of an indicia reading device 1000, 1001, 1002 are shown in accordance with the present disclosure. These indicia reading devices can generally include a host system board 1500 and a Surface Mount Technology (SMT) decoder component decoder module 5000 surface mounted to the host system board 1500, as shown in fig. 15. These indicia reading devices 1000, 10001, 10002 can further include an imaging subsystem 900 connected to the host system board 1500, and a memory component 5620. The memory component 5620 may be in communication with the imaging subsystem 900 and may be capable of storing one or more frames in image data representing light incident on the imaging subsystem 900. Wherein the processor chip 5200 can be in communication with the memory component 5620 through the main PCB 5100 and can be operable to decode a decodable indicia represented in at least one of the frames of image data.

Fig. 11 illustrates one embodiment of an imaging device (such as an indicia reading terminal 1000) for use in reading decodable indicia in accordance with aspects of the disclosure. The indicia reading terminal 1000 can be operative for reading decodable indicia such as bar code 1005 disposed, for example, on a non-backlit substrate 1007 (such as paper) attached to a product 1009. The decodable indicia can include, but is not limited to:

one-dimensional linear symbologies such as bar code 39, I25, bar code 128, UPC/EAN; and stacked linear barcodes, such as PDF-417, 16K, and barcode 49 (also commonly denoted as a two-dimensional symbology), in both cases containing information in the width of lines and spaces;

true two-dimensional matrix codes such as barcode 1, dataMatrix, maxiCode, QR-Code and Aztec Code, where information is included with or without markers at predetermined locations on the two-dimensional coordinate system; and/or

Human readable fonts, such as OCR and typed text.

Many of these tags have specifications defined that have been developed and approved by one or more international standard agencies, such as by AIM and recently by ISO/IEC.

Still referring to FIG. 11, indicia reading terminal 1000 can also be operative to read a decodable indicia such as a bar code 1150 displayed on an electronic device 1200 such as a backlight 1250, such as a display, monitor, LCD display, or other screen commonly employed in mobile phones, cellular phones, satellite phones, smart phones, telemetry devices, personal data assistants, and other devices. Although shown as reading a single decodable indicia at a time, it will be appreciated that the image may be operable to simultaneously capture one or more decodable indicia on a single object or on multiple objects.

For example, in one embodiment, terminal 1000 can include trigger 1220, display 1222, pointer mechanism 1224, and keyboard 1226 disposed on a common side of handheld housing 1014. Display 1222 and pointer mechanism 1224, in combination, may be considered a user interface for terminal 1000. In one embodiment, display 1222 may incorporate a touch sensitive panel for navigation and virtual actuator selection, in which case a user interface for terminal 1000 may be provided by display 1222.

Referring now to FIG. 12, in other embodiments, the hand-held housing 1015 of the indicia reading terminal 1001 may lack a display and keypad and may take the form of a gun-like form factor with a trigger 1221, as shown in FIG. 12. In other embodiments, the handheld housing 1016 of the indicia reading terminal 1002 can include a display 1223 and a keypad 1227, and can be in the form of a gun-like form factor with a trigger 1222, as shown, for example, in FIG. 13.

The following description uses nomenclature associated with an indicia reading terminal and may generally include a handheld indicia reading terminal, a fixed indicia reading terminal, however, those skilled in the art will recognize that aspects of the present disclosure may be incorporated into other electronic devices having imagers for image capture and/or indicia reading, which may be configured as, for example, mobile phones, cellular phones, satellite phones, smart phones, telemetry devices, personal data assistants, cameras, and other devices.

Fig. 14 depicts a block diagram of one embodiment of an indicia reading terminal, such as indicia reading terminal 1000, 1001 or 1002. In general, an indicia reading terminal can include an illumination subsystem g00, a aimer subsystem 600, an plenoptic imaging subsystem 900 (including plenoptic imaging optics 200 and image sensor integrated circuit 1040 having an image sensor array 1033), a hand-held housing 1014, 1015 or 1016, a memory component 1085, and a processor 1060. As described in more detail below, plenoptic imaging optics 200 allows 4D light field information of scene S (fig. 1) to be captured onto image sensor array 1033. For example, plenoptic imaging optics 200 may include a main lens 220 and a microlens array 250. The microlens array may include thousands of microlenses, and the microlens array may be disposed between the main lens and the image sensor array. Analog signals of the scene or portions thereof read out of image sensor array 1033 may be amplified by gain block 1036, converted to digital form by analog-to-digital converter 1037, and sent to DMA unit 1070.DMA unit 1070 can then transfer the digitized image data into volatile memory 1080. Processor 1060 can address one or more frames of image data stored in volatile memory 1080 for processing for tag decoding as described below. The image captured by the plenoptic image optics is referred to as a plenoptic image. The data captured on the image sensor by the plenoptic imaging optics is referred to as plenoptic image data.

Referring again to fig. 14, terminals 1000, 1001, 1002 can include an image sensor 1032 that includes a multi-pixel image sensor array 1033 having pixels arranged in rows and columns of pixels, associated column circuitry 1034, and row circuitry 1035. Amplifier circuitry 1036 (amplifiers) and analog-to-digital converter 1037, which converts image information in the form of analog signals read out from image sensor array 1033 to image information in the form of digital signals, can be associated with image sensor 1032. The image sensor 1032 can also have associated timing and control circuitry 1038 for controlling, for example, the exposure period of the image sensor 1032, the gain applied to the amplifier 1036, and the like. The circuit components 1032, 1036, 1037, and 1038 may be packaged into a common image sensor integrated circuit 1040. Image sensor integrated circuit 1040 may incorporate fewer components than those described above. Image sensor integrated circuit 1040, including image sensor array 1033 and imaging lens assembly 200, may be incorporated into a hand-held housing.

In one example, image sensor integrated circuit 1040 may be provided, for example, by an MT9V022 (752 x 480 pixel array) or MT9V023 (752 x 480 pixel array) image sensor integrated circuit available from Micron Technology company. In one example, image sensor array 1033 can be a hybrid monochrome and color image sensor array having a first subset of monochrome pixels without color filter elements and a second subset of color pixels with color sensitive filter elements. In one example, image sensor integrated circuit 1040 can incorporate a Bayer (Bayer) pattern filter to define red pixels at red pixel locations, green pixels at green pixel locations, and blue pixels at blue pixel locations at image sensor array 1033. A frame provided with such an image sensor array incorporating a bayer pattern may include red pixel values at red pixel locations, green pixel values at green pixel locations, and blue pixel values at blue pixel locations. In embodiments incorporating a bayer pattern image sensor array, processor 1060 prior to subjecting a frame to further processing can utilize green pixel values for interpolation of pixel values at frame pixel positions intermediate of green pixel positions in order to form a monochromatic frame of image data. Alternatively, processor 1060 prior to subjecting a frame to further processing can utilize red pixel values to interpolate pixel values intermediate of red pixel positions in order to form a single color frame of image data. Alternatively, processor 1060 can utilize blue pixel values for interpolation of pixel values in-between blue pixel positions prior to subjecting a frame to further processing. The imaging subsystem of terminal 1000, 1001, 1002 can include image sensor 1032 and plenoptic lens assembly 200 for projecting a plenoptic image onto image sensor array 1033 of image sensor 1032.

In the course of operation of these terminals, image signals may be read out from image sensor 1032, converted, and stored into a system memory (such as RAM 1080). The memory component 1085 of these terminals can include RAM 1080, nonvolatile memory (such as EPROM 1082) and storage memory device 1084 (such as may be provided by flash memory or hard drive memory). In one embodiment, these terminals may include a processor 1060 which can be adapted to read out image data stored in memory 1080 and subject such image data to various image processing algorithms. These terminals may include a direct memory access unit (DMA) 1070 for routing image information read out from image sensor 1032 that has been converted to RAM 1080. In another embodiment, these terminals may employ a system bus (e.g., PCI bus) that provides a bus arbitration mechanism, thus eliminating the need for a central DMA controller. Those skilled in the art will appreciate that other embodiments of the system bus architecture and/or direct memory access components that provide efficient data transfer between the image sensor 1032 and RAM 1080 are within the scope and spirit of the present disclosure.

Referring still to FIG. 14 and to other aspects of the terminal, imaging lens assembly 200 may be adapted to project an image of a decodable indicia 1005 located within a light field or space S (FIG. 11) onto image sensor array 1033.

The terminal may include an illumination subsystem 800 for illumination of a target and projection of an illumination pattern 1260. In the illustrated embodiment, illumination pattern 1260 may be projected approximately to but greater than the area defined by field of view 1240, but may also be projected in an area less than the area defined by field of view 1240. The illumination subsystem 800 may include a light source bank 500 that includes one or more light sources. The light source assembly 800 may further include one or more light source groups, each of which includes, for example, one or more light sources. In an exemplary embodiment, such a light source may illustratively include a Light Emitting Diode (LED). LEDs having any of a variety of wavelengths and filters or combinations of wavelengths or filters may be used in various embodiments. In other embodiments, other types of light sources may also be used. These light sources may be illustratively mounted to a printed circuit board. This may be the same printed circuit board on which image sensor integrated circuit 1040 with image sensor array 1033 is illustratively mounted.

Referring again to fig. 14, the indicia reading terminal 1000, 1001, 1002 can include at least one filter 225 operable to pass illumination reflected from the decodable indicia while suppressing at least some of ambient light reflected off the decodable indicia. For example, plenoptic imaging subsystem 900 may further include at least one filter 225.

These terminals may further include an aiming subsystem 600 for projecting an aiming pattern (not shown). The aiming subsystem 600 may include a light source group 620 and an aiming lens 630. The aiming subsystem 600 may be coupled to an aiming light source group power input unit 1208 via an aiming interface 610 for providing electrical power to the light source group 620 of the aiming subsystem 600. The power input unit 1208 may be coupled to the host system board 1500 (or system bus) via the interface 1108 for communication with the processor 1060.

In one embodiment, illumination subsystem 800 may further include illumination lens assembly 300 in addition to light source bank 500. In addition to or instead of illumination lens assembly 300, illumination subsystem 800 may include alternative light shaping optics, such as one or more diffusers, mirrors, and prisms. In use, these terminals (such as terminals 1000, 1001, and 1002) can be oriented by an operator relative to a target (e.g., a sheet of paper, packaging, another type of substrate, screen, etc.) carrying a decodable indicia 1005 in such a manner that illumination pattern 1260 is projected onto the decodable indicia 1005. In the example of fig. 11, the decodable indicia 1005 is provided by a 1D bar code symbol. The decodable indicia 1005 could also be provided by a 2D bar code symbol or an Optical Character Recognition (OCR) character. The light source bank electric power input unit 1206 may provide energy to the light source bank 500. In one embodiment, the electrical power input unit 1206 may act as a controlled voltage source. In another embodiment, the electric power input unit 1206 may act as a controlled current source. In another embodiment, the electrical power input unit 1206 may act as a combined controlled voltage and controlled current source. The electrical power input unit 1206 may change the level (of the energization level) of the electrical power provided to the light source bank 500, e.g., so as to change the level of the illumination output by the light source bank 500 of the illumination subsystem 800 for generating the illumination pattern 1260.

In another aspect, the terminals may include a power supply 1402 that provides power to a power grid 1404 that may be connected to the electrical components of the terminal 1000. The power supply 1402 may be coupled to various power sources (e.g., battery 1406), a serial interface 1408 (e.g., USB, RS 232), and/or an AC/DC transformer 1410.

Further, with respect to the power input unit 1206, the power input unit 1206 may include a charging capacitor that is continuously charged by the power supply 1402. The power input unit 1206 may be configured to output energy over a range of power-on levels. In the case where the first illumination and exposure control configuration is active, the average power-on level of illumination subsystem 800 during the exposure period may be higher than the average power-on level for which the illumination and exposure control configuration is active.

These terminals may also include a number of peripheral devices including, for example, a trigger 1220 that may be used to activate a trigger signal in order to activate frame readout and/or some decoding process. These terminals may be adapted such that activation of trigger 1220 activates a trigger signal and initiates a decoding attempt. In particular, terminal 1000 can be operative so that, in response to activation of a trigger signal, a succession of frames can be captured by reading out image information (typically in the form of analog signals) from image sensor array 1033 and then storing the image information after conversion into memory component 1080 (which can buffer one or more of the succession of frames at a given time). Processor 1060 can be operative to subject one or more of such succession of frames to a decoding attempt.

For attempting to decode a bar code symbol (e.g., a one-dimensional bar code symbol), processor 1060 can process image data of a frame corresponding to a row of pixel locations (e.g., a row, a column, or a diagonal set of pixel locations) to determine a spatial pattern of light and dark cells and can convert each determined light and dark cell pattern to a character or character string via a table lookup. In the case where the decodable indicia representation is a 2D bar code symbology, the decoding attempt may include the steps of: locating the viewfinder pattern using a feature detection algorithm; positioning a matrix line intersecting the viewfinder pattern according to a predetermined relationship with the viewfinder pattern; determining a pattern of light and dark cells along a matrix line; and converting each bright pattern into a character or character string via a table lookup.

These terminals may include various interface circuits for coupling various peripheral devices to the system addressing/data motherboard 1500 in order to communicate with a processor 1060 also coupled to the motherboard 1500. These terminals may include interface circuitry 1028 for coupling the image sensor timing and control circuitry 1038 to the host system board 1500, interface circuitry 1106 for coupling the illumination source group power input unit 1206 to the host system board 1500, and interface circuitry 1120 for coupling the flip-flop 1220 to the host system board 1500. These terminals may further include a display 1222 coupled to the host system board 1500 and in communication with the processor 1060 via the interface 1122, and a pointer mechanism 1224 in communication with the processor 1060 via the interface 1124 connected to the host system board 1500. These terminals may further include a keyboard 1226 coupled to the host system board 1500 and in communication with the processor 1060 via the interface 1126. These terminals may further include a range detector unit 1210 coupled to the host system board 1500 via an interface 1110. In one embodiment, the range detector unit 1210 may be an acoustic range detector unit. The various interface circuits of these terminals may share circuit components. For example, a common microcontroller may be provided that provides control inputs to the circuit 1038 and to the power input unit 1206 to coordinate timing between the image sensor array control and the illumination subsystem control.

The series of frames of image data that may be captured and subjected to the processing may be full frames (including pixel values corresponding to each pixel of image sensor array 1033 or the maximum number of pixels read out of image sensor array 1033 during operation of these terminals). A series of frames of image data that may be captured and subjected to the process may also be "windowed frames" that include pixel values corresponding to less than a full frame of pixels of image sensor array 1033. The series of frames of image data that may be captured and subjected to the above-described processing may further include a combination of full frames and window frames. The full frame can be read out for capture by selective addressing of pixels of image sensor 1032 having an image sensor array 1033 corresponding to the full frame. The windowed frame can be read out for capture by selectively addressing pixels or pixel ranges of image sensor 1032 having an image sensor array 1033 corresponding to the windowed frame. In one embodiment, a plurality of pixels are subject to addressing and readout to determine the picture size of the frame. Thus, a full frame may be considered to have a first relatively large picture size, and a window frame may be considered to have a relatively small picture size relative to the picture size of the full frame. The picture size of a window frame may vary depending on the number of pixels subject to addressing and readout for capture of the window frame.

These terminals may capture frames of image data at a rate referred to as a frame rate. A typical frame rate is 60 Frames Per Second (FPS), which translates to a frame time (frame period) of 16.6 ms. Another typical frame rate is 30 Frames Per Second (FPS), which translates to a frame time (frame period) of 33.3ms per frame. The frame rate of terminal 1000 can be increased (and the frame time decreased) by a decrease in frame picture size.

Referring to fig. 15A and 15B, an exemplary embodiment of an SMT decoder module assembly 5000 is shown surface mounted to a motherboard 1500 (fig. 15A) and during surface mounting to the motherboard 1500 via reflowable pads 5300 (fig. 15B). In these examples, SMT decoder module assembly 5000 is surface mounted to host system board 1500 by means of image subassembly 900. As can be seen, this process of surface mounted SMT decoder module assembly 5000 differs from the prior art shown in fig. 1A and 1B in that surface mounting of SMT decoder module assembly 5000 does not require any fasteners, flexible PCB cables, board-to-board connectors, the like to connect to host system board 1500.

Referring now to fig. 16-19, a method 6000 of assembling a Surface Mount Technology (SMT) decoder assembly 5000 for an indicia reading device 1000, 10001, 10002 is shown. Method 6000 may include steps for assembling SMT decoder assemblies 5000 in any of the embodiments shown and/or described herein, which may be used in any of the various embodiments of the indicia reading device 1000, 10001, 10002 as shown and/or described herein. The method 6000 may include any known or usual steps for assembling surface mount technology devices. The method 6000 of assembling the SMT decoder component 5000 may generally comprise the steps of:

A step 6100 of providing a double sided main Printed Circuit Board (PCB) 5100 having a top side 5102 configured to receive a processor chip 5200 and a bottom side 5104 having a plurality of reflowable pads 5300 configured for surface mounting to a host system board 1500; and

step 6200 of mounting the processor chip 5200 on the top side of the main PCB 5100.

In an alternative embodiment, the method 6000 of assembling the Surface Mount Technology (SMT) decoder assembly 5000 for the indicia reading device 1000, 10001, 10002 may further comprise a step 6300 of forming cavities 5400 between the plurality of reflowable pads 5300 on the bottom side 5104 of the main PCB 5100. In this embodiment, step 6310 of mounting the other components 5600 on the bottom side 5104 of the main PCB 5100 in the cavity 5400 may be included.

In other alternative embodiments of the method 6000, the step 6300 of forming the cavity 5400 on the bottom side 5104 of the main PCB 5100 may include the step 6310 of providing a solder pad ring PCB 5310 having a plurality of reflowable solder pads 5300, wherein the solder pad ring PCB 5310 is a double-sided ring PCB 5311 having connections 5314 to the main PCB 5100 on the front side 5312 and connections 5318 for the reflowable solder pads 5300 on the back side 5316. In these embodiments, the method 6000 may include a step 6320 of mounting the solder pad ring PCB 5310 on the bottom side 5104 of the main PCB 5100, thereby forming the cavity 5400 on the bottom side 5104 of the main PCB 5100.

Referring to fig. 17A, 17B and 17C, in an alternative embodiment of the method 6000, the step 6310 of providing a solder pad ring PCB 5310 having a plurality of reflowable solder pads 5300 may include the step 6330 of providing tabs 6333 offset from the solder pad ring PCB 5310. As shown in these embodiments, the step 6320 of mounting the solder pad ring PCB 5310 on the bottom side 5104 of the main PCB 5100 may include the steps of: a step 6332 of picking up the pad ring PCB 5310 via the tab 6333 (see fig. 17B); and a step 6334 of placing the solder pad ring PCB 5310 on the main PCB 5100 via the tab 6333. In these embodiments, during assembly, the tab 6333 may be connected between the grommet PCB 5310 and an adjacent grommet PCB 6335, where the two grommet PCBs are placed on the panel 6336 of the main PCB 5100 for assembly.

Referring to fig. 18A, 18B, and 18C, in other alternative embodiments of the method 6000, the step 6320 of mounting the solder pad ring PCB 5310 on the bottom side 5104 of the main PCB 5100 may include the steps of: a step 6340 of picking up the main PCB 5100 (with the processor chip 5200 mounted on the top side 5102 and any other components 5600 mounted on the bottom side 5104); and a step 6342 of placing the main PCB 5100 on the solder pad ring PCB 5310. As shown in these examples, in contrast to the example shown in fig. 17, in this embodiment, the main PCB 5100 is picked up and placed onto the bond pad ring PCB 5310.

Referring now to fig. 19A, 19B, and 19C, in an alternative embodiment of the method 6000, the steps 6340 and 6342 of picking up the primary PCB5100 and placing the primary PCB on the solder pad ring PCB 5310 may include the step 6344 of picking up the primary PCB5100 with the cover 6345 and placing it on the solder pad ring PCB 5310. As shown, the cover 6345 may be configured to be secured on a top side of the main PCB5100 for picking and placing the main PCB 5100. The cap 6345 may be connected to a pin distribution plate ring of the main PCB5100 for easy pick up. The cap 6345 may include a notch 6346 that is used for vent holes during reflow soldering and is also easily removed after SMT. The cover 6345 may be made of LCP material that can transfer SMT temperatures. SMT may be picked up and placed on top of cover 6345.

In other alternative embodiments of the method 6000, the step 6300 of forming the cavity 5400 on the bottom side 5104 of the main PCB5100 may include the step 6350 of providing at least two pad edge PCBs 5320 having a plurality of reflowable pads 5300, wherein the pad edge PCBs 5320 are double-sided edge PCBs 5321 having connections 5324 to the main PCB5100 on the front side 5322 and connections 5328 for the reflowable pads 5300 on the back side 5326. In these embodiments, the method 6000 may include a step 6360 of mounting the pad edge PCB 5320 on the bottom side 5104 of the main PCB5100, thereby forming the cavity 5400 on the bottom side 5104 of the main PCB 5100.

Referring again to fig. 18A, 18B, and 18C, in other alternative embodiments of the method 6000, the step 6360 of mounting the pad edge PCB 5320 on the bottom side 5104 of the main PCB 5100 may include the steps of: a step 6370 of picking up the main PCB 5100 (with the processor chip 5200 mounted on the top side 5102 and any other components 5600 mounted on the bottom side 5104); and a step 6380 of placing the main PCB 5100 on the pad edge PCB 5320.

Referring again to fig. 19A, 19B, and 19C, in an alternative embodiment of the method 6000, the steps 6370 and 6380 of picking up the primary PCB 5100 and placing the primary PCB on the pad edge PCB 5320 may include the step 6390 of picking up the primary PCB 5100 with the cover 6345 (see above) and placing it on the pad edge PCB 5320.

In other alternative embodiments, the method 6000 of assembling the SMT decoder component 5000 for the indicia reading device 1000, 10001, 10002 may further comprise the steps of:

a step 6400 of closing the top side 5102 of the main PCB 5100 around the processor chip 5200 by means of the top seal 5700; and/or

A step 6500 of closing off the cavity 5400 on the bottom side 5102 of the main PCB 5100 between the plurality of reflowable pads 5300 with the bottom seal 5800; and

Step 6600 of providing thermal conduction and/or structural protection to SMT decoder component 5000 via top seal 5700 and/or bottom seal 5800.

To supplement this disclosure, the present application is incorporated by reference in its entirety into the following commonly assigned patents, patent application publications, and patent applications:

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In the description and/or drawings, exemplary embodiments of the invention have been disclosed. The present invention is not limited to such exemplary embodiments. The use of the term "and/or" includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise indicated, certain terms are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A Surface Mount Technology (SMT) decoder assembly for an indicia reading device, comprising:

a double sided main Printed Circuit Board (PCB) having a top side and a bottom side;

a processor chip on the top side of the main PCB;

a plurality of reflowable pads on a perimeter of the bottom side of the main PCB opposite the processor chip on the top side of the main PCB;

a solder pad ring Printed Circuit Board (PCB) having a plurality of connectors stacked on the plurality of reflowable pads on a perimeter of the bottom side of the main PCB; and

Wherein the solder pad ring PCB has a predetermined thickness forming a cavity on the bottom side of the main PCB.

2. An SMT decoder assembly according to claim 1, wherein said cavity is formed to accommodate a plurality of other components including a memory component, an oscillator component and/or a passive component, and wherein said memory component comprises a Dynamic Random Access Memory (DRAM) chip and/or a flash memory chip.

3. The SMT decoder component of claim 1, further comprising: wherein the solder pad ring PCB has a plurality of connectors on a side of the solder pad ring PCB, wherein a plurality of connectors on one side of the solder pad ring PCB are stacked on the plurality of reflowable solder pads, and the plurality of connectors on the other side of the solder pad ring PCB are surface mounted to a host system board of the indicia reading device.

4. The SMT decoder component of claim 3, further comprising: wherein the solder pad ring PCB has a plurality of connectors on at least two sides or four sides of the solder pad ring PCB.

5. The SMT decoder component of claim 1, further comprising: wherein the solder pad ring PCB establishes a connection with another SMT decoder component via a step, and wherein the step is positioned over the solder pad ring PCB via a tab provided on the main PCB.

6. The SMT decoder component of claim 1, further comprising:

a top seal disposed on the top side of the main PCB to cover the processor chip, and

a bottom seal disposed over the cavity formed on the bottom side of the main PCB, the bottom seal covering the bottom side of the main PCB including the other components on the bottom side of the main PCB.

7. An indicia reading device, comprising:

a main system board; and

the Surface Mount Technology (SMT) decoder component of any of claims 1-6, connected to the motherboard, wherein the SMT decoder component is surface mounted to the motherboard.

8. A method of assembling a Surface Mount Technology (SMT) decoder component for an indicia reading device as claimed in any of claims 1-6, comprising the steps of:

providing a double-sided main Printed Circuit Board (PCB) having a top side configured to receive a processor chip and a bottom side having a plurality of reflowable pads configured for surface mounting to a host system board, wherein the plurality of reflowable pads disposed on a perimeter of the bottom side of the main PCB are opposite the processor chip on the top side of the main PCB; and

A solder pad ring Printed Circuit Board (PCB) having a plurality of connectors is stacked on a plurality of reflowable solder pad rings on the periphery of the bottom side of the main PCB, wherein the solder pad ring PCB has a predetermined thickness forming a cavity on the bottom side of the main PCB.