CN116544123A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN116544123A CN116544123A CN202310301629.9A CN202310301629A CN116544123A CN 116544123 A CN116544123 A CN 116544123A CN 202310301629 A CN202310301629 A CN 202310301629A CN 116544123 A CN116544123 A CN 116544123A
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims description 47
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 239000000463 material Substances 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 23
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 14
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 14
- 239000010432 diamond Substances 0.000 claims description 12
- 229910003460 diamond Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 61
- 238000005468 ion implantation Methods 0.000 abstract description 21
- 238000002360 preparation method Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
- H01L21/041—Making n- or p-doped regions
- H01L21/0415—Making n- or p-doped regions using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention relates to a semiconductor device and a preparation method thereof, wherein the preparation method of the semiconductor device comprises the following steps: providing a substrate, forming a bonding stress layer on the back surface of the substrate, forming an ultra-flat sheet layer on one surface of the bonding stress layer far away from the substrate, wherein the thickness of the ultra-flat sheet layer is larger than that of the bonding stress layer, the warping degree of the ultra-flat sheet layer meets the working requirement of a machine, the bonding stress layer counteracts the stress generated by processes such as ion implantation and the like, the back warping caused by the stress is avoided, the ultra-flat sheet layer enables the bonding stress layer not to contact the machine, the influence of machine friction on the bonding stress layer is avoided, the effect of protecting the bonding stress layer is achieved, in addition, the back warping degree of a semiconductor device can meet the working requirement of the machine, the problem that the machine cannot be matched with the semiconductor device to be processed due to the back warping is avoided, the adaption degree of the semiconductor device and the machine is improved, the preparation efficiency and reliability of the semiconductor device are improved, and the product yield and the product performance are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the semiconductor device.
Background
Warpage occurs in the wafer (wafer) during fabrication and when electronic devices and circuits are subsequently fabricated on the wafer. Warpage, also called bending, refers to the phenomenon of wafer deformation and unevenness in the semiconductor field. In the semiconductor manufacturing process, the warpage affects the quality of the wafer and the progress of the semiconductor manufacturing process, for example, if the wafer is deformed in the photolithography process, the illuminated surface of the wafer is uneven, so that a clear image cannot be formed by the mask structure, thereby affecting the etching accuracy.
Taking a silicon nitride (SiC) wafer as an example, after the SiC wafer is subjected to ion implantation with high energy or high dosage, a warpage phenomenon may occur, in a serious case, the warpage may reach more than 200um, and even though the wafer is annealed at a high temperature, the warpage may not be completely repaired, so that a machine station in a subsequent processing technology may not be completely adapted to the wafer, for example, an exposure machine station and an alignment mark measuring machine station, thereby affecting productivity of a production line.
Disclosure of Invention
Based on the above, it is necessary to provide a semiconductor device and a method for manufacturing the same, which counteract the back warpage caused by ion implantation, and the back warpage of the semiconductor device meets the working requirements of a machine, so as to ensure the normal operation of the subsequent process and improve the productivity of the production line.
In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a semiconductor device. The preparation method of the semiconductor device comprises the following steps:
providing a substrate;
forming a bonding stress layer on the back surface of the substrate;
bonding an ultra-flat sheet layer on one surface of the bonding stress layer away from the substrate; the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of a machine.
In one embodiment, before the bonding the ultra-flat sheet layer on the surface of the bonding stress layer away from the substrate, the method for manufacturing the semiconductor device further comprises:
and carrying out surface planarization on the surface of the bonding stress layer far away from the substrate so as to ensure that the warping degree of the surface of the bonding stress layer far away from the substrate meets the preset bonding requirement.
In one embodiment, the method for manufacturing a semiconductor device further includes:
forming a barrier layer on the front surface of the substrate;
etching the barrier layer to form an injection hole on the substrate;
ion implanting the substrate based on the injection hole;
and removing the bonding stress layer and the ultra-flat sheet layer.
In one embodiment, based on the step of removing the ultra-flat sheet, obtaining the ultra-flat sheet, the method for manufacturing the semiconductor device further includes:
and carrying out annealing treatment on the super flat sheet layer with the warpage so that the warpage of the super flat sheet layer after the annealing treatment meets the working requirement of the machine.
According to the preparation method of the semiconductor device, the substrate is provided firstly, then the bonding stress layer is formed on the back surface of the substrate, the super-flat layer is formed on the surface, away from the substrate, of the bonding stress layer, and the three-layer structure of the substrate, the bonding stress layer and the bonding stress layer is formed, which are sequentially stacked from top to bottom, wherein the thickness of the super-flat layer is larger than that of the bonding stress layer.
In another aspect, the present application also provides a semiconductor structure. The semiconductor device includes:
a substrate;
a bonding stress layer located on the back of the substrate;
the ultra-flat sheet layer is positioned on one surface of the bonding stress layer, which is far away from the substrate; the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of a machine.
In one embodiment, the semiconductor device further comprises a barrier layer located on the front side of the substrate.
In one embodiment, the bonding stress layer has a thickness dimension in the range of 10nm to 5 μm.
In one embodiment, the ultra-flat sheet has a thickness dimension in the range of 200 μm to 300 μm.
In one embodiment, the stress layer-bonding material comprises at least one of silicon, silicon carbide, and diamond.
In one embodiment, the ultra-flat sheet of material comprises at least one of silicon oxide, silicon carbide, aluminum nitride, aluminum oxide, silicon nitride, diamond.
The semiconductor device provided by the embodiment comprises a substrate, a bonding stress layer and an ultra-flat layer, wherein the bonding stress layer is positioned on the back of the substrate, the ultra-flat layer is positioned on one surface far away from the substrate, the thickness of the ultra-flat layer is larger than that of the bonding stress layer, the warping degree of the ultra-flat layer meets the working requirements of a machine table, based on the structure, when the processes such as ion implantation and the like are carried out from the front of the substrate, the bonding stress layer counteracts the stress generated by the processes such as the ion implantation and the like, the back warping caused by the stress is avoided, the influence of the back warping to the subsequent process is reduced, the bonding stress layer can not contact the machine table due to the influence of machine table friction to the bonding stress layer, the effect of protecting the bonding stress layer is achieved, the subsequent wafer thinning process can be matched, in addition, the warping degree of the ultra-flat layer meets the working requirements of the machine table, the back warping degree of the semiconductor device can be met, the working requirements of the machine table due to the fact that the back warping is caused by the machine table and the semiconductor device to be processed can not be matched, the product quality is improved, and the product quality of the semiconductor device is guaranteed, and the product quality is improved, and the product quality is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic cross-sectional structure of a semiconductor device after ion implantation;
fig. 2 is a flowchart of a method of manufacturing a semiconductor device provided in an embodiment;
fig. 3a is a schematic cross-sectional structure of the structure obtained in step S201 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 3b is a schematic cross-sectional structure of the structure obtained in step S202 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 3c is a schematic cross-sectional structure of the structure obtained in step S203 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 4 is a flowchart of a method of manufacturing a semiconductor device provided in another embodiment;
fig. 5 is a flowchart of a method of manufacturing a semiconductor device provided in yet another embodiment;
fig. 6a is a schematic cross-sectional structure of the structure obtained in step S504 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 6b is a schematic cross-sectional structure of the structure obtained in step S505 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 6c is a schematic cross-sectional structure of the structure obtained in step S506 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 6d is a schematic cross-sectional structure of the structure obtained in step S507 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 7 is a flowchart of a method of manufacturing a semiconductor device provided in yet another embodiment;
fig. 8a is a schematic cross-sectional structure of the structure obtained in step S702 in the method for manufacturing a semiconductor device according to an embodiment;
fig. 8b is a schematic cross-sectional structure of the structure obtained in step S704 in the method for manufacturing a semiconductor device according to an embodiment.
Reference numerals illustrate:
10-substrate, 20-bonding stress layer, 30-ultra-flat sheet layer, 40-barrier layer, 410-injection hole.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
In SiC device fabrication, an oxide film layer is often grown on the front side of the SiC substrate. As described in the background art, after ion implantation is performed on the SiC substrate, both the implanted layer and the oxide film layer are stacked, which easily causes wafer back warpage, as shown in fig. 1. The wafer with larger back warpage cannot be completely matched with the machine, and the subsequent process cannot be normally performed.
For this, the application provides a semiconductor device and a preparation method thereof, which counteract back warpage caused by ion implantation, and the back warpage of the semiconductor device meets the working requirements of a machine, so that the normal operation of a subsequent process is ensured, and the productivity of a production line is improved.
In one embodiment, a method of fabricating a semiconductor device is provided. As shown in fig. 2, the method of manufacturing the semiconductor device may include the following steps S201 to S203.
S201: a substrate is provided.
Referring to fig. 3a, the substrate 10 may be a warped substrate or a substrate without warpage, which is not limited in this regard. The material of the substrate 10 may be any suitable substrate material, for example at least one of the following mentioned materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and also include multilayer structures composed of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be a Double polished silicon wafer (Double Side PolishedWafers, DSP), or may be a ceramic substrate, quartz, or glass substrate of alumina, or the like, and the present embodiment is not limited thereto.
S202: and forming a bonding stress layer on the back surface of the substrate.
Referring to fig. 3b, the bonding stress layer 20 is located on the back surface of the substrate 10, and in the process of performing ion implantation or the like on the substrate 10 from the front surface, the bonding stress layer 20 can provide support for the substrate 10, counteract stress generated by the ion implantation or the like, and avoid warpage on the back surface of the substrate 10, thereby ensuring normal operation of subsequent processes. The material of the bonding stress layer 20 may be any suitable material, and is not limited herein. The method of forming the bond stress layer 20 may be any suitable plating (deposition) technique, such as an atomic layer deposition (Atomic Layer Deposition, ALD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, or a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process, without limitation.
S203: and bonding the super flat sheet layer on one surface of the bonding stress layer, which is far away from the substrate, wherein the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of the machine.
Referring to fig. 3c, the ultra-flat sheet 30 is located on a surface of the bonding stress layer 20 away from the substrate 10, and the bonding stress layer 20 is located between the substrate 10 and the ultra-flat sheet 30, so that the bonding stress layer 20 is not directly contacted with a machine, the ultra-flat sheet 20 plays a role in protecting the bonding stress layer 20, avoids the influence of machine friction on the bonding stress layer 20, and can cooperate with a subsequent wafer thinning process to reduce the process cost. The material of the ultra-flat sheet 30 may be any suitable material, and is not limited in this regard. The bonding of the ultra-flat sheet 30 may be accomplished using any suitable bonding technique, and the particular bonding process is not limited in any way in the embodiments herein. For example, the ultra-flat sheet may be provided first, and then the ultra-flat sheet and the bonding stress layer 20 may be bonded to form the ultra-flat sheet layer 30 on a side of the bonding stress layer 20 remote from the substrate 10. Wherein the bonding stress layer 20 and the ultra-flat sheet layer 30 constitute a bonded body.
For example, it may be determined which processes to be performed subsequently, and then the wafer warpage requirements of the machine corresponding to the subsequent processes may be determined. Before bonding the ultra-flat sheet layer 30, an annealing treatment process and other processes can be adopted to enable the warping degree of the ultra-flat sheet to be bonded to meet the working requirement of a machine, and then the ultra-flat sheet meeting the working requirement of the machine and the bonding stress layer 20 are bonded to form the ultra-flat sheet layer 30, so that the warping degree of the ultra-flat sheet layer 30 meets the working requirement of the machine, and the normal operation of the subsequent process is ensured.
It will be appreciated that the surface of the ultra-flat sheet 30 away from the bonding stress layer 20 is in contact with the machine, and based on this, the warp of the surface of the ultra-flat sheet 30 away from the bonding stress layer 20 may meet the working requirements of the machine.
Optionally, the hardness of the ultra-flat sheet 30 meets the hardness requirement of the machine, so that the whole semiconductor device can meet the working performance of the machine, the adaptation degree of the semiconductor device and the machine is further improved, the normal operation of the subsequent process is ensured, and the product performance and the product yield are improved. The hardness requirement of the machine is that the semiconductor device to be processed is fed into the machine needs to meet, and can be determined in advance according to the process to be executed and the performance of the machine, without any limitation.
According to the preparation method of the semiconductor device provided by the embodiment, the substrate 10 is provided firstly, then the bonding stress layer 20 is formed on the back surface of the substrate 10, the super-flat layer 30 is formed on the surface, away from the substrate 10, of the bonding stress layer 20, and the three-layer structure of the substrate 10, the bonding stress layer 20 and the bonding stress layer 30, which are sequentially stacked from top to bottom, is formed, wherein the thickness of the super-flat layer 30 is larger than that of the bonding stress layer 20, when the ion implantation and other processes are carried out from the front surface of the substrate 10 based on the structure, the bonding stress layer 20 counteracts the stress generated by the ion implantation and other processes, the back surface warping caused by the stress is avoided, the influence of the back surface warping is reduced, and the bonding stress layer 20 cannot contact a machine table due to the influence of machine table friction on the bonding stress layer 20.
In one embodiment, another method of fabricating a semiconductor device is provided. As shown in fig. 4, the method of manufacturing the semiconductor device may include the following steps S401 to S404.
S401: a substrate is provided.
See fig. 3a and the relevant content of step S201, which are not described herein.
S402: and forming a bonding stress layer on the back surface of the substrate.
See fig. 3b and the related content of step S202, which are not described herein.
S403: and carrying out surface planarization on the surface of the bonding stress layer far away from the substrate so that the warping degree of the surface of the bonding stress layer far away from the substrate meets the preset bonding requirement.
The side of the bonding stress layer 20 remote from the substrate 10 is the lower surface of the bonding stress layer 20. The surface planarization of the bond stress layer 20 may be performed using any suitable planarization technique, such as chemical mechanical polishing (Chemical Mechanical Polishing, CMP) techniques, without limitation. The bonding requirements are predetermined and may be determined according to the bonding technique employed, and are not limited in any way herein.
S404: and bonding the super flat sheet layer on one surface of the bonding stress layer, which is far away from the substrate, wherein the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of the machine.
See fig. 3c and the related content of step S203, which are not described herein.
In the method for manufacturing a semiconductor device provided in the above embodiment, the substrate 10 is provided first, then the bonding stress layer 20 is formed on the back surface of the substrate 10, the surface of the bonding stress layer 20 away from the substrate 10 is planarized, and then the ultra-flat sheet layer 30 is formed on the surface of the bonding stress layer 20 away from the substrate 10. Based on this, before bonding the ultra-flat sheet layer 30 and the bonding stress layer 20, the flatness of the surface, away from the substrate 10, of the bonding stress layer 20, namely, the lower surface is improved, the warpage of the surface, away from the substrate 10, of the bonding stress layer 20 is reduced, the influence of the warpage of the bonding stress layer 20 on the subsequent bonding process is eliminated, the stress is released, the influence on the subsequent bonding ultra-flat sheet layer 30 is reduced, and therefore, the back warpage of the whole wafer is ensured to meet the working requirement of a machine table, and the product performance is further improved.
In one embodiment, a method of fabricating a semiconductor device is also provided. As shown in fig. 5, the method of manufacturing the semiconductor device may include the following steps S501 to S507.
S501: a substrate is provided.
See fig. 3a and the relevant content of step S201, which are not described herein.
S502: and forming a bonding stress layer on the back surface of the substrate.
See fig. 3b and the related content of step S202, which are not described herein.
S503: and forming an ultra-flat sheet layer on one surface of the bonding stress layer, which is far away from the substrate, wherein the thickness of the ultra-flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the ultra-flat sheet layer meets the working requirement of a machine.
See fig. 3c and the related content of step S203, which are not described herein.
S504: a barrier layer is formed on the front side of the substrate.
Referring to fig. 6a, the material of the blocking layer 40 may be any suitable material, for example, may be an oxide, and is not limited herein. The method of forming the barrier layer 40 may employ any suitable plating technique, such as an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a Low Pressure Chemical Vapor Deposition (LPCVD) process, without limitation. Here, the embodiment of the present application forms the barrier layer 40 on the front surface of the substrate 10 using a Chemical Vapor Deposition (CVD) process.
It should be noted that, step S504 may also be performed before step S502, that is, after the substrate 10 is provided, the barrier layer 40 is formed on the front surface of the substrate 10, then the bonding stress layer 20 is formed on the back surface of the substrate 10, and then the ultra-flat sheet layer 30 is formed on the surface of the bonding stress layer 20 away from the substrate 10. The execution sequence of step S504 is not limited here.
S505: the barrier layer is etched to form an injection hole on the substrate.
Referring to fig. 6b, the method of etching the barrier layer 40 may be any suitable etching technique, for example, dry etching or wet etching, which is not limited in this regard. The width dimension of the injection hole 110 may be set according to the requirement of the subsequent ion implantation process, and is not limited herein.
S506: ion implantation is performed on the substrate based on the injection hole. Please refer to fig. 6c.
S507: and removing the bonding stress layer and the ultra-flat sheet layer. Please refer to fig. 6d.
In the method for manufacturing a semiconductor device provided in the above embodiment, the bonding stress layer 20 and the ultra-flat sheet layer 30 are sequentially formed on the back surface of the substrate 10, then the barrier layer 40 is formed on the front surface of the substrate 10, the barrier layer 40 is etched to form the injection hole 410, then the substrate 10 is ion-implanted, and the ultra-flat sheet layer 30 and the bonding stress layer 20 are removed. The method can eliminate the wafer back warping caused by ion implantation, and is not limited by the front barrier layer 40 of the substrate 10, for example, the barrier layer 40 cannot be heated (the situation needs to remove the barrier layer 40 before the warping can be repaired by using a furnace tube heating method), the side wall self-alignment process cannot remove the barrier layer 40 (the situation can not repair the warping by using the furnace tube heating method), the back warping degree of the semiconductor device can meet the working requirement of a machine, the problem that the machine cannot be matched with the semiconductor device to be processed due to the back warping is avoided, the adaptation degree of the semiconductor device and the machine is improved, the normal operation of the subsequent process is ensured, the preparation efficiency of the semiconductor device is improved, and the process cost and the process complexity are reduced.
With continued reference to fig. 5, in one embodiment, after removing the bonding stress layer and the ultra-flat sheet layer based on step S507, the ultra-flat sheet layer may be obtained, and the method for manufacturing a semiconductor device may further include step S508: and (3) carrying out annealing treatment on the super-flat sheet layer with the warpage so that the warpage of the super-flat sheet layer after the annealing treatment meets the working requirement of a machine.
The annealing treatment can repair the warping of the ultra-flat sheet layer in the ion implantation process. The ultra-flat sheets may be annealed using any suitable annealing technique, such as a rapid thermal annealing (Rapid thermal Annealing, RTA) process, without limitation. The warping degree of the super flat sheet after annealing treatment meets the working requirement of a machine, so that the super flat sheet can be recycled, the utilization rate of the super flat sheet is improved, and the process cost is reduced.
Optionally, annealing treatment can be performed on each obtained super flat sheet, so that the step of screening the super flat sheet which is warped and is not warped is omitted, the warping degree of each super flat sheet after annealing treatment can meet the working requirement of a machine, the process treatment process is simplified, the utilization rate of the super flat sheet is improved, and the process cost is reduced.
In one embodiment, the material of the bonding stress layer 20 may be a high temperature resistant material, for example, the temperature range that the high temperature resistant material may withstand may be 600-700 ℃.
In one embodiment, the bonding stress layer 20 may have a thickness ranging from 10nm to 5 μm, such as 100nm, 500nm, 2 μm, 3.5 μm, etc., and may have any other value ranging from 10nm to 5 μm, without limitation. The bonding stress layer 20 is grown on the back side of the substrate 10 to counteract the back side warpage caused by ion implantation.
In one embodiment, the thickness dimension of the ultra-flat sheet 30 may range from 200 μm to 300 μm, such as 225 μm, 250 μm, 280 μm, etc., or any other value between 200 μm and 300 μm, without limitation. By bonding the ultra-flat sheet 30 on the side of the bonding stress layer 20 away from the substrate 10, the back surface flatness of the semiconductor device meets the working performance requirements of the machine.
In one embodiment, the material of the bonding stress layer 20 may include at least one of silicon (Si), silicon carbide (SiC), and diamond, that is, any combination of one or more of silicon, silicon carbide, and diamond.
In one embodiment, the material of the ultra-flat sheet 30 may include silicon oxide (SiO 2 ) Silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al) 2 O 3 ) At least one of silicon nitride (SiN), diamond, that is, any combination of one or more of silicon oxide, silicon carbide, aluminum nitride, aluminum oxide, silicon nitride, and diamond.
For better understanding, another method of fabricating a semiconductor device is provided. As shown in fig. 7, the method of manufacturing the semiconductor device may include the following steps S701 to S710.
S701: a substrate is provided.
Referring to fig. 3a, substrate 10 is a silicon nitride (SiC) substrate.
S702: and forming a barrier layer on the front surface of the substrate by adopting a chemical vapor deposition process.
Referring to fig. 8a, the material of the barrier layer 40 is an oxide.
S703: and carrying out chemical mechanical polishing treatment on the surface of the bonding stress layer, which is far away from the substrate, so that the warping degree of the surface of the bonding stress layer, which is far away from the substrate, meets the preset bonding requirement.
S704: and forming a bonding stress layer on the back surface of the substrate by adopting a chemical vapor deposition process.
Referring to fig. 8b, the material of the bonding stress layer 20 is silicon oxide (SiO 2 ). The bonding stress layer 20 has a thickness dimension in the range of 10nm to 5 μm.
S705: providing an ultra-flat sheet. The material of the ultra-flat sheet is silicon (Si).
S706: bonding the super flat sheet and the bonding stress layer, and forming a super flat sheet layer on one surface of the bonding stress layer far away from the substrate, wherein the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of the machine.
Referring to fig. 6a, the material of the ultra-flat sheet 30 is silicon, and the thickness dimension of the ultra-flat sheet 30 ranges from 200 μm to 300 μm.
S707: the barrier layer is etched to form an injection hole on the substrate. See fig. 6b.
S708: ion implantation is performed on the substrate based on the injection hole. See fig. 6c.
S709: and removing the bonding stress layer and the ultra-flat sheet layer to obtain the ultra-flat sheet layer. See fig. 6d.
S710: and (3) carrying out annealing treatment on the super-flat sheet layer with the warpage so that the warpage of the super-flat sheet layer after the annealing treatment meets the working requirement of a machine.
Compared with a furnace tube heating method, the method provided by the embodiment of the invention has the advantages that the three-layer structure of the substrate 10, the bonding stress layer 20 and the ultra-flat sheet layer 30 which are sequentially stacked from top to bottom is formed, wherein the bonding stress layer 20 counteracts the stress generated by the ion implantation process, the back warping caused by the stress is avoided, the influence of the back warping on the subsequent process is reduced, the ultra-flat sheet layer 30 is positioned on the back of the bonding stress layer 20, the bonding stress layer 20 is protected from being contacted with a machine table, the influence of machine table friction on the bonding stress layer 20 is avoided, the subsequent wafer thinning process can be matched, the wafer preparation cost is reduced, the time consumption is short, the preparation efficiency is high, the film layer on the front side of the substrate 10 is not influenced, the process for eliminating the back warping is not limited by the film layer on the front side of the substrate 10, the application range is expanded, the back warping degree of the semiconductor device can meet the working requirement of a machine table, the problem that the machine table cannot be matched with the semiconductor device to be processed due to the back warping is avoided, the fact that the machine table is matched with the semiconductor device to be processed, the machine table is guaranteed to be matched with the machine table, the process can be recycled, and the process cost can be reduced.
It should be understood that, although the steps in the flowcharts are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in each flowchart may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, a semiconductor device is provided. Referring to fig. 3c, the semiconductor device may include a substrate 10, a bonding stress layer 20, and a super flat sheet 30. Wherein the bond stress layer 20 is located on the back side of the substrate 10. The ultra-flat sheet layer 30 is located on one surface of the bonding stress layer 20 far away from the substrate 10, and the thickness of the ultra-flat sheet layer 30 is larger than that of the bonding stress layer 20, and the warping degree of the ultra-flat sheet layer 30 meets the working requirement of a machine. The bonding stress layer 20 and the ultra-flat sheet layer 30 may be specifically referred to the description related to the preparation method of the semiconductor device provided in the above embodiment, and will not be repeated here.
The semiconductor device provided in the above embodiment includes the substrate 10, the bonding stress layer 20 and the ultra-flat sheet layer 30 stacked sequentially from top to bottom, based on this structure, when the processes such as ion implantation are performed from the front side of the substrate 10, the bonding stress layer 20 counteracts the stress generated by the processes such as ion implantation, so as to avoid the back warpage caused by the stress, reduce the influence of the back warpage on the subsequent process, since the ultra-flat sheet layer 30 is located at the back side of the bonding stress layer 20, the bonding stress layer 20 will not contact the machine, avoid the influence of the machine friction on the bonding stress layer 20, play a role of protecting the bonding stress layer 20, and can also cooperate with the subsequent wafer thinning process, so as to reduce the process cost.
In one embodiment, the hardness of the ultra-flat sheet 30 meets the hardness requirement of the machine, so that the whole semiconductor device can meet the working performance of the machine, the adaptation degree of the semiconductor device and the machine is further improved, the normal operation of the subsequent process is ensured, and the product performance and the product yield are improved. The hardness requirement of the machine is that the semiconductor device to be processed is fed into the machine needs to meet, and can be determined in advance according to the process to be executed and the performance of the machine, without any limitation.
In one embodiment, the semiconductor device may further include a barrier layer 40, where the barrier layer 40 is located on the front surface of the substrate 10. Referring to fig. 6a and the related content of step S504, details are not described herein.
In one embodiment, the bonding stress layer 20 may have a thickness ranging from 10nm to 5 μm, such as 250nm, 800nm, 3 μm, 4.5 μm, etc., and may have any other value ranging from 10nm to 5 μm, without limitation.
In one embodiment, the thickness dimension of the ultra-flat sheet 30 may range from 200 μm to 300 μm, such as 230 μm, 260 μm, 285 μm, etc., or any other value between 200 μm and 300 μm, without limitation.
In one embodiment, the material of the bonding stress layer 20 may include at least one of silicon (Si), silicon carbide (SiC), and diamond, that is, any combination of one or more of silicon, silicon carbide, and diamond.
In one embodiment, the material of the ultra-flat sheet 30 may include silicon oxide (SiO 2 ) Silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al) 2 O 3 ) At least one of silicon nitride (SiN), diamond, that is, any combination of one or more of silicon oxide, silicon carbide, aluminum nitride, aluminum oxide, silicon nitride, and diamond.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a bonding stress layer on the back surface of the substrate;
bonding an ultra-flat sheet layer on one surface of the bonding stress layer away from the substrate; the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of a machine.
2. The method of manufacturing a semiconductor device according to claim 1, wherein before the bonding of the ultra-flat sheet layer to the side of the bonding stress layer remote from the substrate, the method further comprises:
and carrying out surface planarization on one surface of the bonding stress layer far away from the substrate so as to ensure that the warping degree of one surface of the bonding stress layer far away from the substrate meets the preset bonding requirement.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that the method for manufacturing a semiconductor device further comprises:
forming a barrier layer on the front surface of the substrate;
etching the barrier layer to form an injection hole on the substrate;
ion implanting the substrate based on the injection hole;
and removing the bonding stress layer and the ultra-flat sheet layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the ultra-flat sheet is obtained based on the step of removing the ultra-flat sheet, the method for manufacturing a semiconductor device further comprising:
and carrying out annealing treatment on the super flat sheet layer with the warpage so that the warpage of the super flat sheet layer after the annealing treatment meets the working requirement of the machine.
5. A semiconductor device, comprising:
a substrate;
a bonding stress layer located on the back of the substrate;
the ultra-flat sheet layer is positioned on one surface of the bonding stress layer, which is far away from the substrate; the thickness of the super flat sheet layer is larger than that of the bonding stress layer, and the warping degree of the super flat sheet layer meets the working requirement of a machine.
6. The semiconductor device of claim 5, further comprising a barrier layer on a front side of the substrate.
7. The semiconductor device of claim 5, wherein the bonding stress layer has a thickness dimension in the range of 10nm-5 μm.
8. The semiconductor device of claim 5, wherein the ultra-flat sheet layer has a thickness dimension in the range of 200 μm to 300 μm.
9. The semiconductor device of claim 5, wherein the stress layer-bonding material comprises at least one of silicon, silicon carbide, and diamond.
10. The semiconductor device of claim 5, wherein the ultra-flat sheet of material comprises at least one of silicon oxide, silicon carbide, aluminum nitride, aluminum oxide, silicon nitride, diamond.
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