CN116542215A

CN116542215A - Clock tree design method, device, design equipment, storage medium and integrated circuit

Info

Publication number: CN116542215A
Application number: CN202310457253.0A
Authority: CN
Inventors: 姚水音
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2023-04-25
Filing date: 2023-04-25
Publication date: 2023-08-04

Abstract

The embodiment of the application provides a clock tree design method, a device, design equipment, a storage medium and an integrated circuit, wherein the method comprises the following steps: determining a design module to be subjected to clock tree design, wherein the design module comprises a top layer module and a plurality of bottom layer modules called by the top layer module; determining design information of top-level clock ports, wherein the design information comprises design positions of a plurality of top-level clock ports and top-level clock ports associated with each bottom-level module; the top clock end is designed at the boundary of the bottom module, and the overlapping area of the effective coverage area corresponding to the design position of the plurality of top clock ends accords with a preset overlapping condition; according to the top clock ports associated with each bottom module, designing a bottom clock tree on each bottom module; the bottom clock tree of the bottom module is accessed to the top clock tree of the top module through the associated top clock port. According to the embodiment of the application, the redundant circuit of the clock tree design can be reduced, and the performance of the clock tree design is improved.

Description

Clock tree design method, device, design equipment, storage medium and integrated circuit

Technical Field

The embodiment of the application relates to the technical field of integrated circuit design, in particular to a clock tree design method, a clock tree design device, a storage medium and an integrated circuit.

Background

A clock signal (simply referred to as a clock) is used as a sequential logic base of an integrated circuit such as a chip, and plays an important role in performance and operation stability of the integrated circuit, so that a clock design is required in a back-end design of the integrated circuit. Clock design is understood to mean the design of a clock circuit in an integrated circuit implementation.

Clock tree as a type of clock circuit, clock design can be achieved by clock tree design of an integrated circuit. In this context, how to improve the performance of clock tree design is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present application provide a clock tree design method, apparatus, design device, storage medium, and integrated circuit, so as to reduce redundant circuits of the clock tree design, thereby improving the performance of the clock tree design.

In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions.

In a first aspect, an embodiment of the present application provides a clock tree design method, including:

Determining a design module to be subjected to clock tree design, wherein the design module comprises a top layer module and a plurality of bottom layer modules called by the top layer module;

determining design information of top-level clock ports, wherein the design information comprises design positions of a plurality of top-level clock ports and top-level clock ports associated with each bottom-level module; the top clock end is designed at the boundary of the bottom module, and the overlapping area of the effective coverage area corresponding to the design position of the top clock ends accords with a preset overlapping condition;

according to the top clock ports associated with each bottom module, designing a bottom clock tree on each bottom module; the bottom clock tree of the bottom module is accessed to the top clock tree of the top module through the associated top clock port.

In a second aspect, an embodiment of the present application provides a clock tree design apparatus, including:

the design module determining unit is used for determining a design module to be subjected to clock tree design, and the design module comprises a top layer module and a plurality of bottom layer modules called by the top layer module;

the top clock port design unit is used for determining design information of the top clock ports, wherein the design information comprises design positions of a plurality of top clock ports and top clock ports associated with each bottom module; the top clock end is designed at the boundary of the bottom module, and the overlapping area of the effective coverage area corresponding to the design position of the top clock ends accords with a preset overlapping condition;

The bottom clock tree design unit is used for designing a bottom clock tree at each bottom module according to the top clock port associated with each bottom module; the bottom clock tree of the bottom module is accessed to the top clock tree of the top module through the associated top clock port.

In a third aspect, embodiments of the present application provide a design apparatus, including: at least one memory and at least one processor; the memory stores one or more computer-executable instructions that the processor invokes to perform the clock tree design method as described in the first aspect above.

In a fourth aspect, embodiments of the present application provide a storage medium storing one or more computer-executable instructions that, when executed, implement a clock tree design method as described in the first aspect above.

In a fifth aspect, embodiments of the present application provide an integrated circuit, the integrated circuit comprising: a hierarchical design module, configured to design a clock tree based on the clock tree design method described in the first aspect; the clock tree provides clock signals for the design module.

The embodiment of the application provides a top-to-bottom clock tree design method, namely, a top-level clock port is designed with the aim that an overlapping area of an effective coverage area of the top-level clock port meets a preset overlapping condition, so that after the design of the top-level clock port is completed, the design of a bottom-level clock tree is performed in a bottom-level module associated with the top-level clock port based on the top-level clock port. Based on the above, the embodiment of the application can determine the design module to be subjected to clock tree design after the layout planning stage, wherein the design module comprises a top layer module and a plurality of bottom layer modules called by the top layer module; therefore, in the clock design stage, the embodiment of the application can determine the design information of the top clock port, wherein the design information comprises the design positions of a plurality of top clock ports and the top clock ports associated with each bottom module, the top clock port is designed at the boundary of the bottom module, and the overlapping area of the effective coverage area corresponding to the design positions of the plurality of top clock ports accords with a preset overlapping condition; and designing a bottom clock tree at each bottom module according to the top clock ports associated with each bottom module, wherein the bottom clock tree of the bottom module is accessed to the top clock tree of the top module through the associated top clock ports.

According to the embodiment of the application, under the condition that the overlapping condition of the effective coverage area of the top clock port meets the design requirement, the design of the top clock port is carried out, then the bottom clock tree is designed in the related bottom module based on the top clock port, so that the redundant design brought by the overlapping area of the effective coverage area of the top clock port can be reduced, the redundant circuit of the clock tree design is reduced, and the performance of the clock tree design is improved.

Drawings

To more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the embodiments or the prior art will be described below

The drawings that are required for the description are briefly introduced and it is apparent that the drawings in the following description are merely examples of the present application and that other drawings may be obtained from the drawings provided without inventive effort for a person skilled in the art.

FIG. 1A is an exemplary diagram of a hierarchical design of an integrated circuit.

FIG. 1B is another exemplary diagram of a hierarchical design of an integrated circuit.

Fig. 2 is a diagram showing a design example of a design module in an integrated circuit.

Fig. 3 is an exemplary diagram of a clock tree.

Fig. 4 is an example diagram of a clock tree design.

Fig. 5A is an exemplary diagram of the effective coverage of a top level clock port.

Fig. 5B is another example diagram of the effective coverage of the top-level clock port.

Fig. 6 is a flowchart of a clock tree design method according to an embodiment of the present application.

Fig. 7 is a diagram illustrating still another example of the effective coverage area of the top-level clock port according to an embodiment of the present application.

Fig. 8 is another exemplary diagram of a clock tree design provided in an embodiment of the present application.

Fig. 9 is another flowchart of a clock tree design method according to an embodiment of the present application.

Fig. 10 is a block diagram of a clock tree design apparatus according to an embodiment of the present application.

Fig. 11 is a block diagram of a design apparatus provided in an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The integrated circuit design is mainly divided into a front-end design and a back-end design, wherein the back-end design relates to a layout planning stage, a clock design stage and a winding stage. In the layout planning stage of the back-end design, the integrated circuit can be hierarchically designed and divided according to the design requirement, for example, the integrated circuit can be divided into hierarchically designed design modules, and the hierarchically designed design modules comprise a top layer module and a plurality of bottom layer modules called by the top layer module; meanwhile, in the layout planning stage, layout design can be performed on the size, the relative position, the position distribution of devices (such as registers) inside the design module (top module and bottom module) and the like in the integrated circuit. In the clock design stage, the integrated circuit may be clocked, for example, in a clock tree design. The integrated circuit may be circuit-level wound during the winding phase.

For ease of understanding, fig. 1A illustrates an exemplary diagram of a hierarchical design of an integrated circuit, and it is assumed that the hierarchical design of the integrated circuit is divided into two physical implementation levels, such as a top layer and a bottom layer (the bottom layer is also referred to as a block layer), as shown in fig. 1A, the top layer may be designed to be a top layer module 110, the bottom layer may be designed to be a plurality of bottom layer modules, and for ease of illustration, fig. 1A illustrates 3 bottom layer modules 121, 122 and 123, and the actual number of bottom layer modules may be determined according to the actual design situation, which is not limited in this embodiment of the present application. In the hierarchical design of an integrated circuit, a plurality of bottom modules are called by a top module; both the top layer module and the bottom layer module can be regarded as design modules of the integrated circuit, but in the hierarchical design, the top layer module is located at the top layer, the bottom layer module is located at the bottom layer, and the top layer and the bottom layer can be regarded as two physical implementation layers of the hierarchical design.

It should be noted that the layout form of the bottom module shown in fig. 1A is only an example, and other possible layout forms of the bottom module exist in the actual layout planning design of the design module, for example, the bottom module may also be in a top-bottom layout form. By way of example, FIG. 1B illustrates another example diagram of a hierarchical design of an integrated circuit, with an underlying module 121 positioned above underlying modules 122 and 123, and underlying modules 122 and 123 positioned below underlying module 121, as shown in FIG. 1B.

In one example, a design module, such as an IP (intellectual property) module, a plurality of bottom layer modules of the bottom layer and a top layer module of the top layer may form a subsystem in an integrated circuit; in the subsystem, the top layer module invokes a plurality of bottom layer modules, and the plurality of bottom layer modules cooperate to implement the functions of the subsystem.

For a design module (top-level module or bottom-level module) in an integrated circuit, the design module may include one or more registers, and for ease of understanding, fig. 2 exemplarily illustrates a design example diagram of the design module in the integrated circuit, and as shown in fig. 2, the design module may include a plurality of registers 211 to 21n (n is a number of registers in the design module, and may be specific according to actual design situations), where one register may include a D port (data input port), a Q port (data output port), and a CLK port (clock port). It should be further noted that, the design module may have combinational logic in addition to the registers; the output of the combinational logic at any instant depends on the input at that instant and is not related to the original state of the combinational logic; the combinational logic is any one of an arithmetic operation circuit, an encoder, a decoder, a data selector, a data distributor, a numerical comparator, and the like. In one example, the combinational logic may be connected to a data input port, or a data output port, of a register.

Based on the layering design of the integrated circuit, after the top layer layout design is completed in the layout planning stage of the integrated circuit rear end design, each bottom layer module can respectively take the respective module boundary as a boundary to carry out the layout design of devices such as an internal register and the like, so that after each bottom layer module respectively completes the layout design, the layout design result of each bottom layer module can be spliced in the top layer, and the design of the layout planning stage is completed. After the integrated circuit has completed the design of the layout planning stage, a clock design stage may be entered to clock the integrated circuit, such as a clock tree design.

Taking clock tree design as an example, clock tree design is mainly designed for implementation of clock trees in integrated circuits (e.g., design for structures and corresponding implementation circuits of clock trees in integrated circuits). The clock tree (abbreviated as clock tree circuit) is a clock circuit, and is a circuit structure capable of providing a synchronous clock signal for a register in a synchronous circuit design. It should be noted that the synchronous circuit design is a widely used integrated circuit design, in which the integrated circuit

The clocked units are controlled by a unified global clock.

In one example, FIG. 3 illustrates an example diagram of a clock tree, as shown in FIG. 3, that may include a multi-stage structure, and that may include one or more buffers (buffers), where the buffers of the final stage structure are coupled to a clock port (CLK port) of a register to provide a clock signal to the register. In one example, a clock (i.e., a clock signal) starts at the root of a clock tree, propagates through the multi-stage structure of the clock tree, and accesses the clock port of a register through the buffers of the final stage structure, thereby providing the clock signal to the register. The root of the clock tree may be considered the clock source of the clock tree, e.g., the root position of the clock tree may be considered the clock source position; the buffer access register in the final stage structure of the clock tree can be considered as the clock end point of the clock tree. In integrated circuits of hierarchical design, the root of the clock tree may be located at the top module and the clock end of the clock tree may be connected to registers of the bottom module.

In a possible implementation, the clock tree may have a plurality of roots, different roots corresponding to different clocks, such that one clock may access a clock port of a register through a final stage structure in the multi-stage structure under the corresponding root, and the clock port of the register may switch between different clocks by switching a buffer connecting the final stage structure in the multi-stage structure under the different root.

It should be noted that the multi-stage structure of the clock tree may form a tree circuit structure based on a root, but the tree circuit structure is only an alternative circuit structure of the clock tree, and the clock tree may be other circuit structures. In one example, the clock tree may also be a grid-like circuit structure, such as where each stage of the clock tree forms a grid and the stages are connected by one or more buffers, with the buffer of the last stage being connected to the clock port of the register.

One way for electronic design aids to implement clock tree design is CTS (Clock Tree Synthesis ), which is a means of designing clock tree circuits for integrated circuits through electronic design aids. For example, after the electronic design auxiliary tool completes the layout planning design of the integrated circuit, in the case that the register position distribution of the design module (related to the top layer module and the bottom layer module) is determined, the electronic design auxiliary tool can comprehensively analyze the register position distribution, the clock source position, the clock tree quality requirement and the like of the design module, so as to design the topology structure of the clock tree and the corresponding circuit implementation, and realize the clock tree design based on CTS.

In integrated circuits with hierarchical designs, the CTS-based clock tree design may be divided into a top-level clock tree design and a bottom-level clock tree design, where the bottom-level clock tree design is mainly a clock tree design inside the bottom-level module. One implementation of the clock tree design may be a bottom-to-top clock tree design, with the top and bottom clock tree designs being distinguished. For example, firstly, clock tree design is carried out in the bottom layer module to finish the clock tree design in the bottom layer module; then designing a top clock port at the boundary of the bottom module, and designing a top clock tree at the top module; and the clock tree design in the bottom module is accessed into the clock tree design at the top layer through the clock port at the top layer, so that the clock tree design from bottom to top is completed.

For ease of understanding, fig. 4 illustrates an exemplary diagram of a clock tree design, and in conjunction with fig. 4, in a bottom-to-top clock tree design, the clock tree design may be first performed inside the bottom module, with the module boundary of the bottom module as a boundary, for example, inside the bottom module, and the design of the multi-stage structure of the clock tree may be performed according to the register location distribution inside the bottom module. After the clock tree design inside the bottom layer module is completed, the position of the top layer clock port can be designed at the boundary of the bottom layer module; and, the clock tree design of the top layer is carried out on the top layer module; the bottom clock tree inside the bottom module can be connected to the top clock tree of the top design through the top clock ports located at the boundaries of the bottom module.

For ease of illustration, the clock tree within the bottom module may be referred to as the bottom clock tree, and the top clock tree may be considered the clock tree designed in the top module. From the perspective of the top module and the bottom module, the root of the clock tree may be located in the top module, and the bottom clock tree inside the bottom module may be considered as a sub-structure of the top clock tree. It should be noted that, the top-level clock port may be regarded as a port connected to the top-level clock tree on the boundary of the bottom-level module.

In synchronous circuit design, the design difficulty, complexity of the clock design is related to the design requirements of the clock signal, such as clock coverage, quality requirements for the clock signal during clock use, quality requirements for the respective clock delay between different registers where there is a timing check requirement, quality requirements for clock skew, quality requirements for clock OCV (On chip variation, on-chip variation), etc. OCV is a circuit whose pointer pair has a logical relationship and appears in the same timing path, and device characteristic variation due to uncertainty of production process may appear as device timing characteristic variation.

Therefore, when designing the clock tree of the integrated circuit based on the CTS, the clock tree design needs to be performed by integrating the clock tree quality requirements. The clock tree quality requirements may include clock tree design requirements and clock tree design metrics. In performing the clock tree design, the clock tree design metrics such as clock frequency, signal duty cycle, signal variation delay, clock offset, etc.

For clock delay in the clock tree design index, the clock delay refers to signal delay from a clock source to a clock destination of a clock, and the clock destination of a clock circuit can be connected with a clock port of a register so as to provide a clock signal for the clock port of the register. For example, the clock delay of a clock tree may be considered as the signal delay of a clock from the clock source to the clock destination of the clock tree; i.e. the signal delay of the clock from the root of the clock tree to the buffers of the final structure, which may be connected to the clock ports of the registers.

For clock offset in the clock tree design index, the clock offset refers to the difference of clock delays corresponding to different clock endpoints. For example, the clock skew of a clock tree may be considered as the difference in clock delays corresponding to different clock endpoints in the clock tree; i.e. the difference in clock delays for the different buffers of the final stage structure in the clock tree.

Based on the clock delay in the clock tree design index, under the condition of distinguishing the top-layer clock tree design and the bottom-layer clock tree design, the clock delay of the clock port of any register in the bottom-layer module can be: the top clock delay of the clock port plus the bottom clock delay.

The bottom clock delay can be regarded as the clock delay of a bottom clock tree in the bottom module, and is related to the length of the bottom clock tree in the bottom module, and the length of the bottom clock tree is related to the number of buffer levels of the bottom clock tree; that is, the bottom clock delay of a clock port of a register is the clock delay of the clock port inside the bottom module, e.g., the delay of the top clock port of the bottom module to the clock port of the register. The top-level clock delay may be considered as the clock delay from the root of the clock tree to the top-level clock port of the bottom-level module, where the root of the clock tree is the root of the clock tree of the bottom-level and top-level whole, and is located at the top level.

As shown in connection with fig. 4, the clock delay of the clock port of the register in the bottom module may be: the root of the clock tree is the clock delay of the top clock port (i.e., the top clock delay) +the clock delay of the top clock port to the clock port of the register (i.e., the bottom clock delay).

Assuming that the clock delays are balanced on the top layer, for example, the top layer clock delays of the clock ports of the bottom layer respective registers are balanced, so that the top layer clock delays of the clock ports of the bottom layer respective registers may be regarded as being approximately equal, such as taking the bottom layer modules 121, 122, and 123 illustrated in fig. 1A and 1B as an example, the top layer clock delay of the clock port of the design module 121=the top layer clock delay of the clock port of the design module 122=the top layer clock delay of the clock port of the design module 123.

In the case where the top clock delays tend to be equal, the overall clock delay of the integrated circuit depends on the bottom clock delay of the clock port, that is, the balance of the bottom clock delay of the clock port of the register is a major factor affecting the balance of the overall clock delay of the integrated circuit.

Therefore, in order to ensure the balance of the overall clock delay of the integrated circuit, the bottom clock delays of the clock ports of different registers need to be balanced, so that the delays of clock signals obtained by the clock ports of different registers tend to be consistent; for example, given a desired clock delay, the delay of clock signals obtained by clock ports of different registers should be made not to exceed the desired clock delay. Where different registers are such as registers of different underlying modules and different registers within the underlying modules.

Based on this, for the underlying clock tree of the internal design of each underlying module, the underlying clock delay depends on the following factors:

bottom clock latency = func (register distribution); that is, the lower-level clock delay is positively correlated with the register distribution of the lower-level module, and the more distributed the register distribution of the lower-level module is, the greater the lower-level clock delay is.

Therefore, when the balance processing of the bottom clock delay is carried out on the clock ports of the registers of the bottom module, the number of the buffers or the inverters on the bottom clock tree in the bottom module can be adjusted based on the physical size of the bottom module and the distribution of the registers of the bottom module, and the device driving capability of the bottom clock tree is adjusted, so that the clock ports of different registers (the clock ports of the registers of different bottom modules and the clock ports of different registers in the bottom module) acquire the delay trend of the clock signal to be consistent at the bottom, and the balance processing of the bottom clock delay of the clock ports of different registers is realized.

The top-level clock port has an active coverage area (active coverage area is also referred to as active coverage area) for the top-level clock port, based on the expected clock delay of the clock design indicator. That is, given the expected clock delay, the maximum area that the top clock port can cover and affect at the bottom clock tree length corresponding to the bottom layer can be used as the effective coverage area of the top clock port. The length of the bottom clock tree corresponding to the top clock port at the bottom is related to the number of the levels of the bottom clock tree, and corresponds to the bottom clock delay. If the effective coverage area of the top clock port is larger, the length of the bottom clock tree corresponding to the bottom layer of the top clock port is longer, the levels of the bottom clock tree are more, and accordingly the bottom clock delay is larger.

It should be noted that, given the expected clock delay, the effective coverage of the top-level clock port should be determined, if the coverage of the top-level clock port exceeds the effective coverage, the bottom-level clock delay exceeds the bottom-level clock delay that needs to be balanced, and accordingly, the clock delay (top-level clock delay plus bottom-level clock delay) of the clock port of the register exceeds the expected clock delay; and the clock delay of the clock port of the register exceeds the expected clock delay, which causes excessive clock offset of the integrated circuit and affects timing convergence. The effective coverage of the top clock port can be determined by the overall energy efficiency requirement and the actual process performance of the design when the clock delay is expected, and the excessive or insufficient effective coverage of the top clock port may cause problems in efficiency and energy consumption of the integrated circuit.

For convenience of illustration, taking the bottom module shown in fig. 1A as an example, fig. 5A illustrates an example diagram showing an effective coverage area of a top clock port, and it should be noted that, based on the content of the effective coverage area of the top clock port described in the embodiment of the present application, the effective coverage area of the top clock port of the bottom module shown in fig. 1B may be correspondingly derived, so that the embodiment of the present application illustrates the top clock port of the bottom module shown in fig. 1A, and does not expand the effective coverage area of the top clock port of the bottom module shown in fig. 1B.

As shown in fig. 5A, the effective coverage of the top clock port is represented by a dashed box, and the effective coverage of the top clock port 511 of the bottom module 121 is 51 when the clock delay is expected; for example, at an expected clock delay, the length of the corresponding bottom clock tree of top clock port 511 within bottom module 121 may cover an integrated circuit area of 51; the effective coverage of the top clock port 512 of the bottom module 122 is 52 and the effective coverage of the top clock port 513 of the bottom module 123 is 53 at the expected clock delay.

It should be noted that, the top clock port is disposed at the boundary of the bottom module and is used for connecting the top clock tree of the top layer, and the top clock port is not disposed in the bottom module; that is, the top clock port 511 is disposed at the boundary of the bottom module 121, rather than being disposed inside the bottom module 121, and similarly, the top clock port 512 is disposed at the boundary of the bottom module 122 and the top clock port 513 is disposed at the boundary of the bottom module 123. Fig. 5A is an illustration of the effective coverage of the top-level clock port from a timing perspective, rather than from a physical logic perspective, and therefore, fig. 5A centers the top-level clock port in the effective coverage to illustrate the effective coverage from a timing perspective.

It should be further noted that, the configuration of the effective coverage of the top-level clock port is not limited, and fig. 5A is an example of the effective coverage in a rectangular configuration for convenience of illustration, but the specific configuration of the effective coverage may be according to practical situations.

It can be seen that the effective coverage of the top clock port 512 can substantially cover the area of the bottom module 122, and the effective coverage of the top clock port 513 can cover the area of the bottom module 123; the area of the bottom module 121 is larger, and the effective coverage area of the top clock port 511 cannot cover the area of the bottom module 121, which makes the devices such as the register with larger area in the bottom module 121 not covered by the clock signal, resulting in an increase of the bottom clock delay of the bottom module 121. Thus, in the example of FIG. 5A, the bottom clock delay of bottom module 121 will be much greater than the bottom clock delays of bottom module 122 and bottom module 123, which will have an adverse effect on timing closure.

Considering the balance of the bottom clock delay, for the situation that the effective coverage area of a single top clock port of the bottom module cannot cover the bottom module, the number of the top clock ports can be increased at the boundary of the bottom module during clock tree design, so that the area of the bottom module covered by the effective coverage area of the top clock ports is increased, and the effect of balancing the bottom clock delay among the bottom modules is achieved.

By way of example, fig. 5B illustrates another exemplary diagram of the effective coverage of the top-level clock ports, and in conjunction with fig. 5A and 5B, based on the fact that the effective coverage of a single top-level clock port 511 of the bottom-level module 121 cannot cover the area of the bottom-level module 121, and given the expected clock delay, the effective coverage of the top-level clock port cannot be too large or too small (the effective coverage of the top-level clock port is too large or too small may cause problems in efficiency and energy consumption of the integrated circuit), so the position of the top-level clock port 511 can be adjusted on the boundary of the bottom-level module 121, and the top-level clock port 514 is added, and the effective coverage of the top-level clock port 514 is 54, considering the balance of the bottom-level clock delay among the bottom-level modules 121, 122, and 123; thus, the bottom module 121 may substantially cover the area of the bottom module 121 through the effective coverage area 51 of the top clock port 511 and the effective coverage area 54 of the top clock port 514, so as to balance the bottom clock delay of the bottom module 121, so that the bottom clock delays among the bottom modules 121, 122 and 123 tend to be balanced. Thus, in the case where the top-level clock delays of the bottom-level modules 121, 122, and 123 are designed to be approximately equal, the overall clock delays of the integrated circuits can be made to be approximately balanced based on the balancing process of the bottom-level clock delays of the bottom-level modules 121, 122, and 123.

However, due to the effect of the execution efficiency of the electronic design aid, when the PnR design (circuit placement and wire winding design) is performed on the integrated circuit such as a chip, the integrated circuit is divided into design modules (e.g., a top module and a plurality of bottom modules called by the top module) of hierarchical design, and the PnR design is performed in units of the design modules, which results in clock tree designs between the design modules being independent of each other and not related to each other. The PnR is a process of carrying out actual circuit deployment and optimization on a circuit and interconnection relation in a gate-level circuit netlist by combining an actual physical realization scene through an electronic design auxiliary tool, and relates to processes of circuit placement, clock design, winding and the like; the clock design (e.g., clock tree design) may be a step performed after the placement of the circuits of the PnR design, before winding.

Based on this, in the bottom-to-top clock tree design, each bottom module independently designs the bottom clock tree, and then independently designs the top clock port at the boundary of each bottom module, and due to layout limitation of the bottom modules and no consideration of the peripheral situation of the bottom modules, there may be an overlapping area in the effective coverage of the top clock port of each bottom module, which leads to redundant design of the clock tree circuit. It should be explained that, when the effective coverage area of the top clock port has an overlapping area, it is indicated that the top clock port has overlapping in the maximum area that can be covered and affected by the bottom clock tree length corresponding to the bottom layer, and there are top clock ports and bottom clock trees with redundant designs.

As shown in connection with fig. 5B, the effective coverage area 51 of the top-level clock port 511 and the effective coverage area 54 of the top-level clock port 514 have an overlapping area 501, the effective coverage area 54 of the top-level clock port 514 and the effective coverage area 52 of the top-level clock port 512 have an overlapping area 502, the effective coverage area 52 of the top-level clock port 512 and the effective coverage area 53 of the top-level clock port 513 have an overlapping area 503, and these overlapping areas result in the existence of redundant circuits in the clock tree design, thereby resulting in the redundant design of the clock tree circuit.

It can be seen that, when considering the balance of clock delay, if the clock tree design is based on the bottom-to-top clock tree design manner, the clock tree designs of the design modules are independent and not related to each other, which may cause the following problems:

the clock tree designs among the design modules are mutually independent (the bottom clock tree design of the bottom module and the top clock tree design of the top module are mutually independent), so that a clock tree circuit with redundant design (for example, a redundant circuit corresponding to an overlapping area of an effective coverage area shown in fig. 5B) possibly exists, and the designed clock tree circuit has the situation that the area of an integrated circuit is unreasonably occupied, and the area of the integrated circuit is excessively occupied, so that the problems of increased cost of the integrated circuit, influence on energy consumption of the integrated circuit and the like are possibly caused;

Further, the clock tree designs among the design modules are mutually independent, so that the complexity of the top clock tree circuit of the top module is increased, and the top clock tree circuit with the complex top module occupies more integrated circuit area, influences the cost of the integrated circuit and increases the energy consumption of the integrated circuit;

furthermore, the clock tree designs between the Design modules are independent, which is not friendly to DFT (Design For Test) and increases Design complexity, for example, each Design module needs to perform independent DFT clock processing; wherein DFT refers to adding a special circuit design used for functional testing of an integrated circuit to the integrated circuit design;

furthermore, the clock tree designs between the design modules are independent, so that the common path (common path) of the clock tree circuits between the design modules is reduced, thereby increasing the OCV degradation probability of the clock tree circuits and being unfavorable for the timing convergence of integrated circuits such as chips.

Based on this, the embodiments of the present application provide an improved clock design scheme to reduce redundant circuits of a clock tree design by a top-to-bottom clock tree design scheme, taking into account the balance of clock delays of an integrated circuit, thereby optimizing the performance of the clock tree design.

As an alternative implementation, top-to-bottom clock tree design can be understood as that the design of the top clock port is first performed at the boundary of the bottom module based on the area, the phase position and the effective coverage of the top clock port of the bottom modules, and

the overlapping area of the effective coverage of the designed top-level clock port is made to conform to a preset overlapping condition (the preset overlapping condition is, for example, the overlapping area is minimized, or the overlapping area under consideration of a timing condition and a power consumption condition is minimized); therefore, after the design of the top clock port is completed, the embodiment of the application can design the bottom clock tree in each bottom module according to the top clock port associated with each bottom module; furthermore, the bottom clock tree of the bottom module can be connected with the top clock tree of the top module through the associated top clock port, so that the clock tree design is completed.

Because the embodiment of the application designs the top clock port based on the area and the phase position of the bottom module and the effective coverage area of the top clock port under the condition of setting the preset overlapping condition, the overlapping area of the effective coverage area of the top clock port accords with the preset overlapping condition, so that the overlapping condition of the effective coverage area of the top clock port accords with the design requirement, and the redundant design brought by the overlapping area of the effective coverage area of the top clock port is reduced. Furthermore, the bottom clock tree is designed at each bottom module according to the top clock ports associated with each bottom module, so that the situation that the bottom clock tree is designed by multiplexing the same top clock ports possibly exists among the bottom modules, and the redundant design of the clock tree design is reduced.

In order to facilitate understanding of the top-to-bottom clock tree design scheme provided in the embodiments of the present application, as an optional implementation, fig. 6 schematically illustrates an optional flowchart of a clock tree design method provided in the embodiments of the present application, where the method flowchart may be implemented by a design apparatus, and the design apparatus may perform integrated circuit design through an electronic design auxiliary tool, and in the embodiments of the present application, a clock tree design manner may be improved in a back-end design process (for example, in a PnR design process) of the electronic design auxiliary tool, so as to reduce redundant design of the clock tree design. Referring to fig. 6, the method flow may include the following steps.

In step S610, a design module to be designed for a clock tree is determined, where the design module includes a top module and a plurality of bottom modules called by the top module.

After the design of the layout planning stage is completed on the integrated circuit, the embodiment of the application can determine the design module to be subjected to clock tree design, and the design module to be subjected to clock tree design can comprise a top layer module and a plurality of bottom layer modules called by the top layer module based on the hierarchical design of the design module.

Optionally, in a layout planning stage, the embodiment of the application may utilize electronic design assistance to perform layout planning and design of the integrated circuit, so as to obtain layout planning information of the design module for the design module of the integrated circuit hierarchical design. The design module based on hierarchical design comprises a top layer module and a plurality of bottom layer modules called by the top layer module, and in a layout planning stage, the embodiment of the application can plan and design the relative positions of the bottom layer modules, for example, plan and design the relative positions of the bottom layer modules in the global of the integrated circuit, so that the layout planning information of the design module can at least comprise the relative positions of the bottom layer modules for the design module of hierarchical design. In a further optional implementation, in the layout planning stage, the embodiment of the application may also plan and design information such as a size (e.g. an area) of the design module.

In step S611, design information of the top-level clock ports is determined, where the design information includes design positions of the plurality of top-level clock ports and top-level clock ports associated with the bottom-level modules; wherein the top clock end is designed on the bottom module

And the overlapping areas of the effective coverage areas corresponding to the top-layer clock ports at the design positions meet preset overlapping conditions.

After the design of the layout planning stage is completed, the embodiment of the application can perform top-to-bottom clock tree design, so that the design positions of the top clock ports and the top clock ports associated with the bottom modules are designed at the boundaries of the bottom modules, and the design information of the top clock ports is obtained. Alternatively, the embodiment of the application may design the top-level clock port after the design of the top-level clock tree is completed.

When designing design positions of a plurality of top-level clock ports, the design targets of the embodiment of the application are as follows: and under the condition of expected clock delay of a given clock tree, enabling an overlapping area of the effective coverage range of the top-level clock port to meet a preset overlapping condition. Further, in addition to considering the timing condition, the embodiments of the present application may also consider the power consumption condition of the integrated circuit, for example, the design objective may be: and under the conditions of expected clock delay of a given clock tree and power consumption of an integrated circuit, enabling an overlapping area of the effective coverage range of the top-level clock port to meet a preset overlapping condition.

Alternatively, the preset overlap condition may be a degree to which an overlap region of an effective coverage of the top-level clock port can be designed to be accepted, for example, an area of the overlap region of the effective coverage of the top-level clock port is minimized. Therefore, when determining the design positions of the top-level clock ports, the area of the overlapping area of the effective coverage area corresponding to the design positions of the top-level clock ports is minimized.

It should be noted that, according to the design requirement, the embodiment of the present application may consider the specific content of the preset overlapping condition, which is not limited. In other possible examples, the embodiments of the present application may set an area threshold that may be allowed by the overlapping area of the effective coverage area of the top-level clock port given the expected clock delay of the clock tree and the power consumption condition of the integrated circuit, so that when the area of the overlapping area of the effective coverage area of the top-level clock port is not greater than the area threshold, the preset overlapping condition is considered to be met. It should be noted that, in the case where the timing and power consumption requirements of the integrated circuit are satisfied, the embodiment of the present application may pursue that the area of the overlapping area of the effective coverage area of the top-level clock port is minimized.

As an optional implementation, when designing the positions of the top-level clock ports, in order to achieve the design goal that the overlapping area of the effective coverage area of the top-level clock ports meets the preset overlapping condition, the design positions of the top-level clock ports may be determined at least according to the area of each bottom-level module, the relative positions of each bottom-level module, and the effective coverage area of the top-level clock ports; the area of each bottom layer module and the relative position of each bottom layer module are determined according to the layout planning information of the design module.

For example, the present application may determine the design locations of the plurality of top-level clock ports based at least on the area of each bottom-level module, the relative location of each bottom-level module, and the effective coverage of the top-level clock ports. That is, in combination with the effective coverage area of the top-layer clock port and the area and the relative position of each bottom-layer module, the embodiment of the present application targets that the overlapping area of the effective coverage area of the top-layer clock port meets the preset overlapping condition (for example, the area of the overlapping area is minimized as a target), and determines the design position of the top-layer clock port at the boundary of the bottom-layer module.

Alternatively, the effective coverage of the top-level clock port may be the expected effective coverage of the top-level clock port, where

Given the expected clock delay of the clock tree, if the clock delay of the top clock tree is balanced, the length of the bottom clock tree corresponding to the top clock port at the bottom layer should be determined, that is, the effective coverage of the top clock port should be determined.

In some embodiments, the electronic design assistance tool may provide a clock tree design page, based on the area of each bottom module designed in the layout planning stage and the relative position of each bottom module, the electronic design assistance tool may present a plurality of bottom modules in the clock tree design page; therefore, a designer can consider the effective coverage area of the top clock port, the area and the relative position of each bottom module, and design the position of the top clock port on the boundary of the bottom module on a clock tree design page; based on the design operation of the designer on the top clock port, the clock tree design page can display the display effect of the effective coverage area of the top clock port; furthermore, the designer can continuously adjust the design position of the top clock port through the display effect displayed by the clock tree design page, so that the overlapping area of the effective coverage area of the top clock port meets the preset overlapping condition. When a designer confirms that the design operation is completed (for example, the designer confirms that the design of the top-level clock port achieves the design goal, and can confirm that the design operation is completed), the embodiment of the application can determine the design information corresponding to the design operation of the top-level clock port as the final design information of the top-level clock port, thereby determining the design positions of a plurality of top-level clock ports and the top-level clock ports associated with each bottom-level module.

That is, in an alternative implementation, a designer may design the position of the top-level clock port on the boundary of the bottom-level module in combination with the effective coverage area of the top-level clock port and the area and the relative position of each bottom-level module based on the effect display of the electronic design assistance tool on the design operation, and make the overlapping area of the effective coverage area of the top-level clock port meet the preset overlapping condition.

Unlike the bottom-to-top clock tree design, which requires independent design of the top-level clock port at each bottom-level module, embodiments of the present application may not implement the top-level clock port design at each bottom-level module. For example, if the area of a certain bottom layer module can be covered by the effective coverage area of the top layer clock port designed by the adjacent bottom layer module, the bottom layer module may not design the top layer clock port, but may multiplex the top layer clock ports designed by the adjacent bottom layer module to design the bottom layer clock tree.

Based on this, the top-level clock port associated with the bottom-level module according to the embodiment of the present application may include the following cases: if the boundary of the bottom layer module is designed with a top layer clock port, the top layer clock port associated with the bottom layer module is at least the top layer clock port designed by the boundary of the bottom layer module; if the boundary of the bottom layer module is not designed with the top layer clock port, the top layer clock port associated with the bottom layer module is designed on the boundary of the adjacent bottom layer module and effectively covers the top layer clock port of the bottom layer module.

As an alternative implementation, in determining the design location of the top-level clock port, embodiments of the present application may consider the following design strategy:

for any current bottom layer module, if the area of the current bottom layer module is smaller than a preset area, the preset area is smaller than the effective coverage area of a single top layer clock port (the preset area can be set according to actual design conditions), the design positions of the top layer clock ports of the adjacent bottom layer modules of the current bottom layer module are adjusted, so that the effective coverage area of the top layer clock ports of the adjacent bottom layer modules is located in the part of the current bottom layer module, the current bottom layer module can be covered, and the top layer clock ports are not designed at the boundary of the current bottom layer module. Where a portion referred to herein may be considered as a range (e.g., area) of an underlying module covered by the effective coverage of the top clock port of an adjacent underlying module.

That is, for the bottom layer module with a smaller area, the embodiment of the application considers that the top layer clock port is not designed at the boundary of the bottom layer module, but the design position of the top layer clock port of the adjacent bottom layer module is adjusted, so that the effective coverage area of the top layer clock port of the adjacent bottom layer module is located at the part of the bottom layer module, and the bottom layer module can be covered, so that the bottom layer module with a smaller area can not design the top layer clock port, but reuse the top layer clock port of the adjacent bottom layer module.

After the design positions of the top clock ports of the adjacent bottom modules of the bottom modules are adjusted, the effective coverage area of the top clock ports of the adjacent bottom modules can cover the bottom modules, but the condition that the effective coverage area of the top clock ports of the adjacent bottom modules cannot cover the area of the bottom modules may exist. That is, for the case where the boundary of the bottom layer module is designed with the top layer clock port, the top layer clock port designed by the boundary of the bottom layer module may be able to cover the area of the bottom layer module, or may not be able to cover the area of the bottom layer module.

Based on the above, if the boundary of the bottom module is designed with the top clock port, and the effective coverage area of the top clock port designed by the boundary of the bottom module can cover the bottom module, the top clock port associated with the bottom module is the top clock port designed by the boundary of the bottom module;

if the boundary of the bottom layer module is designed with a top layer clock port, but the effective coverage area of the top layer clock port designed by the boundary of the bottom layer module cannot cover part of the area of the bottom layer module, the top layer clock port associated with the bottom layer module is as follows: the boundary of the bottom layer module is designed with a top layer clock port and the top layer clock port is designed on the adjacent bottom layer module and covers the partial area in an effective coverage range.

Taking the bottom layer module shown in fig. 1A as an example for convenience of illustration, fig. 7 illustrates still another example diagram of the effective coverage area of the top layer clock port provided by the embodiment of the present application, assuming that the area of the bottom layer module 123 is smaller (for example, the area of the bottom layer module 123 is smaller than the preset area), and the bottom layer module 122 is an adjacent bottom layer module of the bottom layer module 123, the embodiment of the present application may not set the top layer clock port at the boundary of the bottom layer module 123, but adjust the design position of the top layer clock port 512 of the bottom layer module 122, so that the portion of the effective coverage area of the top layer clock port 512 of the bottom layer module 122 located in the bottom layer module 123 can cover the bottom layer module 123. The top-level clock port associated with the bottom-level module 123 may thus be the top-level clock port 512 designed in the bottom-level module 122.

Because the design position of the top clock port 512 of the bottom module 122 is adjusted, the effective coverage area of the top clock port 512 may not cover the area of the bottom module 122, and at this time, the design position of the top clock port 514 of the adjacent bottom module 121 of the bottom module 122 may be adjusted, so that the effective coverage area of the top clock port 512 may not cover a part of the area of the bottom module 122 and may be covered by the effective coverage area of the top clock port 514; thus, the top-level clock ports associated with the bottom-level module 122 may be top-level clock ports 512 designed for the bottom-level module 122 and top-level clock ports 514 designed for the adjacent bottom-level module 121. It should be noted that, if the design position of the top clock port 512 of the bottom module 122 is adjusted, the effective coverage area of the top clock port 512 can still cover the area of the bottom module 122, the bottom module 122 does not need to multiplex the top clock ports of the adjacent bottom modules, and at this time, the associated top clock port of the bottom module 122 may be the top clock port 512 designed in the bottom module 122.

For the bottom module 121, the top clock ports 511 and 514 associated with the bottom module 121 are top clock ports 511 and 514, because the top clock ports 511 and 514 designed by the bottom module 121 are effectively covered by the bottom module 121.

By the design of the top clock port, the utilization rate of the effective coverage area of the top clock port can be improved, for example, the area of the overlapping area of the effective coverage area of the top clock port is minimized.

As an optional implementation of adjusting the design position of the top-layer clock port of the adjacent bottom-layer module, when the area of the current bottom-layer module is smaller (for example, the area of the current bottom-layer module is smaller than the preset area), the embodiment of the application can determine the target adjacent bottom-layer module from the adjacent bottom-layer modules of the current bottom-layer module, wherein the sum of the areas of the target adjacent bottom-layer module and the current bottom-layer module is not greater than the effective coverage area of the top-layer clock port; therefore, the embodiment of the application can enable the effective coverage range of the top clock port of the target adjacent bottom layer module to cover the target adjacent bottom layer module and the current bottom layer module by adjusting the design position of the top clock port of the target adjacent bottom layer module.

That is, if there is a neighboring bottom layer module of the current bottom layer module when the area of the current bottom layer module is small: the sum of the areas of the adjacent bottom layer modules and the current bottom layer module is not larger than the target adjacent bottom layer module of the effective coverage range of a single top layer clock port; the embodiment of the application can enable the effective coverage area of the top clock port to cover the target adjacent bottom module and the current bottom module by adjusting the design position of the top clock port of the target adjacent bottom module.

By way of example, assuming that the sum of the areas of the bottom layer modules 122 and 123 in the example of FIG. 7 is not greater than the effective coverage of a single top layer clock port, the bottom layer module 122 and the bottom layer module 123 may be covered by adjusting the design position of the top layer clock port 512 on the boundary of the bottom layer module 122 such that the effective coverage of the top layer clock port 512.

Optionally, when the area of the current bottom layer module is smaller (for example, the area of the bottom layer module is smaller than the preset area), if no target adjacent bottom layer module exists in the adjacent bottom layer modules of the current bottom layer module, the sum of the areas of the target adjacent bottom layer module and the current bottom layer module is not greater than the effective coverage area of a single top layer clock port; the embodiment of the application can cover the current bottom layer module by adjusting the design positions of the top layer clock ports of the plurality of adjacent bottom layer modules of the current bottom layer module so that the effective coverage area of the top layer clock ports of the plurality of adjacent bottom layer modules is the sum of the areas of the parts of the current bottom layer module; accordingly, the top-level clock port associated with the current bottom-level module may be the top-level clock ports of a plurality of adjacent bottom-level modules.

In other embodiments, the electronic design aid may also be automatically processed by software to automatically determine the design location of the top level clock port. For example, based on the design strategy described above, the clock tree design flow of the electronic design auxiliary tool may be improved by a programming means, so as to automatically determine the design positions of the top clock ports, and make the overlapping areas of the effective coverage areas corresponding to the design positions of the top clock ports meet the preset overlapping conditions.

In an alternative implementation, when the electronic design auxiliary tool performs design of the top clock port on any current bottom module, if the area of the current bottom module is smaller than the preset area, the design of the top clock port is not performed on the current bottom module, but the design of the top clock port is performed on an adjacent bottom module of the current bottom module, so that the current bottom module can be covered by adjusting the design position of the top clock port of the adjacent bottom module of the current bottom module, so that the effective coverage of the top clock port of the adjacent bottom module is in the part of the current bottom module. If the area of the current bottom layer module is not smaller than the preset area, a top layer clock port (single or multiple top layer clock ports may be designed) may be designed at the boundary of the current bottom layer module, and the designed top layer clock port may cover or partially cover the area of the current bottom layer module.

It can be seen that, for the bottom layer module with a smaller area, the embodiment of the application does not design the top layer clock port, but multiplexes the top layer clock ports of the adjacent bottom layer modules, so that the overlapping area of the effective coverage area of the top layer clock port can be obviously reduced, and support is provided for reducing the redundant design of the clock tree design.

In step S612, a bottom clock tree is designed at each bottom module according to the top clock port associated with each bottom module; the bottom clock tree of the bottom module is accessed to the top clock tree of the top module through the associated top clock port.

After the design of the top clock port is completed, the embodiment of the application can design the bottom clock tree for the bottom module, so that the bottom design of the clock tree is realized. Different from the mode that each bottom module designs the clock tree independently, in the embodiment of the application, under the condition that the top clock port designed is associated with the bottom module, the bottom clock tree can be designed at each bottom module according to the top clock port associated with each bottom module.

As an optional implementation, if the top clock port associated with the bottom module is a top clock port designed by a boundary of the bottom module, based on a clock tree length corresponding to an effective coverage area of the top clock port, the embodiment of the application may perform design of the bottom clock tree in the bottom module based on the top clock port designed by the boundary of the bottom module, so that the bottom clock tree designed in the bottom module may access the top clock tree through the top clock port at the boundary.

For easy understanding, as shown in connection with the example of fig. 7, the top clock ports associated with the bottom module 121 are top clock ports 511 and 514, and in this embodiment of the present application, the design of the bottom clock tree may be performed inside the bottom module 121 based on the top clock ports 511 and 514, respectively; thus, the bottom clock tree designed based on the top clock port 511 may access the top clock tree through the top clock port 511, and the bottom clock tree designed based on the top clock port 514 may access the top clock tree through the top clock port 514.

If the top clock port associated with the bottom module is a top clock port designed on the boundary of the bottom module and a top clock port designed on an adjacent bottom module, the embodiment of the application can design a bottom clock tree in the bottom module based on the top clock port designed on the boundary of the bottom module, and design the bottom clock tree in the portion of the top clock port located in the bottom module based on the top clock port designed on the adjacent bottom module.

For ease of understanding, as shown in connection with the example of fig. 7, assuming that the top-level clock ports associated with the bottom-level module 122 are the top-level clock port 512 and the top-level clock port 514 of the bottom-level module 121, the design of the bottom-level clock tree may be performed inside the bottom-level module 122 based on the top-level clock port 512; and, based on the top clock port 514, the bottom clock tree design of the bottom module 122 is performed at the portion where the effective coverage area of the top clock port 514 is located in the bottom module 122; thus, in the bottom module 122, the bottom clock tree designed based on the top clock port 512 may be accessed through the top clock port 512, and the bottom clock tree designed based on the top clock port 514 may be accessed through the top clock port 514.

As another alternative implementation, if the boundary of the bottom module is not designed with the top clock port, the top clock port associated with the bottom module is: the top clock port of the bottom module is designed on the boundary of the adjacent bottom module and covered by the effective coverage area. Based on this situation, for the top-level clock port associated with the bottom-level module, the embodiment of the application may design the bottom-level clock tree based on the top-level clock port, where the effective coverage area of the top-level clock port is located in the bottom-level module.

For ease of understanding, as shown in connection with the example of fig. 7, the boundary of the bottom layer module 123 is not provided with a top layer clock port, and the top layer clock port associated with the bottom layer module 123 is the top layer clock port 512 of the adjacent bottom layer module 122; thus, embodiments of the present application may multiplex top-level clock port 512 to design the bottom-level clock tree for bottom-level module 123; based on the portion of the top-level clock port 512 that is located in the bottom-level module 123 and the effective coverage area of the top-level clock port 512, in the embodiment of the present application, the bottom-level clock tree design may be performed on the bottom-level module 123 based on the top-level clock port 512, and the designed clock tree may access the top-level clock tree through the top-level clock port 512.

It should be noted that, if the top-level clock port associated with the bottom-level module includes multiple top-level clock ports of the adjacent bottom-level module (multiple top-level clock ports may be located in different adjacent bottom-level modules), the embodiment of the present application may respectively base on each top-level clock port of the adjacent bottom-level module, and design the bottom-level clock tree at a portion where an effective coverage area of each top-level clock port is located in the bottom-level module.

It can be seen that if the top clock port associated with the bottom module includes the top clock port of the adjacent bottom module, the bottom module can design the bottom clock tree by multiplexing the top clock ports of the adjacent bottom module, so that the redundant circuit designed by the clock tree can be greatly reduced.

In an alternative implementation example, it is assumed that the area of an overlapping area of an effective coverage area corresponding to a design position of a plurality of top-layer clock ports is minimized, and for a bottom-layer module with a boundary not provided with the top-layer clock ports, the bottom-layer module designs a bottom-layer clock tree by multiplexing the top-layer clock ports of adjacent bottom-layer modules, so that the embodiment of the invention can maximally improve the utilization rate of the effective coverage area of the top-layer clock ports, thereby realizing the balance of bottom-layer clock delay without affecting the bottom-layer clock delay of the bottom-layer clock tree (related to the length of the bottom-layer clock tree), reducing the design quantity of the top-layer clock ports, realizing the reduction of redundant circuits of clock tree design, and improving the performance of clock tree design.

For ease of understanding, fig. 8 illustrates another exemplary diagram of a clock tree design provided by embodiments of the present application from the logic level of an integrated circuit. As shown in fig. 8, according to the clock tree design method provided in the embodiment of the present application, top-level clock ports 511 and 514 may be designed at the boundary of the bottom-level module 121, and top-level clock port 512 may be designed at the boundary of the bottom-level module 122; the boundary of the bottom module 123 is not designed with the top clock port, and the bottom module 123 performs the design of the bottom clock tree by multiplexing the top clock port 512. Thus, for the bottom clock tree design of the bottom module 121, the embodiment of the application may design the bottom clock tree 811 in the bottom module 121 based on the top clock port 511, and design the bottom clock tree 812 in the bottom module 121 based on the top clock port 514, so that the bottom clock tree 811 accesses the top clock tree 801 through the top clock port 511, and the bottom clock tree 812 accesses the top clock tree 801 through the top clock port 514, so that the bottom clock tree 811 and the bottom clock tree 812 designed in the bottom module 121 are used as the sub-structures of the top clock tree 801.

For the bottom clock tree design of the bottom module 122, the embodiment of the application may design the bottom clock tree 821 in the bottom module 122 based on the top clock port 512, so that the bottom clock tree 821 accesses the top clock tree 801 through the top clock port 512 as a sub-structure of the top clock tree 801. If the effective coverage of the top-level clock port 512 cannot cover the area of the bottom-level module 122, the bottom-level clock tree may also be designed in the bottom-level module 122 based on the top-level clock port 514, and in this case, reference is made to the foregoing description, which is not expanded here.

For the bottom clock tree design of the bottom module 123, since the bottom module 123 is not designed with the top clock port, the bottom module 123 multiplexes the top clock port 512 to design the bottom clock tree; therefore, in the embodiment of the present application, the bottom clock tree 831 may be designed for the bottom module 123 based on the top clock port 512 according to the area of the portion of the top clock port 512 where the effective coverage area is located on the bottom module 123; in turn, bottom clock tree 831 accesses top clock tree 801 through top clock port 512 as a sub-structure of top clock tree 801.

As a further alternative implementation, for the case where the top-level clock port associated with the bottom-level module includes a top-level clock port designed by an adjacent bottom-level module, since the bottom-level module involves clock signal transfer between the bottom-level module and the top-level clock port of the adjacent bottom-level module when multiplexing the top-level clock ports of the adjacent bottom-level module, the bottom-level clock delay (delay from the top-level clock port to the clock end point of the bottom-level clock tree) of the bottom-level module may be divided into an external bottom-level clock delay and an internal bottom-level clock delay of the bottom-level module.

The internal underlying clock delay of an underlying module may be considered as the delay of a clock signal from the boundary of the underlying module to the clock end of the underlying clock tree.

The external bottom clock delay of a bottom module may be considered as the delay of a clock signal from the top clock port of an adjacent bottom module to the boundary of the bottom module; for example, when the bottom layer module 123 designs the bottom layer clock tree 831 multiplexing the top layer clock port 512 of the bottom layer module 122, the external bottom layer clock delay of the bottom layer module 123 may be considered as the delay of the clock signal from the top layer clock port 512 to the boundary of the bottom layer module 123.

Based on the above, for the case that the top clock port associated with the bottom module comprises the top clock port of the adjacent bottom module, when the bottom module performs bottom clock tree design, the external bottom clock delay and the internal bottom clock delay of the bottom module can be determined according to the bottom clock delay required to be balanced by the bottom module; for example, based on the length of the bottom clock delay of the bottom module, the external bottom clock delay outside the bottom module and the internal bottom clock delay inside the bottom module are distributed to ensure that the bottom clock delay of the bottom module is balanced. Therefore, in an alternative implementation, according to the external bottom clock delay of the bottom module, the connection position of the top clock port of the adjacent bottom module (the connection position can be physically embodied in a port or the like) can be designed at the boundary of the bottom module, so as to design the connection position of the top clock port of the adjacent bottom module in the boundary of the bottom module. Meanwhile, according to the internal bottom clock delay of the bottom module, the bottom clock tree is designed at the part of the adjacent bottom module where the effective coverage area of the top clock port of the bottom module is located; for example, the effective coverage of the top-level clock ports for adjacent bottom-level modules is located in the portion of the bottom-level module, and the length of the designed bottom-level clock tree corresponds to the internal bottom-level clock delay.

It should be noted that, for the bottom module with the boundary designed with the top clock port, the bottom module uses the top clock port at the boundary to design the bottom clock tree, so the external bottom clock delay is not involved; when the bottom layer clock tree is designed based on the top layer clock port, the length of the designed bottom layer clock tree can correspond to the bottom layer clock delay required to be balanced by the bottom layer module.

As a further optional implementation, after the design of the bottom clock tree of each bottom module is completed, the bottom clock tree of each bottom module is accessed to the top clock tree through the associated top clock port, so that the bottom clock tree of the bottom module is split at the top. Based on the clock tree with the split top layer, the embodiment of the application can further perform time sequence

And (5) checking. Further, the embodiment of the application may perform the power consumption check after the timing check passes. After the time sequence check and the power consumption check are passed, the clock tree design can be completed according to the embodiment of the application, so that the performance of the clock tree design is optimized under the condition of considering the angles of time sequence, power consumption, redundant design of the clock tree and the like. Optionally, if the timing sequence check or the power consumption check fails, the embodiment of the application may adjust the position design of the top clock port and/or the design of the bottom clock tree in the bottom module to meet the requirements of the timing sequence check and the power consumption check, so as to balance the timing sequence, the power consumption and the redundancy design of the clock tree of the integrated circuit.

As an alternative implementation, fig. 9 illustrates another alternative flowchart of a clock tree design method provided in an embodiment of the present application, and as shown in fig. 9, the method flow may include the following steps.

In step S910, a layout design is performed on the integrated circuit.

After the integrated circuit is subjected to layout planning design, the embodiment of the application can determine layout planning information of design modules in the integrated circuit, wherein the layout planning information can comprise information such as relative positions of all bottom layer modules, sizes (e.g. areas) of all bottom layer modules and the like.

In step S911, the top-level clock tree design is performed on the integrated circuit, and the top-level clock port is designed at the design position of the bottom-level module.

After layout planning and design, the embodiment of the application can perform top-to-bottom clock tree design, so that the embodiment of the application can perform top-level clock tree design on the top layer, including the design of the root of the clock tree and the hierarchical structure related to the top layer; meanwhile, the embodiment of the application can design the position of the top clock port at the boundary of the bottom module.

When the position of the top clock port is designed, besides the balance of the clock delay (under the condition that the top clock delay is balanced, the balance of the bottom clock delay is mainly considered), the position design of the top clock port can be performed by maximizing the utilization rate of the effective coverage of the top clock port according to the expected factors such as the effective coverage of the top clock port, the relative position relation among bottom modules, the area of the bottom modules and the like, and the effect of reducing the deployment number of the top clock port is achieved. The relevant content of the position design of the top clock port can be referred to the description of the corresponding parts, and the description is omitted here.

In step S912, an underlying clock tree design is performed at the underlying module.

Based on the position design of the top clock ports, the embodiment of the application can determine the top clock ports associated with each bottom module, so that the bottom clock tree design is performed for the bottom modules based on the top clock ports associated with each bottom module.

As described above, if the top clock port associated with the bottom module is the top clock port designed by the boundary of the bottom module, the bottom module may design the bottom clock tree inside the bottom module based on the top clock port designed by the boundary under the condition that the bottom clock delay needs to be balanced. Aiming at the situation that the top-layer clock port associated with the bottom-layer module comprises the top-layer clock port designed by the adjacent bottom-layer module, the bottom-layer module needs to design the boundary of the external top-layer clock port and the bottom-layer module and design the bottom-layer clock tree inside the bottom-layer module under the condition of giving external bottom-layer clock delay and internal bottom-layer clock delay, so that the bottom-layer clock delay of the bottom-layer module can meet the bottom-layer clock delay condition needing balance.

In step S913, the bottom clock tree of each bottom module is top-level stitched.

Optionally, the bottom clock tree of the bottom module may be accessed to the top clock tree through the associated top clock port to achieve top splicing.

In step S914, it is checked whether the clock delay and clock offset of each register in the integrated circuit meet the expectations, if so, step S915 is executed, and if not, step S912 is returned.

After the top layer stitching is completed, the clock delay and clock offset of each register in the integrated circuit can be checked to determine whether the timing sequence of the integrated circuit meets the expectations. Optionally, the embodiment of the present application may determine whether the clock delay of the register accords with the expected clock delay, and whether the clock offset accords with the expected clock offset; if the clock delay of each register matches the expected clock delay and the clock offset matches the expected clock offset, then it may be confirmed that the timing check matches the expected, step S915 may be entered to complete the clock tree design; if there is any register whose clock delay does not meet the expected clock delay or the clock offset does not meet the expected clock offset, the embodiment of the application may return to step S912 to re-perform the bottom layer clock tree design on the bottom layer module until the clock delay and the clock offset of the register in the integrated circuit meet the expected clock delay.

In step S915, the clock tree design is completed.

In a further optional implementation, the embodiment of the present application may further check whether the power consumption of the integrated circuit meets the expectation after the clock delay and clock offset check of each register meet the expectation, and complete the clock tree design if the power consumption of the integrated circuit meets the expectation; if the power consumption of the integrated circuit is not expected, the embodiment of the present application may return to step S912 to re-design the underlying clock tree.

In another optional implementation, the embodiment of the present application may also return to step S911 when the clock delay and clock offset of the register are not expected, or the power consumption of the integrated circuit is not expected, so as to perform adjustment from the stage of position design of the top clock port, to comprehensively consider factors such as timing, power consumption, redundancy design of the clock tree, and the like of the integrated circuit, so as to optimize the performance of the clock tree design.

Compared with the bottom-to-top clock tree design, the top-to-bottom clock tree design provided by the embodiment of the application can have the following advantages:

the utilization rate of the effective coverage area of the top clock port is improved (for example, the effective coverage area of the top clock port is utilized to the maximum extent), and the number of the top clock ports is reduced, so that the redundant design brought by the overlapping area of the effective coverage area of the top clock port is reduced, and the redundant circuit of the clock tree design is reduced;

Furthermore, by reducing the number of top clock ports, or even minimizing the number of top clock ports, the design complexity of the top clock tree can be effectively reduced, and the effects of saving the area of an integrated circuit and saving the power consumption are achieved;

further, by reducing or even minimizing the number of top-level clock ports, a portion of the bottom-level modules may not be designed with top-level clock ports, so that a portion of the DFT designs associated with the bottom-level modules may be removed to achieve

The area of the integrated circuit is saved, and the power consumption is saved;

furthermore, by reducing the number of top-level clock ports, even minimizing the number of top-level clock ports, on the premise that the total length of the sequential circuits between the bottom-level modules is unchanged, the number of clock circuits shared between the bottom-level modules can be increased, and the improvement effect that the OCV of the clock path part can be reduced is brought.

The embodiment of the application also provides a clock tree design device, which can be regarded as a functional module required by design equipment for realizing the clock tree design method provided by the embodiment of the application, the design equipment can run an electronic design auxiliary tool, and the device can be loaded in the electronic design auxiliary tool operated by the design equipment. The contents described below may be referred to in correspondence with the above description.

As an alternative implementation, fig. 10 illustrates an alternative block diagram of a clock tree design apparatus provided in an embodiment of the present application, where the apparatus may be applied to a design device, as shown in fig. 10, and the apparatus may include:

the design module determining unit 01 is used for determining a design module to be subjected to clock tree design, and the design module comprises a top layer module and a plurality of bottom layer modules called by the top layer module;

a top-level clock port design unit 02, configured to determine design information of top-level clock ports, where the design information includes design positions of a plurality of top-level clock ports and top-level clock ports associated with each bottom-level module; the top clock end is designed at the boundary of the bottom module, and the overlapping area of the effective coverage area corresponding to the design position of the top clock ends accords with a preset overlapping condition;

the bottom clock tree design unit 03 is configured to design a bottom clock tree at each bottom module according to the top clock ports associated with each bottom module; the bottom clock tree of the bottom module is accessed to the top clock tree of the top module through the associated top clock port.

Optionally, the overlapping area of the effective coverage area corresponding to the design position of the plurality of top-level clock ports meets a preset overlapping condition includes: the area of the overlapping area of the effective coverage area corresponding to the design position of the top-layer clock ports is minimized.

Optionally, the design positions of the top-level clock ports are determined at least according to the area of each bottom-level module, the relative position of each bottom-level module, and the effective coverage area of the top-level clock ports; the area of each bottom layer module and the relative position of each bottom layer module are determined according to the layout planning information of the design module.

Optionally, as further shown in conjunction with fig. 10, the apparatus may further include:

the design page display unit 04 is used for displaying a clock tree design page, wherein the clock tree design page displays a plurality of bottom layer modules based on the area of each bottom layer module and the relative position of each bottom layer module;

the effect display unit 05 is used for displaying the display effect of the effective coverage range of the top clock port on the clock tree design page based on the design operation of the top clock port;

further optionally, the top-level clock port design unit 02 is configured to determine design information of the top-level clock port, including: at the position of

And when the design operation is confirmed to be completed, determining design information corresponding to the design operation of the top clock port.

Optionally, the top clock port associated with the bottom module includes:

if the boundary of the bottom layer module is designed with a top layer clock port, the top layer clock port associated with the bottom layer module is at least the top layer clock port designed by the boundary of the bottom layer module;

If the boundary of the bottom module is not designed with the top clock port, the top clock port associated with the bottom module is: the top clock port of the bottom module is designed on the boundary of the adjacent bottom module and covered by the effective coverage area.

If the boundary of the bottom module is designed with a top clock port, the top clock port associated with the bottom module is at least the top clock port designed for the boundary of the bottom module, and the top clock port comprises:

if the boundary of the bottom layer module is designed with a top layer clock port, and the effective coverage area of the top layer clock port designed by the boundary of the bottom layer module can cover the bottom layer module, the top layer clock port associated with the bottom layer module is the top layer clock port designed by the boundary of the bottom layer module;

Optionally, the bottom clock tree design unit 03 is configured to design, at each bottom module, a bottom clock tree according to a top clock port associated with each bottom module, where the bottom clock tree includes:

If the top clock port associated with the bottom module is the top clock port designed by the boundary of the bottom module, the bottom clock tree is designed inside the bottom module based on the top clock port designed by the boundary of the bottom module.

if the top clock port associated with the bottom module is a top clock port designed on the boundary of the bottom module and a top clock port designed on the adjacent bottom module, the bottom clock tree is designed inside the bottom module based on the top clock port designed on the boundary of the bottom module; and designing a bottom clock tree on the basis of a top clock port designed on the adjacent bottom module, wherein the effective coverage area of the top clock port is positioned on the part of the bottom module.

if the top clock port associated with the bottom module is the top clock port designed on the adjacent bottom module, the bottom clock tree is designed on the basis of the top clock port designed on the adjacent bottom module at the part of the effective coverage area of the top clock port located on the bottom module.

Optionally, for the case that the top clock port associated with the bottom module includes a top clock port designed by an adjacent bottom module, the bottom clock delay of the bottom module is divided into an external bottom clock delay and an internal bottom clock delay of the bottom module; the external bottom layer clock delay is the delay from the top layer clock port of the adjacent bottom layer module to the boundary of the bottom layer module, and the internal bottom layer clock delay is the delay from the boundary of the bottom layer module to the clock end point of the bottom layer clock tree.

Optionally, the bottom clock tree design unit 03 is configured to design a bottom clock tree based on a top clock port designed on an adjacent bottom module, where an effective coverage area of the top clock port is located in a portion of the bottom module, where the bottom clock tree design unit includes:

according to the external bottom clock delay of the bottom module, designing a connection position with a top clock port of an adjacent bottom module at the boundary of the bottom module; and designing a bottom clock tree according to the internal bottom clock delay of the bottom module and the part of the effective coverage area of the top clock port of the adjacent bottom module, which is positioned on the bottom module.

Optionally, for any current bottom layer module, if the area of the current bottom layer module is smaller than the preset area, the boundary of the current bottom layer module is not designed with the top layer clock port, and the design position of the top layer clock port of the adjacent bottom layer module of the current bottom layer module is such that the effective coverage area of the top layer clock port of the adjacent bottom layer module is located at the part of the current bottom layer module to cover the current bottom layer module.

Optionally, the design position of the top clock port of the adjacent bottom module of the current bottom module is such that the effective coverage area of the top clock port of the adjacent bottom module is located in the portion of the current bottom module, and covering the current bottom module includes:

if the adjacent bottom layer module of the current bottom layer module is provided with the target adjacent bottom layer module, the design position of the top clock port of the target adjacent bottom layer module enables the effective coverage area of the top clock port of the target adjacent bottom layer module to cover the target adjacent bottom layer module and the current bottom layer module; the sum of the areas of the target adjacent bottom layer module and the current bottom layer module is not larger than the effective coverage area of the top layer clock port.

if the adjacent bottom layer module of the current bottom layer module does not have the target adjacent bottom layer module, the design positions of the top clock ports of the adjacent bottom layer modules of the current bottom layer module are such that the effective coverage area of the top clock ports of the adjacent bottom layer modules is positioned in the sum of the areas of the parts of the current bottom layer module to cover the current bottom layer module; the sum of the areas of the target adjacent bottom layer module and the current bottom layer module is not larger than the effective coverage area of the top layer clock port.

Further alternatively, the apparatus may be further configured to:

after the bottom clock tree of each bottom module is accessed into the top clock tree of the top module through the associated top clock port, checking whether the clock delay of each register in the integrated circuit accords with the expected clock delay or not and whether the clock offset accords with the expected clock offset or not; and checking whether the power consumption of the integrated circuit meets the expectations;

if the clock delay of each register matches the expected clock delay, the clock offset matches the expected clock offset, and the power consumption of the integrated circuit is checked for compliance, the completion of the clock tree design is confirmed.

The embodiment of the application also provides design equipment, which can be used for carrying the clock tree design device provided by the embodiment of the application so as to realize the clock tree design method provided by the embodiment of the application. As an alternative implementation, fig. 11 illustrates an alternative block diagram of a design apparatus provided by an embodiment of the present application, where the design apparatus may be a computer apparatus running an electronic design assistance tool, and referring to fig. 11, the design apparatus may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4.

In the embodiment of the present application, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 complete communication with each other through the communication bus 4.

Alternatively, the communication interface 2 may be an interface of a communication module for performing network communication.

Alternatively, the processor 1 may be a CPU (central processing unit), GPU (Graphics Processing Unit, graphics processor), NPU (embedded neural network processor), FPGA (Field Programmable Gate Array ), TPU (tensor processing unit), AI chip, specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present application, or the like.

The memory 3 may comprise a high-speed RAM memory or may further comprise a non-volatile memory, such as at least one disk memory.

Wherein the memory 3 stores one or more computer-executable instructions that the processor 1 invokes to perform the clock tree design method provided in the embodiments of the present application.

The embodiment of the application also provides a storage medium, which stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the clock tree design method provided by the embodiment of the application is realized.

The embodiment of the application also provides an integrated circuit, which may include: the design module of hierarchical design and the clock tree designed based on the clock tree design method provided by the embodiment of the application; the clock tree provides clock signals for the design module. The design module of the hierarchical design and the relevant content of the clock tree can refer to the description of the corresponding parts, and are not repeated here.

The foregoing describes a number of embodiments provided by embodiments of the present application, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible, all of which may be considered embodiments disclosed and disclosed by embodiments of the present application.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.

Claims

1. A method of clock tree design, comprising:

2. The method of claim 1, wherein the overlapping area of the effective coverage area corresponding to the design position of the plurality of top-level clock ports meets a preset overlapping condition comprises: the area of the overlapping area of the effective coverage area corresponding to the design position of the top-layer clock ports is minimized.

3. The method of claim 1, wherein the design locations of the plurality of top-level clock ports are determined based at least on an area of each bottom-level module, a relative location of each bottom-level module, and an effective coverage of the top-level clock ports; the area of each bottom layer module and the relative position of each bottom layer module are determined according to the layout planning information of the design module.

4. A method according to claim 3, further comprising:

displaying a clock tree design page, wherein the clock tree design page displays a plurality of bottom layer modules based on the area of each bottom layer module and the relative position of each bottom layer module;

based on the design operation of the top clock port, displaying the display effect of the effective coverage area of the top clock port on a clock tree design page;

the determining design information of the top clock port includes:

5. The method of any of claims 1-4, wherein the top-level clock port associated with the bottom-level module comprises:

6. The method of claim 5, wherein if the boundary of the bottom module is designed with a top-level clock port, the top-level clock port associated with the bottom module is at least the top-level clock port designed with the boundary of the bottom module comprises:

7. The method of claim 6, wherein designing the bottom level clock tree at each bottom level module based on the top level clock ports associated with each bottom level module comprises:

8. The method of claim 6, wherein designing the bottom level clock tree at each bottom level module based on the top level clock ports associated with each bottom level module comprises:

9. The method of claim 6, wherein designing the bottom level clock tree at each bottom level module based on the top level clock ports associated with each bottom level module comprises:

10. The method according to claim 8 or 9, wherein for the case where the top-level clock port associated with the bottom-level module comprises a top-level clock port designed for an adjacent bottom-level module, the bottom-level clock delay of the bottom-level module is divided into an external bottom-level clock delay and an internal bottom-level clock delay of the bottom-level module; the external bottom layer clock delay is the delay from the top layer clock port of the adjacent bottom layer module to the boundary of the bottom layer module, and the internal bottom layer clock delay is the delay from the boundary of the bottom layer module to the clock end point of the bottom layer clock tree.

11. The method of claim 10, wherein the designing the bottom clock tree based on the top clock port designed in the adjacent bottom module, in a portion of the top clock port having an effective coverage area located in the bottom module, comprises:

12. The method of claim 5, wherein for any current bottom layer module, if the area of the current bottom layer module is smaller than the preset area, the boundary of the current bottom layer module is not designed with the top layer clock port, and the design positions of the top layer clock ports of the adjacent bottom layer modules of the current bottom layer module are such that the effective coverage area of the top layer clock ports of the adjacent bottom layer modules is located at the portion of the current bottom layer module to cover the current bottom layer module.

13. The method of claim 12, wherein the designing the top-level clock ports of the adjacent bottom-level modules of the current bottom-level module is positioned such that the effective coverage area of the top-level clock ports of the adjacent bottom-level modules is located in a portion of the current bottom-level module, and the covering the current bottom-level module comprises:

14. The method of claim 12, wherein the designing the top-level clock ports of the adjacent bottom-level modules of the current bottom-level module is positioned such that the effective coverage area of the top-level clock ports of the adjacent bottom-level modules is located in a portion of the current bottom-level module, and the covering the current bottom-level module comprises:

15. The method as recited in claim 1, further comprising:

if the clock delay of each register matches the expected clock delay, the clock offset matches the expected clock offset, and the power consumption of the integrated circuit matches the expected, then the completion of the clock tree design is confirmed.

16. A clock tree design apparatus, comprising:

17. The apparatus as recited in claim 16, further comprising:

the clock tree design page is used for displaying a clock tree design page, and the clock tree design page displays a plurality of bottom layer modules based on the area of each bottom layer module and the relative position of each bottom layer module;

the effect display unit is used for displaying the display effect of the effective coverage range of the top clock port on the clock tree design page based on the design operation of the top clock port;

the top-level clock port design unit is configured to determine design information of a top-level clock port, including: and when the design operation is confirmed to be completed, determining design information corresponding to the design operation of the top clock port.

18. The apparatus of claim 16 or 17, wherein the top-level clock port associated with the bottom-level module comprises:

If the boundary of the bottom module is not designed with the top clock port, the top clock port associated with the bottom module is: the top clock port is designed at the boundary of the adjacent bottom module and covers the bottom module in an effective coverage range;

the method comprises the steps that aiming at the condition that a top clock port associated with a bottom module comprises a top clock port designed by an adjacent bottom module, bottom clock delay of the bottom module is divided into external bottom clock delay and internal bottom clock delay of the bottom module; the external bottom layer clock delay is the delay from the top layer clock port of the adjacent bottom layer module to the boundary of the bottom layer module, and the internal bottom layer clock delay is the delay from the boundary of the bottom layer module to the clock end point of the bottom layer clock tree.

19. A design apparatus, comprising: at least one memory and at least one processor; the memory stores one or more computer-executable instructions that the processor invokes to perform the clock tree design method of any one of claims 1-15.

20. A storage medium storing one or more computer-executable instructions which, when executed, implement the clock tree design method of any one of claims 1-15.

21. An integrated circuit, the integrated circuit comprising: a design module of hierarchical design, a clock tree designed based on the clock tree design method of any one of claims 1 to 15; the clock tree provides clock signals for the design module.