CN116501436B - Method, electronic device and medium for maximizing display chip design code annotation - Google Patents
Method, electronic device and medium for maximizing display chip design code annotation Download PDFInfo
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Abstract
The invention relates to the technical field of chips, in particular to a method, electronic equipment and medium for maximizing annotation of a chip design code, wherein the method comprises the following steps of S1, longitudinally dividing a visual interface into a first display area for displaying the chip design code and a second display area for displaying annotation information corresponding to the chip design code; s2, acquiring a j-th annotation code row A to be displayed in the chip design code displayed in the first display area j Corresponding quadruple information (T j ，x j ，Vx j ，W j ) The method comprises the steps of carrying out a first treatment on the surface of the Step S3, contrast W J And R, if W J If R is less than or equal to R, directly executing the step S5, otherwise, executing the step S4; step S4, updating at least one Vx j So that all Vx j Is equal to R, and then step S5 is performed; step S5, displaying each A in the second display area j Corresponding to Vx j Line annotation information. The invention improves the interface utilization rate and the display effect of the chip design annotation display.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method, an electronic device, and a medium for maximizing annotation of a design code of a display chip.
Background
In the field of chip design verification, it is often necessary to verify the data values of the same design signal at different points in time. In order to view the corresponding signal value in the design code file, an Annotation (analysis) mode is generally adopted, and in the same display interface, the original design code file is displayed, and specific data values of the signal at the corresponding time point are displayed. In the prior art, the data values of the corresponding signal variables are typically displayed in the design code in a row-by-row fashion, with the signal variable names corresponding to the signal values on the columns. However, when the display length required by the signal value of one signal is longer than the signal variable name, the display interface cannot display the complete signal value data, and the display effect is poor. So that part of the tool will also display annotation information in a multi-line fashion. However, when the number of signal variables in the same row is too large, a large amount of annotation information exists in the display interface, so that enough chip design information cannot be displayed, and the interface utilization rate is low. Therefore, how to improve the interface utilization rate of the chip design annotation display and improve the display effect is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a method, electronic equipment and medium for maximizing display of chip design code annotation, and the interface utilization rate and display effect of chip design annotation display are improved.
According to a first aspect of the present invention, there is provided a method of maximising display chip design code annotation, comprising:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, and the second display area is used for displaying annotation information corresponding to the chip design codes;
s2, acquiring a j-th annotation code row A to be displayed in the chip design code displayed in the first display area j Corresponding quadruple information (T j ，x j ，Vx j ，W j ) Wherein the total display line number of the first display area is R; t (T) i Is A j Corresponding physical line numbers in the chip design codes, and lines of codes needing to be annotated for the behavior of the annotation codes to be displayed; x is x j Is A j The number of lines of the annotation to be written, vx, corresponding to the second display area j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j =x j ；W j In order to the J-th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is 1 to J, wherein J is the total number of the code lines to be displayed in the currently displayed chip design code, J is less than or equal to R, and 1 is less than or equal to T i ≤R；
Step S3, contrast W J And R, if W J If R is less than or equal to R, directly executing the step S5, otherwise, executing the step S4;
step S4, updating at least one Vx j So that all Vx j Is equal to R, and then step S5 is performed;
step S5, displaying each A in the second display area j Corresponding to Vx j Line annotation information.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having stored therein computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the method, the electronic equipment and the medium for maximizing the annotation of the design codes of the display chip can achieve quite technical progress and practicality, and have wide industrial utilization value, and the method and the medium have at least the following beneficial effects:
according to the method, the visual interface is longitudinally divided into the first display area and the second display area, the chip design codes and the annotation information are decoupled, the annotation information is displayed through the two areas, the display of the annotation information is more flexible and compact, the four-element information of each annotation code to be displayed in the chip design codes displayed in the first display area is obtained, the corresponding annotation information is displayed based on the four-element information of each annotation code to be displayed, and the interface utilization rate and the display effect of the chip design annotation display are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for maximizing display of chip design code annotations provided by an embodiment of the present invention;
FIG. 2 is a diagram illustrating the design code annotation of the maximized display chip according to the embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a method for maximizing display chip design code annotation, which is shown in fig. 1 and comprises the following steps:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, and the second display area is used for displaying annotation information corresponding to the chip design codes.
S2, acquiring a j-th annotation code row A to be displayed in the chip design code displayed in the first display area j Corresponding quadruple information (T j ，x j ，Vx j ，W j ) Wherein the total display line number of the first display area is R; t (T) i Is A j Corresponding physical line numbers in the chip design codes, and lines of codes needing to be annotated for the behavior of the annotation codes to be displayed; x is x j Is A j The number of lines of the annotation to be written, vx, corresponding to the second display area j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j =x j ；W j In order to the J-th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is 1 to J, wherein J is the total number of the code lines to be displayed in the currently displayed chip design code, J is less than or equal to R, and 1 is less than or equal to T i ≤R。
The chip design code displayed in the first display area includes a code line that needs to display the annotation, and also includes a code line that does not need to display the annotation, and in step S2, only four-tuple information corresponding to the code line that needs to display the annotation is extracted. Further, the line content of the chip design code may be divided into visible lines and physical lines, where the physical lines correspond to lines of the real text file and the visible lines correspond to lines visible on the interface. When the folding function exists in the interface, the physical line of the file cannot be obtained through simple line number addition and subtraction. Such as: visible rows 12, 13, 14 may be 12, 13, and 37 for physical rows, i.e., 23 physical rows are hidden from view behind visible row 13. T obtained in step S2 j Is the physical line number.
Step S3, contrast W J And R, if W J And (5) if R is not more than, directly executing the step S5, otherwise, executing the step S4.
It can be understood that the maximum number of lines that can be displayed in the first display area and the second display area is the same, and the total number of lines displayed in the first display area is R, so the total number of lines displayed in the second display area is R. If W is J And R is less than or equal to R, the second display area is enough to display all annotation information lines, and the annotation information lines do not need to be hidden. If W is J >R, it is explained that the second display area is insufficient to display all the annotation information lines, and therefore a part of the annotation information lines needs to be hidden.
Step S4, updating at least one Vx j So that all Vx j Is equal to R, and then step S5 is performed.
Updating Vx by step S4 j And determining the number of lines of hidden annotation information corresponding to at least one annotation code to be displayed.
Step S5, displaying each A in the second display area j Corresponding to Vx j Line annotation information.
According to the embodiment of the invention, the visual interface is longitudinally divided into the first display area and the second display area, the chip design code and the annotation information are decoupled, and the display of the annotation information is more flexible and compact through the two areas.
As an embodiment, the step S2 includes:
step S21, initializing chip design code sequence number r=1, j=0, W j =0, step S22 is performed.
Step S22, obtaining the r-th row design code B in the chip design codes displayed in the first display area r If B r If there is a signal variable, then set j=j+1, set a j =B r Step S23 is performed, otherwise step S25 is performed.
It should be noted that, the code row of the annotation to be displayed is the code of the annotation to be displayed in the chip design code row with signal variable.
Step S23, obtaining A j Corresponding physical line number T i Number of signal variables G j Sum signal variable list L j 。
It will be appreciated that A j Corresponding list of signal variables L j The number of signals in (a) is G j 。
Step S24, based on G j Acquisition A j The number of lines x of the annotation to be written corresponding to the second display area j ，x j =⌈G j M ⌉, wherein m is the annotation number of signal variables which can be displayed in each row of the second display area, ⌈ ⌉ represents rounding up, and Vx is set j =x j Setting W j =W j + x j Based on A j Corresponding T j ，x j ，Vx j ，W j Generation A j Corresponding quadruple information (T j ，x j ，Vx j ，W j ) Step S25 is performed.
It should be noted that, each signal variable corresponds to a signal annotation, and the signal annotation specifically may include a signal variable identifier and a corresponding signal annotation identifier. Number of lines of annotations to be written x j For the expected number of annotation lines to be displayed corresponding to each annotation code to be displayed, but limited by the display lines of the second area, the lines may not be completely displayed, so that the number of annotation lines to be displayed corresponding to the second display area, that is, the number of annotation lines actually capable of being displayed in the display process, is set, and Vx can be set in the initial process j =x j And then the display is adjusted according to specific display requirements.
Step S25, if R < R, r=r+1 is set, and the routine returns to step S22, and if r=r, step S3 is executed.
Through the steps S21-S25, four-tuple information corresponding to all annotation code lines to be displayed in the chip design code displayed in the first display area can be obtained.
As an embodiment, the step S4 includes:
step S41, obtaining the number of lines h of the line annotation to be hidden, where h=w J -R, set i=j, execute step S42.
Since the second display area is insufficient to display all lines of annotation information, it is necessary to hide a part of the lines of annotation information. Note that, in general, the note information line corresponding to the chip design code line having the front sequence number is more important, and therefore, it is preferable to hide the note information line from the line having the largest sequence number.
Step S42, if Vx i And (3) if L is less than or equal to L, executing the step S45, otherwise, executing the step S43, wherein L is the preset minimum annotation information line number corresponding to each annotation code line to be displayed.
Wherein, if Vx i The number of lines of annotation information which are required to be displayed for indicating the lines of the annotation code to be displayed is less than the minimum number of lines of annotation information, so that the corresponding Vx is directly displayed subsequently i And annotating the information.
Step S43, if x i -L is greater than or equal to h, setting Vx i =x i H, and set h=0, jump to step S5, otherwise, execute step S44.
Wherein if x i And L is larger than or equal to h, and the actual requirement can be met after the annotation line corresponding to the current annotation code line to be displayed is hidden.
Step S44, setting Vx i =l, set h=h- (x) i -L), if h=0, jump to step S5, if h>0, step S45 is performed.
Wherein, when x i When L, the current ith annotation code row to be displayed is insufficient to hide h rows on the premise of meeting the minimum annotation information row number, so x is hidden on the premise of meeting the minimum annotation information row number i L rows and updates the corresponding h value.
In step S45, if i >1, i=i-1 is set, and the process returns to step S41.
It should be noted that, through steps S41-S45, one possibility is to go through J Vx i H can be updated to 0, i.e. the display requirement is met by hiding part of the annotation line. However, in still another case, J Vx's are traversed i And h is still larger than 0, namely the second display area is still insufficient to display the hidden annotation information row on the premise of ensuring that the minimum annotation information row is met. As an example, in the step S45, if i=1 and h>0, the step S5 includes:
step S50, starting with j=1, according to the current Vx i Value the second display area displays A j Corresponding annotation information, when the total number of lines displaying the annotation information reaches R, the rest A is not displayed any more j Is provided.
It will be appreciated that the annotation code line a to be displayed with the front sequence number is preferentially displayed on the premise that the second display area is insufficient to display the hidden annotation information line j Corresponding Vx i The lines annotate the information lines. The embodiment of the invention covers more annotation information corresponding to the chip design codes in the first display area as much as possible.
As an embodiment, the step S5 includes:
step S51, transversely dividing the second display area into J sub-areas A j And B is connected with j Associated, B j And the j-th sub-area of the second display area.
Wherein A is j And B is connected with j Can be specifically correlated by adopting a correlation line, and can be clearDisplay A j And B is connected with j And the association relation between the two. In the example shown in fig. 2, the left area in the figure is a first display area for displaying a chip design code, in the example in fig. 2, the chip design code includes 4 lines of annotation code lines to be displayed, each line includes at least one Signal variable Signal, in the second display area on the right side, the number m of Signal variable annotations that can be displayed in each line in the second display area is set to 1, and value is a Signal value corresponding to the corresponding Signal. Note that, in the first area in fig. 2, a code line that does not need to display annotation information is omitted. In FIG. 2, the associated line is specifically arranged in the form of a line segment with brackets, and A is clearly shown j And B is connected with j And the association relation between the two images improves the display effect.
Step S52, at B j Middle display A j Corresponding Vx j Line annotation information.
As an embodiment, each sub-area of the second display area is provided with a corresponding horizontal scroll bar and a corresponding vertical scroll bar, the annotation information horizontally displayed in the corresponding sub-area is adjusted by operating the horizontal scroll bar, and the annotation information vertically displayed in the corresponding sub-area is adjusted by operating the vertical scroll bar. Note that, the length of the annotation information corresponding to different signal variables may be different, and for the annotation information that is too long, it may be impossible to completely display the annotation information in the second display area through one line, so a horizontal scroll bar may be set, and the annotation information that is horizontally displayed in the corresponding sub-area may be adjusted by operating the horizontal scroll bar. Furthermore, by means of steps S41-S45, a partial sub-area is made to hide a partial annotation information line, so that a longitudinal scroll bar may be provided, and the annotation information displayed longitudinally in the corresponding sub-area is adjusted by operating the longitudinal scroll bar. Each sub-region of the second display area may be provided with a horizontal scroll bar and a vertical scroll bar separately according to display requirements.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores computer instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the visual interface is longitudinally divided into the first display area and the second display area, the chip design codes and the annotation information are decoupled, the annotation information corresponding to all the annotation code lines to be displayed in the first display area is displayed in the second display area as much as possible, when the second annotation display area is insufficient for displaying, the annotation code lines to be displayed in the first display area are covered as much as possible through the adjustment of a hiding algorithm, and the annotation code lines to be displayed in the first display area are maximally covered. In addition, the display of the annotation information is more flexible and compact through the display of the two areas, and the corresponding annotation information is displayed based on the four-tuple information of each annotation code to be displayed in the chip design code displayed in the first display area by acquiring the four-tuple information of each annotation code to be displayed, so that the interface utilization rate and the display effect of the chip design annotation display are improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (6)
1. A method of maximizing display of chip design code annotations, comprising:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, and the second display area is used for displaying annotation information corresponding to the chip design codes;
s2, acquiring a j-th annotation code row A to be displayed in the chip design code displayed in the first display area j Corresponding quadruple information (T j ，x j ，Vx j ，W j ) Wherein the total display line number of the first display area is R; t (T) i Is A j Corresponding physical line numbers in the chip design codes, and lines of codes needing to be annotated for the behavior of the annotation codes to be displayed; x is x j Is A j The number of lines of the annotation to be written, vx, corresponding to the second display area j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j =x j ；W j In order to the J-th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is 1 to J, wherein J is the total number of the code lines to be displayed in the currently displayed chip design code, J is less than or equal to R, and 1 is less than or equal to T i ≤R；
Step S3, contrast W J And R, if W J If R is less than or equal to R, directly executing the step S5, otherwise, executing the step S4;
step S4, updating at least one Vx j So that all Vx j Is equal to R, and then step S5 is performed;
step S5, displaying each A in the second display area j Corresponding to Vx j Line annotation information;
the step S2 includes:
step S21, initializing the chipDesign code sequence number r=1, j=0, w j =0, step S22 is performed;
step S22, obtaining the r-th row design code B in the chip design codes displayed in the first display area r If B r If there is a signal variable, then set j=j+1, set a j =B r Step S23 is executed, otherwise step S25 is executed;
step S23, obtaining A j Corresponding physical line number T i Number of signal variables G j Sum signal variable list L j ；
Step S24, based on G j Acquisition A j The number of lines x of the annotation to be written corresponding to the second display area j ，x j =⌈G j M ⌉, wherein m is the annotation number of signal variables which can be displayed in each row of the second display area, ⌈ ⌉ represents rounding up, and Vx is set j =x j Setting W j =W j + x j Based on A j Corresponding T j ，x j ，Vx j ，W j Generation A j Corresponding quadruple information (T j ，x j ，Vx j ，W j ) Step S25 is performed;
step S25, if R < R, r=r+1 is set, and the process returns to step S22, and if r=r, step S3 is executed;
the step S4 includes:
step S41, obtaining the number of lines h of the line annotation to be hidden, where h=w J -R, set i=j, execute step S42;
step S42, if Vx i If L is less than or equal to L, executing step S45, otherwise, executing step S43, wherein L is the preset minimum annotation information line number corresponding to each annotation code line to be displayed;
step S43, if x i -L is greater than or equal to h, setting Vx i =x i -h, and setting h=0, jumping to step S5, otherwise, executing step S44;
step S44, setting Vx i =l, set h=h- (x) i -L), if h=0, jump to step S5, if h>0, executing step S45;
in step S45, if i >1, i=i-1 is set, and the process returns to step S41.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the step S45, if i=1 and h >0, the step S5 includes:
step S50, starting with j=1, according to the current Vx i Value the second display area displays A j Corresponding annotation information, when the total number of lines displaying the annotation information reaches R, the rest A is not displayed any more j Is provided.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S5 includes:
step S51, transversely dividing the second display area into J sub-areas A j And B is connected with j Associated, B j A j-th sub-region of the second display region;
step S52, at B j Middle display A j Corresponding Vx j Line annotation information.
4. The method of claim 3, wherein the step of,
and each subarea of the second display area is provided with a corresponding transverse scroll bar and a corresponding longitudinal scroll bar, annotation information which is transversely displayed in the corresponding subarea is adjusted through operating the transverse scroll bar, and annotation information which is longitudinally displayed in the corresponding subarea is adjusted through operating the longitudinal scroll bar.
5. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-4.
6. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-4.
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| CN111831279A (en) * | 2019-04-22 | 2020-10-27 | 华为技术有限公司 | Interface code generation method and device |
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| CN111814449A (en) * | 2020-07-10 | 2020-10-23 | 泰康保险集团股份有限公司 | Form analysis method, device, equipment and storage medium |
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| CN112817592A (en) * | 2021-01-26 | 2021-05-18 | 四川天翼网络服务有限公司 | Automatic code generation method based on entity annotation |
| CN114138270A (en) * | 2021-12-14 | 2022-03-04 | 中国平安财产保险股份有限公司 | User interface display method and device, equipment and storage medium |
| CN115714653A (en) * | 2022-11-03 | 2023-02-24 | 中国农业银行股份有限公司 | Annotation-based authentication method, device, equipment and storage medium |
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