CN116501389A - Instruction buffer unit, processor and computer system - Google Patents
Instruction buffer unit, processor and computer system Download PDFInfo
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- CN116501389A CN116501389A CN202310774475.5A CN202310774475A CN116501389A CN 116501389 A CN116501389 A CN 116501389A CN 202310774475 A CN202310774475 A CN 202310774475A CN 116501389 A CN116501389 A CN 116501389A
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- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to the technical field of processors, and discloses an instruction buffer unit, a processor and a computer system, wherein the instruction buffer unit comprises a main buffer, a first crossbar matrix connected with the input end of the main buffer, a second crossbar matrix connected with the output end of the main buffer, a public buffer, a third crossbar matrix connected with the input end of the public buffer and a fourth crossbar matrix connected with the output end of the public buffer; the third crossbar is further connected to an input of the main buffer, and the fourth crossbar is further connected to an output of the main buffer. The instruction buffer unit can store the public information corresponding to the instruction information into the public buffer, so that the main buffer only needs to store the instruction information and the corresponding public buffer read pointer, and does not need to store the complete information of the instruction information, thereby reducing the design area and the power consumption of the main buffer.
Description
Technical Field
The present invention relates to the field of processor technologies, and in particular, to an instruction buffer unit, a processor, and a computer system.
Background
Processors are the primary computational components in computer systems that are responsible for executing instructions and performing arithmetic and logical operations, and with the continued development of computer technology, the performance and functionality of processors have also been greatly improved.
Processors are largely classified into Reduced Instruction Set (RISC) processors, which can achieve efficient instruction processing using a simple instruction set, and Complex Instruction Set (CISC) processors, which support more complex instructions and higher level operations.
The simplified pipeline structure of the superscalar processor in the related art is shown in fig. 1, and is mainly divided into five units, namely a fetching unit, a branch prediction unit, an instruction buffer unit, a decoding unit and an execution unit, wherein the fetching unit is responsible for fetching instruction information to be executed from a memory in a cache line (cache) unit in each cycle, and transmitting program counter information corresponding to the instruction information and exception handling information to a lower unit; the branch prediction unit is used for predicting an instruction of a branch type by a cache line unit, fetching and executing the instruction in advance by removing the correct instruction stream position, and packaging the predicted result into branch prediction information to be transmitted to a lower-level unit together with the value unit; the instruction buffer unit is responsible for protecting instruction information and other related information fetched by the access value unit and balancing instruction throughput gap between the access value unit and the decoding unit; the decoding unit is responsible for decoding the fetched instruction information to obtain operands, and transmitting relevant information thereof to the execution unit for execution and obtaining a result.
The instruction buffer unit in the related art is a key component in the processor and mainly plays a role of storing and scheduling instructions, the structure of the instruction buffer unit in the related art is shown in fig. 2, the main body of the instruction buffer unit is composed of two crossbar matrixes and a main buffer, wherein the main buffer structure is a first-in first-out (FIFO) queue, when the processor runs, a front-stage instruction fetching unit sequentially stores a plurality of pieces of fetched instruction information, corresponding program counter information and exception handling information in the main buffer of the instruction buffer unit together with branch prediction information transmitted by a branch prediction unit, and at the outlet of the instruction buffer unit, each cycle transmits a certain number of instructions to a rear-stage processing unit according to the residual instruction quantity of the current instruction buffer unit.
In the high-performance superscalar processor, each storage unit of the main buffer of the instruction buffer unit stores basic instruction information and program counter information, and also stores branch prediction information, exception handling information generated by a pre-stage module of the pipeline, and the like, as shown in a schematic diagram of the storage unit of the main buffer in fig. 3. The Program Counter (Program Counter) information records a Program Counter value corresponding to the instruction, namely, an address of the current execution instruction of the processor is saved, and the instruction information is the content of the current instruction; the branch prediction information represents the branch prediction information transmitted by the branch prediction unit in cache line units, and comprises a predicted jump instruction bit and a predicted jump address (i.e. a program counter value after jump); exception handling information includes exception information generated when instructions are executed in a pre-pipeline, which relates to processor architecture and design, and generally includes instruction address misalignment exceptions, page miss exceptions, and the like.
In summary, in the related art, each storage unit in the main buffer of the instruction buffer unit stores complete information of a single instruction information, such as program counter information, instruction information, branch prediction information and exception handling information, but in the front stage of the processor, the program counter information, branch prediction information and exception handling information transmitted from the instruction fetch unit and branch prediction are generated in cache line units, except for the instruction information; that is, for program counter information, the instruction packet transmitted from each cycle instruction fetch unit must be in a cache line, so the cache line offset information of the program counter must be the same, and for branch prediction information and exception handling information, the processor will jump to the corresponding program counter address for valid branch instructions and exception conditions to continue execution without following the original program counter flow, so that the branch prediction information and exception handling information in cache line units only contains only one valid branch instruction/exception handling information. Therefore, the program counter information, the branch prediction information, and the exception handling information are common information for all instructions in each cache line for the main buffer, but in the structure of the main instruction buffer unit of the related art, the information is redundantly stored in each storage unit of the main buffer, resulting in waste of area and power consumption in its design.
Disclosure of Invention
The invention aims to provide an instruction buffer unit, a processor and a computer system, which are used for solving the problem that the instruction buffer unit in the related art stores instruction information, corresponding program counter information, branch prediction information and exception handling information in a single main buffer redundantly, so that the waste of the design area and the power consumption is caused.
To solve the above technical problem, in a first aspect, the present invention provides an instruction buffer unit, which includes a main buffer, a first crossbar matrix connected to an input terminal of the main buffer, a second crossbar matrix connected to an output terminal of the main buffer, a common buffer, a third crossbar matrix connected to an input terminal of the common buffer, and a fourth crossbar matrix connected to an output terminal of the common buffer; the third cross switch matrix is also connected with the input end of the main buffer, and the fourth cross switch matrix is also connected with the output end of the main buffer;
the main buffer is used for controlling the first crossbar matrix to map instruction information and corresponding public buffer read pointers thereof to the main buffer through a main buffer write pointer; the common buffer is used for controlling the third crossbar matrix to map common information corresponding to the instruction information to the common buffer through a common buffer write pointer;
the main buffer is also used for controlling the second crossbar matrix to output the instruction information and the corresponding public buffer read pointer through the main buffer read pointer; and the public buffer is also used for controlling the fourth crossbar matrix to output the public information corresponding to the instruction information through the output public buffer read pointer.
Preferably, the main buffer includes a plurality of first storage units; each of the instruction information and its corresponding common buffer read pointer are mapped to one of the first memory locations.
Preferably, the common buffer includes a plurality of second storage units; each of the common information corresponding to the instruction information is mapped to one of the second storage units.
Preferably, the structure of the main buffer is a first-in first-out queue.
Preferably, the common information includes program count information, branch prediction information, and exception handling information.
In a second aspect, the present invention provides a processor, which includes a fetch unit, an instruction buffer unit as described above, a branch prediction unit connected to a second input of the instruction buffer unit, a decoding unit connected to an output of the instruction buffer unit, and an execution unit connected to an output of the decoding unit, where a first input of the instruction buffer unit is connected to the fetch unit;
the instruction fetching unit is used for taking out instruction information to be executed from the memory in a cache line unit in each period, and transmitting program counter information corresponding to the instruction information and exception handling information to the instruction buffer unit; the branch prediction unit is used for predicting an instruction of a branch type by using a cache line unit, fetching and executing the instruction in advance by removing the correct instruction stream position, and packaging the predicted result into branch prediction information to be transmitted to the instruction buffer unit; the decoding unit is used for decoding the fetched instruction information to obtain an operand and transmitting the operand to the execution unit; the execution unit is used for executing the instruction information and obtaining a result.
In a third aspect, the invention provides a computer system comprising a processor as described above.
Compared with the related art, the instruction buffer unit in the invention maps the instruction information and the corresponding public buffer read pointer thereof to the main buffer by additionally arranging the public buffer, and simultaneously maps the public information corresponding to the instruction information to the public buffer, so that the public information corresponding to the instruction information can be stored in the public buffer, the main buffer only needs to store the instruction information and the corresponding public buffer read pointer thereof, the whole information of the instruction information is not needed to be stored, the area of the instruction buffer is greatly reduced, and the design area and the power consumption of the instruction buffer are reduced.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic diagram of a pipeline architecture of a superscalar processor provided in the related art;
FIG. 2 is a schematic diagram of an instruction buffer unit according to the related art;
FIG. 3 is a schematic diagram of a memory cell structure of a main buffer according to the related art;
FIG. 4 is a schematic diagram of an instruction buffer unit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a memory cell structure of a main buffer according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a memory cell structure of a common buffer according to an embodiment of the invention.
100, an instruction buffer unit; 1. a main buffer; 11. a first storage unit; 2. a first crossbar matrix; 3. a second crossbar matrix; 4. a common buffer; 41. a second storage unit; 5. a third crossbar matrix; 6. and a fourth crossbar matrix.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The embodiment of the invention provides an instruction buffer unit 100, which is shown in connection with fig. 4 to 5, and comprises a main buffer 1, a first crossbar matrix 2 connected with an input end of the main buffer 1, a second crossbar matrix 3 connected with an output end of the main buffer 1, a common buffer 4, a third crossbar matrix 5 connected with an input end of the common buffer 4, and a fourth crossbar matrix 6 connected with an output end of the common buffer 4; the third crossbar 5 is also connected to the input of the main buffer 1, and the fourth crossbar 6 is also connected to the output of the main buffer 1.
The main buffer 1 is configured to control the first crossbar matrix 2 to map instruction information and its corresponding common buffer read pointer to the main buffer 1 through a main buffer write pointer; the common buffer 4 is configured to control the third crossbar matrix 5 to map common information corresponding to the instruction information to the common buffer 4 through a common buffer write pointer.
The main buffer 1 is further configured to control the second crossbar matrix 3 to output the instruction information and the corresponding common buffer read pointer thereof through a main buffer read pointer; the common buffer 4 is further configured to control the fourth crossbar matrix 6 to output the common information corresponding to the instruction information through the output common buffer read pointer.
The common information includes program count information, branch prediction information, and exception handling information.
The instruction information, the program count information and the exception handling information are input by a superior value unit, and the branch prediction information is input by superior branch prediction information.
In this embodiment, the structures of the main buffer 1 and the common buffer 4 are all first-in first-out queues, but the storage structure of the common buffer 4 is different from the storage structure of the main buffer 1.
In this embodiment, the main buffer 1 includes a plurality of first storage units 11; each of the instruction information and its corresponding common buffer read pointer is mapped to one of the first memory units 11.
Each instruction information and its corresponding common buffer read pointer are mapped sequentially and in turn into a plurality of the first memory units 11.
In this embodiment, the common buffer 4 includes a plurality of second storage units 41; the common information each corresponding to the instruction information is mapped to one of the second storage units 41.
The common information corresponding to the instruction information is sequentially mapped to the plurality of second storage units 41.
The design principle of the instruction buffer unit 100 in this embodiment is as follows: separately constructing a common buffer 4 in cache line units so as to store common information of each cache line instruction packet in cache line units; in this way, the main buffer 1 does not store redundant information any more, but only stores a pointer to a certain storage unit of the common buffer 4, so that it can read the corresponding storage unit of the common buffer 4 according to the position of the pointer when outputting, thereby obtaining corresponding information.
When the instruction information and the related information are output, the instruction information still controls the first crossbar matrix 2 to map the instruction information and the corresponding public buffer read pointer thereof to the corresponding position of the main buffer 1 through the main buffer write pointer in the information packet input by the value unit for storage, but the program counting information, the exception handling information and the branch prediction information input by the branch prediction unit are not input to the main buffer 1 any more, but the public information corresponding to the instruction information is mapped to the corresponding position of the public buffer 4 for storage through the public buffer write pointer control the third crossbar matrix 5; at the same time, the location in the common buffer 4 where the instruction information is stored, i.e. the read pointer corresponding to the common buffer 4, will also be stored in the main buffer 1.
When the instruction information and the related information thereof are input to the instruction buffer unit 100, the corresponding instruction information and the corresponding common buffer read pointer thereof are read from the corresponding position in the main buffer 1 according to the position of the main buffer read pointer, the read common buffer read pointer is used for reading the common information corresponding to the instruction information in the common buffer 4, and the common information and the previously read instruction information are packaged and then output to a decoding unit at a lower stage.
Compared with the related art, the instruction buffer unit 100 in the invention maps the instruction information and the corresponding public buffer read pointer thereof to the main buffer 1 by additionally arranging the public buffer 4, and maps the public information corresponding to the instruction information to the public buffer 4, so that the public information corresponding to the instruction information can be stored in the public buffer 4, the main buffer 1 only needs to store the instruction information and the corresponding public buffer read pointer thereof, and does not need to store the complete information of the instruction information, thereby greatly reducing the area of the instruction buffer, and reducing the area and the power consumption in design thereof, and being beneficial to reducing the area, the power consumption and the cost of a processor.
Example two
The present embodiment provides a processor, which is characterized in that the processor includes a fetch unit, an instruction buffer unit 100 as described in embodiment one, in which a first input end is connected to the fetch unit, a branch prediction unit connected to a second input end of the instruction buffer unit 100, a decoding unit connected to an output end of the instruction buffer unit 100, and an execution unit connected to an output end of the decoding unit.
The instruction fetching unit is configured to take out instruction information to be executed from the memory in a cache line unit in each cycle, and transmit program counter information corresponding to the instruction information and exception handling information to the instruction buffer unit 100; the branch prediction unit is configured to predict an instruction of a branch type in a cache line unit, fetch and execute the instruction in advance by going to a correct instruction stream position, and package a predicted result into branch prediction information to transmit the branch prediction information to the instruction buffer unit 100; the decoding unit is used for decoding the fetched instruction information to obtain an operand and transmitting the operand to the execution unit; the execution unit is used for executing the instruction information and obtaining a result.
Since the processor in this embodiment includes the instruction buffer unit 100 in the first embodiment, the technical effects achieved by the instruction buffer unit 100 in the first embodiment can be achieved, and the description thereof is omitted herein.
Example III
The present embodiment provides a computer system including a processor as described in the second embodiment. Because the computer system in this embodiment includes the processor in the second embodiment, the technical effects achieved by the processor in the second embodiment can also be achieved, which is not described herein.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (7)
1. An instruction buffer unit is characterized by comprising a main buffer, a first crossbar matrix connected with the input end of the main buffer, a second crossbar matrix connected with the output end of the main buffer, a public buffer, a third crossbar matrix connected with the input end of the public buffer and a fourth crossbar matrix connected with the output end of the public buffer; the third cross switch matrix is also connected with the input end of the main buffer, and the fourth cross switch matrix is also connected with the output end of the main buffer;
the main buffer is used for controlling the first crossbar matrix to map instruction information and corresponding public buffer read pointers thereof to the main buffer through a main buffer write pointer; the common buffer is used for controlling the third crossbar matrix to map common information corresponding to the instruction information to the common buffer through a common buffer write pointer;
the main buffer is also used for controlling the second crossbar matrix to output the instruction information and the corresponding public buffer read pointer through the main buffer read pointer; and the public buffer is also used for controlling the fourth crossbar matrix to output the public information corresponding to the instruction information through the output public buffer read pointer.
2. The instruction buffer unit of claim 1, wherein the main buffer comprises a plurality of first memory units; each of the instruction information and its corresponding common buffer read pointer are mapped to one of the first memory locations.
3. The instruction buffer unit of claim 1, wherein the common buffer comprises a plurality of second storage units; each of the common information corresponding to the instruction information is mapped to one of the second storage units.
4. The instruction buffer unit of claim 1, wherein the main buffer and the common buffer are each configured as a first-in-first-out queue.
5. The instruction buffer unit of claim 1, wherein the common information includes program count information, branch prediction information, and exception handling information.
6. A processor, characterized in that the processor comprises a fetch unit, an instruction buffer unit according to any of claims 1 to 5, a branch prediction unit connected to a second input of the instruction buffer unit, a decoding unit connected to an output of the instruction buffer unit, and an execution unit connected to an output of the decoding unit;
the instruction fetching unit is used for taking out instruction information to be executed from the memory in a cache line unit in each period, and transmitting program counter information corresponding to the instruction information and exception handling information to the instruction buffer unit; the branch prediction unit is used for predicting an instruction of a branch type by using a cache line unit, fetching and executing the instruction in advance by removing the correct instruction stream position, and packaging the predicted result into branch prediction information to be transmitted to the instruction buffer unit; the decoding unit is used for decoding the fetched instruction information to obtain an operand and transmitting the operand to the execution unit; the execution unit is used for executing the instruction information and obtaining a result.
7. A computer system comprising the processor of claim 6.
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| CN202310774475.5A CN116501389B (en) | 2023-06-28 | 2023-06-28 | Instruction buffer unit, processor and computer system |
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| CN202310774475.5A CN116501389B (en) | 2023-06-28 | 2023-06-28 | Instruction buffer unit, processor and computer system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117348933A (en) * | 2023-12-05 | 2024-01-05 | 睿思芯科(深圳)技术有限公司 | Processor and computer system |
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