CN116457919A - Tin oxide and tin carbide materials for semiconductor patterning applications - Google Patents

Tin oxide and tin carbide materials for semiconductor patterning applications Download PDF

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Publication number
CN116457919A
CN116457919A CN202180077490.3A CN202180077490A CN116457919A CN 116457919 A CN116457919 A CN 116457919A CN 202180077490 A CN202180077490 A CN 202180077490A CN 116457919 A CN116457919 A CN 116457919A
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layer
hard mask
patterned
substrate
silicon
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林永振
郎纪一
黃和湧
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Applied Materials Inc
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Applied Materials Inc
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

A method and apparatus for patterning semiconductor material using tin-based materials as mandrels, hard mask and liner materials is provided. One or more embodiments of the present disclosure use tin oxide and/or tin carbide materials as hard mask materials, mandrel materials, and/or liner materials during various patterning applications. Tin oxide or tin carbide materials relative to other highly selective materials such as metal oxides (e.g., tiO 2 、ZrO 2 、HfO 2 、Al 2 O 3 ) Is easier to peel off to avoid affecting critical dimensions and creating defects. In addition, tin oxide and tin carbide have low refractive indices, low k values, and are transparent below 663 nanometers for photolithographic coverage.

Description

Tin oxide and tin carbide materials for semiconductor patterning applications
Technical Field
Implementations described herein relate generally to film stacks and etching processes for etching film stacks with high selectivity and good profile control for patterning processes.
Background
The production of very large scale integration (very large scale integration; VLSI) and very large scale integration (ultralarge scale integration; ULSI) semiconductor devices involves the reliable production of submicron and smaller features. However, with the continued miniaturization of circuit technology, the size of circuit features (e.g., interconnects) and the size of the pitch place more demands on processing power. To further increase the element and interconnect density, multilevel interconnects of the technology core involve precise imaging and placement of high aspect ratio features such as vias and other interconnect structures. In addition, it is also sought to form sub-micron sized features and interconnects while reducing waste of intermediate materials such as resist and hard mask materials.
As feature sizes become smaller and smaller, the demand for higher aspect ratios (defined as the ratio of feature depth to feature width) steadily increases to 10:1 or even higher. It is a significant challenge to develop film stacks and etching processes that can reliably form features with such high aspect ratios. Inaccurate control or low resolution of the photolithographic exposure and development process may result in poor critical dimensions for transferring features to the various layers in the film stack, resulting in unacceptable line width roughness (line width roughness; LWR). Large Line Width Roughness (LWR) and improper twist profile can lead to inaccurate feature transfer to the film stack, ultimately leading to device failure and yield loss.
Furthermore, during etching of such film stacks, redeposition or accumulation of byproducts or other materials generated in the etching process may accumulate on the top and/or sidewalls of the features being etched, thereby disadvantageously blocking the openings of the features being formed in the material layer. Different materials selected for the film stack may result in different amounts or distribution of byproducts redeposited in the film stack. Furthermore, the reactive etchant is prevented from reaching the lower surface of the feature because the opening of the etched feature is narrowed and/or sealed by the cumulative redeposition of material, thus limiting the available aspect ratio. In addition, accumulation of redeposited material or byproducts may randomly and/or irregularly adhere to the top surfaces and/or sidewalls of the features being etched, and the resulting irregular profile and growth of redeposited material may alter the flow path of the reactive etchant, resulting in curved or distorted profiles of the features formed in the material layer. Inaccurate profiles or feature sizes can lead to device structural breakdown, ultimately leading to device failure and low product yields. Furthermore, poor etch selectivity to materials contained in the film stack can disadvantageously lead to inaccurate profile control, ultimately leading to component failure.
Accordingly, there is a need in the art for a suitable film stack and etching method for etching features in the film stack that have a target profile and small dimensions.
Disclosure of Invention
Implementations described herein relate generally to film stacks and etching processes for etching film stacks with high selectivity and good profile control for patterning processes.
In one aspect, a method of forming a feature on a substrate is provided. The method includes forming a mandrel (mandril) layer on a substrate, wherein the mandrel layer is a tin carbide layer or a tin oxide layer. The method further includes patterning the mandrel layer. The method further includes conformally forming a spacer layer on the patterned mandrel layer. The method further includes patterning the spacer layer.
Implementations may include one or more of the following. The patterned mandrel layer is selectively removed from the patterned spacer layer. Forming the mandrel layer on the substrate includes depositing the mandrel layer using a physical vapor deposition (physical vapor deposition PVD) process, a chemical vapor deposition (chemical vapor deposition; CVD) process, or an atomic layer deposition (atomic layer deposition; ALD) process. Patterning the mandrel layer includes supplying a first gas mixture including a halogen-containing gas and oxygen, and applying a first RF source power setting in the first gas mixture. The halogen-containing gas being selected from Cl 2 Gas, HBr gas, or a combination thereof. The first gas mixture further comprises a gas selected from N 2 、O 2 、COS、SO 2 Or a combination thereof. The spacer layer comprises a material different from the material of the mandrel layer and is selected from silicon oxide, silicon nitride, metal oxide, or polysilicon. A hard mask layer is formed on the mandrel. The hard mask layer comprises a material selected from the group consisting of polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material or combination of materials. The substrate comprises silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or a combination thereof.
In another aspect, a method of forming features on a substrate is provided. The method includes forming a hard mask layer on a film stack formed over a substrate, wherein the hard mask layer includes tin oxide or tin carbide. The method further includes supplying a first etching gas mixture to the substrate; and etching the hard mask layer to form a patterned hard mask layer.
Implementations may include one or more of the following. The method further includes supplying a second etching gas mixture to the substrate and etching the film stack exposed by the patterned hard mask layer. The film stack includes a plurality of dielectric layers. The film stack includes an oxide-nitride-oxide (ONO) layer. The film stack includes alternating layers of silicon and silicon germanium. The hard mask layer is selectively removed. The first etching gas mixture includes a halogen-containing gas. The halogen-containing gas being selected from Cl 2 Gas, HBr gas, or a combination of the foregoing. The first etching gas mixture further comprises N 2 、O 2 、COS、SO 2 Or a combination of the above materials.
In yet another aspect, a method of forming a feature on a substrate is provided. The method includes forming a patterned hard mask layer on a film stack formed over a substrate, wherein the patterned hard mask layer includes carbon. The method further includes supplying a first etching gas mixture to the substrate. The method further includes etching the film stack exposed by the hard mask layer to form a patterned film stack. The method further includes forming a liner layer over the patterned hard mask layer and the patterned film stack, wherein the liner layer comprises tin oxide or tin carbide.
Implementations may include one or more of the following. The liner layer is formed by an ALD process. The liner layer is exposed to wet chemicals or dry plasma to remove the liner layer. The patterned hard mask layer comprises amorphous carbon, diamond-like carbon, or a combination of the above materials. The film stack includes a plurality of dielectric layers. The film stack includes an oxide-nitride-oxide (ONO) layer. The film stack includes alternating layers of silicon and silicon germanium.
In another aspect, a non-transitory computer readable medium has instructions stored thereon that, when executed by a processor, cause the process to perform the operations of the apparatus and/or method described above.
Drawings
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
Fig. 1 illustrates a cross-sectional view of one example of a plasma processing chamber that may be used to perform an etching process in accordance with one or more embodiments of the present disclosure.
Fig. 2 illustrates a flow diagram of a method for performing a high aspect ratio feature patterning process in accordance with one or more embodiments of the present disclosure.
Figures 3A-3D illustrate various stages of a high aspect ratio feature patterning process in accordance with one or more embodiments of the present disclosure.
Fig. 4 illustrates a flow diagram of another method for performing a high aspect ratio feature patterning process in accordance with one or more embodiments of the present disclosure.
Fig. 5A-5D illustrate various stages of a high aspect ratio feature patterning process in accordance with one or more embodiments of the present disclosure.
Fig. 6 illustrates a flow diagram of another method for performing a high aspect ratio feature patterning process in accordance with one or more embodiments of the present disclosure.
Fig. 7A-7D illustrate various stages of a high aspect ratio feature patterning process in accordance with one or more embodiments of the present disclosure.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Detailed Description
The following disclosure describes the formation of high aspect ratio features. Certain details are set forth in the following description and in figures 1-7D to provide a thorough understanding of various embodiments of the present disclosure. Other details describing well-known structures and systems often associated with the formation of high aspect ratio features are not set forth in the following disclosure to avoid unnecessarily obscuring the description of the various embodiments. Furthermore, the device descriptions described herein are illustrative and should not be understood or construed as limiting the scope of the embodiments described herein.
Many of the details, operations, dimensions, angles, and other features shown in the figures are merely illustrative of particular embodiments. Thus, other embodiments may have other details, components, dimensions, angles, and features without departing from the spirit or scope of the present disclosure. Furthermore, further embodiments of the present disclosure may be practiced without several of the details described below.
Embodiments described herein relate generally to film stacking and etching processes for etching film stacks with high selectivity and good profile control for patterning processes. One of the present disclosureOr more embodiments by using tin oxide (e.g., snO 2 ) Or tin carbide (e.g., snC) materials advantageously provide improved material selectivity in high aspect ratio features. One or more embodiments of the present disclosure use tin oxide and/or tin carbide materials as hard mask materials, mandrel materials, and/or liner materials during various patterning applications. Due to the high young's modulus and non-volatile etch byproducts of tin oxide and tin carbide (e.g., snF 4 ) Some embodiments of the present disclosure thus improve poor selectivity of carbon, high density carbon, and diamond-like carbon materials during capacitor etching of materials used for memory applications (e.g., silicon oxide or silicon nitride). Tin oxide or tin carbide materials relative to other highly selective materials such as metal oxides (e.g., tiO 2 、ZrO 2 、HfO 2 、Al 2 O 3 ) Is easier to peel off to avoid affecting critical dimensions and creating defects. Tin oxide and tin carbide materials may be used for etch-back hard masks in memory applications because of the possibility of providing higher selectivity than carbon. In addition, tin oxide and tin carbide have low refractive indices, k values, and are transparent below 663 nanometers for photolithographic overlay. In addition, carbon, tin and SnO x (oxidation in air) can be easily removed by dry plasma etching or wet etchants, which helps provide precise critical dimension control for multiple patterning. Tin and tin oxide can be easily removed during chamber cleaning to reduce defects in the production process and also to increase chamber productivity.
Although the particular device in which the embodiments described herein may be implemented is not limited, it is sold by applied materials Inc. of Santa Clara, calif.)Implementation of these embodiments in an etching system is particularly beneficial. In addition, other available etching systems may also benefit from the embodiments described herein.
As used herein, "substrate" refers to a surface of a material, or a surface or portion of a material on which a film treatment is performed in a manufacturing process. For example, depending on the application, the substrate surface on which the process may be performed includes materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon on insulator (silicon on insulator; SOI), carbon doped silicon oxide, amorphous silicon, doped amorphous silicon, polysilicon, doped polysilicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, a semiconductor wafer. In addition to performing the film treatment directly on the surface of the substrate itself, in the present disclosure, any of the film treatment steps disclosed may also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlying layer as indicated above and below. Thus, for example, when a film/layer or a portion of a film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.
The substrate may be a silicon wafer, such as a 200 mm wafer, 300 mm wafer, or 450 mm wafer, including wafers having one or more layers of material, such as dielectric, conductive, or semiconductive materials deposited thereon. The patterned substrate may have "features," such as vias, openings, or contact holes, that are characterized by one or more narrow and/or re-enterable openings, constrictions within the features, and high aspect ratios. Features may be formed in one or more of the layers described above. One example of a feature is a hole or via in a semiconductor substrate or layer on a substrate. Another example is a trench in a substrate or layer. In some embodiments, the feature may have an underlying layer, such as a barrier layer or an adhesive layer. Non-limiting examples of the lower layer include dielectric layers and conductive layers such as silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers.
In some implementations, the type of substrate fabricated by performing the disclosed implementations may depend on the aspect ratio of the features on the substrate prior to performing the disclosed implementations. Aspect ratio is a comparison of feature depth to feature critical dimension (e.g., width/diameter). In some embodiments, features on the substrate may have an aspect ratio of at least about 2:1, at least about 3:1, at least about 4:1, at least about 6:1, at least about 10:1, at least about 20:1, or higher. The features may also have dimensions near the opening, such as an opening diameter or line width of between about 5 nanometers and 500 nanometers, such as between about 25 nanometers and about 300 nanometers.
One or more embodiments of the present disclosure generally provide structures that may be implemented in memory structures, including high aspect ratio structures formed by patterning dielectric materials. For example, high aspect ratio features formed in accordance with embodiments of the present disclosure may be memory type semiconductor elements, such as NAND type memory elements.
Fig. 1 is a simplified cross-sectional view of one example of a plasma processing chamber 100, the plasma processing chamber 100 being adapted to pattern a layer of material and form a layer of material disposed on a substrate 102 in the plasma processing chamber 100. The plasma processing chamber 100 is adapted to perform the etching processes described herein. One example of a plasma processing chamber 100 that may be adapted to benefit from the present disclosure isA processing chamber available from applied materials company located in santa clara, california. It is contemplated that other process chambers, including process chambers from other manufacturers, may be suitable for practicing embodiments of the present disclosure.
The plasma processing chamber 100 includes a chamber body 105 having a processing volume 101 defined therein. The chamber body 105 has sidewalls 112 and a bottom 118 that are coupled to a floor 126. The sidewall 112 has a liner 115 to protect the sidewall 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limited and may be proportionally larger than the dimensions of the substrate 102 to be processed therein. Examples of substrate dimensions include 200 mm diameter, 250 mm diameter, 300 mm diameter, 450 mm diameter, etc.
The chamber body 105 supports a chamber lid assembly 110 to enclose the process volume 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate access port 113 is formed through the sidewall 112 of the chamber body 105 to facilitate transfer of the substrate 102 into and out of the plasma processing chamber 100. The substrate access port 113 may be coupled to a transfer chamber and/or other chambers of a substrate processing system (not shown).
A pumping port 145 is defined in the chamber body 105 and is connected to the process volume 101. A pumping device (not shown) is coupled to the process volume 101 through a pumping port 145 to evacuate and control the pressure of the process volume 101. The pumping means may comprise one or more pumps and throttles.
The gas panel 160 is coupled to the chamber body 105 by a gas line 167 to supply process gases into the process volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may additionally include inert gases, non-reactive gases, and reactive gases. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, oxygen-containing gases, including O 2 、H 2 O、H 2 O 2 、O 3 、N 2 O、NO 2 The method comprises the steps of carrying out a first treatment on the surface of the Halogen-containing gases, including Cl 2 、HCl、HF、F 2 、Br 2 、HCl、HBr、SF 6 、NF 3 The method comprises the steps of carrying out a first treatment on the surface of the Passivation gas including nitrogen (N) 2 ) Carbonyl sulfide (COS) and sulfur dioxide (SO) 2 ) The method comprises the steps of carrying out a first treatment on the surface of the And inert gases including argon and helium. In addition, the process gas may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as BCl 3 、C 2 F 4 、C 4 F 8 、C 4 F 6 、CHF 3 、CH 2 F 2 、CH 3 F、NF 3 、NH 3 、CO 2 、SO 2 、CO、N 2 、NO 2 、N 2 O and H 2 Etc.
The valve 166 controls the flow of process gases from the sources 161, 162, 163, 164 from the gas panel 160 and is managed by the system controller 165. The gas flow supplied from the gas panel 160 to the chamber body 105 may comprise a combination of gases.
The chamber lid assembly 110 may include a nozzle 114. The nozzle 114 has one or more ports for introducing process gases from the sources 161, 162, 164, 163 of the gas panel 160 into the process volume 101. After the process gas is introduced into the plasma processing chamber 100, the gas is excited to form a plasma. An antenna 148, such as one or more inductive coils, may be disposed adjacent the plasma processing chamber 100. The antenna power supply 142 may provide power to the antenna 148 through the matching circuit 141 to inductively couple energy (e.g., radio frequency energy) to the process gas to maintain a plasma formed from the process gas in the process volume 101 of the plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, rf power may be capacitively coupled to the process gas using process electrodes below the substrate 102 and/or above the substrate 102 to sustain a plasma within the process volume 101. The operation of the antenna power supply 142 may be controlled by a controller, such as the system controller 165, which also controls the operation of other components in the plasma processing chamber 100.
A substrate support pedestal 135 is disposed in the processing volume 101 to support the substrate 102 during processing. The substrate support pedestal 135 may include an electrostatic chuck (electrostatic chuck; ESC) 122 for holding the substrate 102 during processing. The electrostatic chuck 122 holds the substrate 102 on the substrate support pedestal 135 using electrostatic attraction. The electrostatic chuck 122 is powered by a radio frequency power supply 125 integrated with a matching circuit 124. The electrostatic chuck 122 includes an electrode 121 embedded within a dielectric. The electrode 121 is coupled to a radio frequency power supply 125 and provides a bias voltage to the electrostatic chuck 122 and the substrate 102 thereon that attracts plasma ions formed from the process gas in the process volume 101. The rf power source 125 may be cycled on and off, or pulsed, during processing of the substrate 102. The electrostatic chuck 122 has an isolator 128 for reducing the attraction of the sidewall of the electrostatic chuck 122 to the plasma to extend the maintenance life cycle of the electrostatic chuck 122. In addition, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gases and to extend the maintenance interval of the plasma processing chamber 100.
In addition, electrode 121 is coupled to a power source 150. The power supply 150 provides a clamping voltage of about 200 volts to about 2,000 volts to the electrode 121. The power supply 150 may also include a system controller, such as system controller 165, for controlling the operation of the electrode 121 by directing a direct current to the electrode 121 to clamp and unclamp the substrate 102.
The electrostatic chuck 122 may include a heater disposed therein and connected to a power supply (not shown) for heating the substrate, and the cooling susceptor 129 supporting the electrostatic chuck 122 may include a conduit for circulating a heat transfer fluid to maintain the temperature of the electrostatic chuck 122 and the substrate 102 disposed thereon. The electrostatic chuck 122 is configured to operate within a temperature range specified by the thermal budget of the component being fabricated on the substrate 102. For example, the electrostatic chuck 122 may be configured to hold the substrate 102 at a temperature of-50 degrees celsius to about 250 degrees celsius, such as from about 25 degrees celsius to about 150 degrees celsius.
A cooling susceptor 129 is provided to help control the temperature of the substrate 102. To mitigate process drift and reduce time, the temperature of the substrate 102 may be maintained substantially constant by cooling the susceptor 129 throughout the time the substrate 102 is in the plasma processing chamber 100. In one embodiment, the temperature of the substrate 102 is maintained at-50 degrees celsius to about 250 degrees celsius, such as from about 25 degrees celsius to about 150 degrees celsius, throughout the etching process.
A cover ring 130 is disposed on the electrostatic chuck 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 is configured to confine the etching gas to a target portion of the exposed top surface of the substrate 102 while shielding the top surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins (not shown) are selectively moved through the substrate support pedestal 135 to lift the substrate 102 above the substrate support pedestal 135 to facilitate access to the substrate 102 by a transfer robot (not shown) or other suitable transfer mechanism.
The system controller 165 may be used to control the process sequence, adjust the flow of gases from the gas panel 160 into the plasma processing chamber 100, and other process parameters. When executed by the central processor, the software program converts the central processor into a special purpose computer (controller) that controls the plasma processing chamber 100, thereby performing processes in accordance with the present disclosure. The software routines may also be stored and/or executed by a second controller (not shown) that is collocated with the plasma processing chamber 100.
Fig. 2 shows a flow diagram of a method 200 for performing a high aspect ratio feature patterning process using a tin-based mandrel material in accordance with one or more embodiments of the present disclosure. Figures 3A-3D illustrate cross-sectional views of a film stack 300 at various stages of a high aspect ratio feature patterning process according to method 200. The mandrel material comprises tin oxide (e.g., snO 2 ) Or tin carbide (e.g., snC) materials. The method 200 may be used to form features with target critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory elements, as desired. Alternatively, the method 200 may be advantageously used to pattern other types of structures.
The method 200 begins with operation 210 by providing a film stack 300 having a patterned hard mask layer 330 disposed on a patterned mandrel layer 320, the film stack 300 being disposed on a substrate 310, as shown in fig. 3A. The patterned hard mask layer 330 may be patterned using a patterned photoresist layer (not shown) having defined openings that expose a portion of the hard mask layer for etching.
During operation 220, the patterned hard mask layer 330 is then used to form the patterned mandrel layer 320. The mandrel patterning process of operation 220 may be performed in a plasma processing chamber, such as plasma processing chamber 100 shown in fig. 1. The mandrel patterning process is performed by supplying a first gas mixture that selectively removes material of the mandrel layer at a higher rate than the material of the patterned hard mask layer 330 to form sidewalls 324 of the patterned mandrel layer 320. The first gas mixture supplied during the mandrel patterning process includes a reactive etchant for etching tin carbide or tin oxide material.
The first gas mixture may include a halogen-containing gas. The halogen-containing gas is selected from HBr, chlorine (Cl) 2 ) Gases containing carbon and fluorine (e.g. CF 4 、CHF 3 、C 4 F 8 ) Or a combination of the above materials. The first gas mixture may further comprise an oxygen-containing gas or H 2 . Oxygen-containing gas canSelected from the group consisting of O 2 、H 2 O、H 2 O 2 、O 3 、N 2 O、NO 2 CO or a combination of the above. The first gas mixture may further comprise a passivation gas. The passivation gas may be selected from the group consisting of nitrogen (N) 2 ) Sulfur dioxide (SO) 2 ) Carbonyl sulfide (COS), or a combination of the foregoing. The first gas mixture is configured to remove material from the mandrel layer to form sidewalls 324 of the patterned mandrel layer 320. Without being bound by theory, it is believed that the inclusion of a passivation gas helps to achieve the vertical etch profile of the sidewalls 324. In one particular example, the first gas mixture includes O 2 HBr and chlorine (Cl) 2 ) At least one/N of (2) 2 COS and SO 2 At least one of them.
When a first gas mixture is supplied to a plasma processing chamber, such as plasma processing chamber 100 shown in fig. 1, several process parameters are adjusted. In one embodiment, the chamber pressure in the presence of the first gas mixture is regulated. In one example, the process pressure in the etch chamber is adjusted from about 1 mtorr to about 80 mtorr, such as from about 3 mtorr to about 60 mtorr. A radio frequency source and bias power may be applied to sustain a plasma formed from the first gas mixture. For example, a radio frequency source power of from about 100 watts to about 3000 watts (from about 200 watts to about 1500 watts; from about 200 watts to about 1,000 watts; or from about 500 watts to about 3,000 watts) may be applied to the inductively coupled antenna source to maintain a plasma within the plasma processing chamber. The first gas mixture may be supplied while applying a radio frequency bias power of less than about 1500 watts (from about 40 watts to 400 watts, from about 150 watts to about 400 watts, or from about 500 watts to about 1,500 watts). The first gas mixture may flow into the chamber at a rate of about 50sccm to about 1,000 sccm. The temperature of the substrate may be maintained at about-50 degrees celsius to about 250 degrees celsius, for example about-20 degrees celsius to about 80 degrees celsius.
The rf source and bias power range may be varied while the first gas mixture is supplied so as to primarily remove portions of the mandrel layer. For example, when the first gas mixture is supplied, the RF source power may be adjusted up, for example, from a first RF source power setting to a second RF source power setting, and the RF bias power may be adjusted down, for example, from the first RF bias power setting to the second RF bias power setting, as desired. In one example, after the first rf source and bias power setting has been performed for a period of time from about 5 seconds to about 20 seconds, the first rf source and bias power setting may be transitioned to the second rf source and bias power setting to continue the patterning process. In one example, the second rf source power setting is from about 30% to about 80% higher than the first rf source power setting. The second bias power setting may be from about 30% to about 70% lower than the first bias power setting.
In one particular example, the first RF source power is set from about 500 watts to about 600 watts, and the first RF bias power is set from about 50 watts to about 150 watts. The second rf source power is set at about 700 watts to about 900 watts and the second rf bias power is set at about 20 watts to about 100 watts.
In some embodiments, the patterned hard mask layer 330 may be a first type of dielectric layer selected from the group consisting of polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material. In one particular example, the first type of dielectric layer selected to form the patterned hard mask layer 330 is a carbon-containing layer, such as amorphous carbon, diamond-like carbon, siOC, or the like. In some embodiments where the mandrel material is tin oxide, the hard mask layer 330 may include a carbon-based film (e.g., a spin-on carbon film, an amorphous carbon film, a carbon-based photoresist, an extreme ultraviolet (extreme ultraviolet; "EUV") photoresist material, a dielectric material (e.g., siO, siN, siON, siOCN or SiOC), and a silicon-containing film (e.g., silicon or polysilicon film).
Patterned mandrel layer 320 comprises a different material than patterned hard mask layer 330. Patterned mandrel layer 320 is tin-containing A material. In one example, the patterned mandrel layer 320 is a tin oxide layer (e.g., snOx, snO, or SnO 2 ). In another example, patterned mandrel layer 320 is a tin carbide layer (e.g., sn-C or Sn (C) including Sn-Sn, sn-C, and/or C-C bonds). Without being bound by theory, however, it is believed that the strong bond of sn—c helps maintain the vertical profile of the sidewalls 324 of the patterned mandrel layer 320. Patterned mandrel layer 320 may be formed by any suitable deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable deposition technique. The patterned mandrel layer 320 is used to pattern subsequently deposited spacer material. In one example, the thickness of the patterned mandrel layer 320 is between about 5 nanometers and about 200 nanometers, such as from about 40 nanometers to about 100 nanometers.
In some embodiments, as shown in fig. 3B, after forming patterned mandrel layer 320, patterned hard mask layer 330 is removed. In some embodiments, patterned hard mask layer 330 remains on patterned mandrel layer 320 and may be removed later. In some embodiments, the patterned hard mask layer 330 is consumed in patterning the patterned mandrel layer 320.
In some embodiments, the substrate 310 may include a dielectric layer, a dual damascene structure, or any suitable material for forming a contact layer. Suitable examples of dielectric layers include carbon-containing silicon oxide (SiOC), tetraethyl orthosilicate (TEOS), thermal silicon oxide, polymeric materials such as polyamides, SOG, USG, silicon oxide, silicon nitride (e.g., siNx), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbide, boron Nitride (BN), high-k dielectrics including, for example, hafnium oxide (e.g., hfOx, hfO) 2 ) Alumina (e.g. Al x O y 、Al 2 O 3 ) Zirconium oxide (ZrO) 2 ) Titanium oxide or a combination of the above materials. In one example, the substrate 310 includes silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or a combination thereof.
In operation 230, a spacer layer 340 is formed over the substrate 310 and the patterned mandrel layer 320, as shown in fig. 3B. Spacer layer 340 is formed of a different material than patterned mandrel layer 320 and substrate 310. In some embodiments, spacer layer 340 comprises a material different from the material of patterned mandrel layer 320 and is selected from silicon oxide, silicon nitride, metal oxide, or polysilicon. In one example, spacer layer 340 is a doped silicon-containing layer, such as a boron doped silicon material, a phosphorus doped silicon, or other suitable group III, IV, or V doped silicon material. In one example, spacer layer 340 is a boron doped silicon layer.
In some embodiments, spacer layer 340 is formed by a chemical vapor deposition process. Note that spacer layer 340 may be formed by any suitable deposition process, such as plasma enhanced chemical vapor deposition, atomic layer deposition, sub-atmospheric chemical vapor deposition, high density plasma chemical vapor deposition, spin coating, or other suitable deposition technique. In one example, spacer layer 340 has a thickness from about 5 nanometers to about 25 nanometers.
In one example, spacer layer 340 is conformally formed on patterned mandrel layer 320 conformally lining top surface 322 and sidewalls 324 of patterned mandrel layer 320. It is believed that spacer layer 340 may provide good etch selectivity during subsequent patterning processes such that a good profile of spacer layer 340 may be obtained as desired after the patterning process.
At operation 240, the spacer layer 340 is patterned, as shown in fig. 3C. The spacer patterning process of operation 240 may be performed in a plasma processing chamber, such as plasma processing chamber 100 shown in fig. 1. The patterning process is performed by supplying a second gas mixture that is capable of selectively removing portions of the spacer layer 340 with a target directionality so that certain portions of the spacer layer 340 (e.g., sidewalls 342) may remain on the substrate 310 and have a target profile to form the spacer structure 350. In one example, the second gas mixture supplied during the spacer patterning process may include a reactive etchant for anisotropically etching the silicon-containing material from the spacer layer 340, particularly for anisotropically etching the doped silicon-containing material.
In some embodiments of the present invention, in some embodiments,the second gas mixture comprises a halogen-containing gas selected from HBr, chlorine (Cl) 2 ) Boron trichloride (BCl) 3 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride gas (SF) 6 ) Gases containing carbon and fluorine, e.g. CF 4 、CHF 3 、C 4 F 8 Or a combination of the above. In one example, the second gas mixture includes HBr and chlorine (Cl) for etching the spacer layer 340 2 ). The second gas mixture is configured to remove the top and bottom of the spacer layer 340 without significantly eroding the sidewalls 342 of the spacer layer 340. In one example, the etching of spacer layer 340 results in a substantially square top surface of spacer structure 350.
When the second gas mixture is supplied into the plasma processing chamber, several processing parameters are adjusted. In one embodiment, the chamber pressure in the presence of the second gas mixture is regulated. In one example, the process pressure in the plasma processing chamber is adjusted from about 1 mtorr to about 80 mtorr, such as from about 3 mtorr to about 60 mtorr. A radio frequency source and bias power may be applied to sustain a plasma formed from the second gas mixture. For example, from about 100 watts to about 3000 watts of radio frequency source power (from about 200 watts to about 1500 watts, from about 200 watts to about 1,000 watts, or from about 500 watts to about 3,000 watts) may be applied to the inductively coupled antenna source to maintain a plasma within the plasma processing chamber. During the supply of the second gas mixture, a radio frequency bias power of less than about 1500 watts (from about 40 watts to 400 watts, from about 150 watts to about 400 watts, or from about 500 watts to about 1,500 watts) may be applied. The second gas mixture may flow into the chamber at a rate of about 50sccm to about 1,000 sccm. The temperature of the substrate may be maintained at about-50 degrees celsius to about 250 degrees celsius, for example about-20 degrees celsius to about 80 degrees celsius.
The rf source and bias power range may be varied while the second gas mixture is supplied so as to primarily remove portions of the spacer layer 340. For example, when the second gas mixture is supplied, the RF source power may be adjusted up, e.g., from a first RF source power setting to a second RF source power setting, while the RF bias power is adjusted down (e.g., from the first RF bias power setting to the second RF bias power setting) as desired. In one example, after the first rf source and bias power setting has been performed for a period of time between about 5 seconds and about 20 seconds, the first rf source and bias power setting may be transitioned to the second rf source and bias power setting to continue the spacer patterning process. In one example, the second rf source power setting is about 30% to about 80% higher than the first rf source power setting. The second bias power setting is about 30% to about 70% lower than the first bias power setting.
In one example, the first RF source power is set at about 500 watts to about 600 watts and the first RF bias power is set at about 50 watts to about 150 watts. The second rf source power is set at about 700 watts to about 900 watts and the second rf bias power is set at about 20 watts to about 100 watts.
At operation 250, the patterned mandrel layer 320 is removed to form a spacer structure 350 as shown in fig. 3D. The etch chemistry used to remove patterned mandrel layer 320 may be selected based on the materials used to form patterned mandrel layer 320 and spacer layer 340.
In one example, the spacer patterning process may include one or more processing stages. For example, after the second gas mixture is supplied to primarily remove the top and bottom of the spacer layer 340, a third gas mixture is supplied to primarily remove the patterned mandrel layer 320. The third gas mixture may include O 2 、H 2 、H 2 /N 2 、Cl 2 、HBr、H 2 O、H 2 O 2 Or combinations of the above materials and/or a carrier gas, e.g. N 2 He, ar, etc. The third gas mixture may comprise an oxygen-containing gas mixture and/or a carrier gas, such as N 2 He, ar, etc. In one example, carbon and fluorine containing gases, such as CH, may also be used as desired 2 F 2 、CF 4 Etc. In one example, the second gas mixture includes O 2 N 2 Or O 2 、N 2 CH (CH) 2 F 2 。
When the third gas mixture is supplied into the plasma processing chamber, several processing parameters may be adjusted. In one embodiment, the chamber pressure is adjusted in the presence of the third gas mixture. In one example, the process pressure in the plasma processing chamber is adjusted from about 1 mtorr to about 80 mtorr, such as from about 3 mtorr to about 60 mtorr. A radio frequency source and bias power may be applied to sustain a plasma formed from the third gas mixture. For example, from about 100 watts to about 3000 watts of radio frequency source power (from about 200 watts to about 1500 watts, from about 200 watts to about 1,000 watts, or from about 500 watts to about 3,000 watts) may be applied to the inductively coupled antenna source to maintain a plasma within the plasma processing chamber. A radio frequency bias power of less than about 1500 watts (from about 40 watts to 400 watts; from about 150 watts to about 400 watts; or from about 500 watts to about 1,500 watts) may be applied while supplying the third gas mixture. The third gas mixture may flow into the chamber at a rate of about 50sccm to about 1,000 sccm. The temperature of the substrate may be maintained at about-50 degrees celsius to about 250 degrees celsius, for example about-20 degrees celsius to about 80 degrees celsius. The spacer structure 350 may be subjected to further processing.
Implementations using a tin-based mandrel may include one or more of the following potential advantages. Because of the strong bond of tin-carbon, the tin-carbon mandrel maintains a vertical profile even at small dimensions (e.g., less than 10 nanometers). Carbon, tin or SnOx (oxidation in air) can be easily removed by dry plasma etching or wet etchants, which provides precise critical dimension control for multiple patterning.
Fig. 4 shows a flow chart of another method 400 for etching a film stack 500 having a tin-based hard mask layer 530. Fig. 5A-5D illustrate cross-sectional views of a film stack 500 at various stages of a high aspect ratio feature patterning process according to method 400. The method 400 may be used to form features having target critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory elements, as desired. Alternatively, the method 400 may be advantageously used to etch other types of structures.
The method 400 begins at operation 410 with providing a film stack 500 having a hard mask layer 530, the hard mask layer 530 disposed on a plurality of layers 520 on a substrate 510, as shown in fig. 5A.
The hard mask layer 530 includes tin oxide (SnO ) as described herein 2 ) Or tin carbide (SnC). In some embodiments, the plurality of layers 520 includes a plurality of dielectric layers. In one example, the plurality of dielectric layers includes alternating oxide-nitride-oxide (ONO) layers. In another embodiment, the plurality of layers 520 includes alternating layers of silicon and silicon germanium.
In some embodiments, the hard mask layer 530 has a patterned photoresist layer 540 disposed thereon, as shown in fig. 5A. Patterned photoresist layer 540 may be a positive photoresist and/or a negative photoresist capable of undergoing a chemical amplification reaction. In one example, the patterned photoresist layer 540 is a polymeric organic material suitable for EUV lithography processes. In one or more examples, patterned photoresist layer 540 includes at least one metallic element selected from tin, tantalum, indium, gallium, zirconium, zinc, any alloy of the above materials, or any combination of the above materials. The metal element included in the patterned photoresist layer 540 may change the light absorption efficiency during the photolithography exposure process as desired.
A patterned photoresist layer 540 is disposed on the hard mask layer 530. In some embodiments, the hard mask layer 530 is disposed on additional layers, such as a bottom anti-reflective coating (BARC) layer and/or an organic layer (not shown). The organic layer may comprise an organic material or a mixture of organic and inorganic materials.
The hard mask layer 530 to be formed in the film stack 500 includes a tin oxide or tin carbide material. The hard mask layer 530 may include a single layer or multiple layers. In the example shown in fig. 5A, the hard mask layer 530 is a single layer comprising, or formed from, tin oxide, tin carbide, or a combination of both. In one or more examples, the hard mask layer 530 has a thickness of about 10 angstroms to about 500 angstroms, such as about 20 angstroms to about 200 angstroms, such as about 50 angstroms to about 100 angstroms.
The hard mask layer 530 may be formed by any suitable deposition technique. In some embodiments, the hard mask layer 530 is formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition process.
In some embodiments, the hard mask layer 530 is formed by a chemical vapor deposition or physical vapor deposition process, and a carrier gas and/or an inert gas having a relatively high atomic weight, such as Xe or Kr, may be used during the plasma deposition process of the hard mask layer 530. The substrate temperature controlled during formation of the hard mask layer 530 may be controlled from about-50 degrees celsius to about 250 degrees celsius. Without being bound by theory, it is believed that relatively low substrate temperature control, e.g., less than 250 degrees celsius, in forming the hard mask layer 530 may facilitate forming the hard mask layer 530 at a relatively low deposition rate, thereby providing a relatively smooth surface to the film surface.
The substrate 510 may be any one of a semiconductor substrate, a silicon wafer, a glass substrate, and the like. The substrate 510 may be a material such as crystalline silicon (e.g., si <100> or Si <111 >), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned silicon on wafer insulators (silicon on insulator; SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 510 may have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameters, and may be a rectangular or square panel. Unless otherwise indicated, the examples described herein were performed on substrates having diameters of 200 mm, 300 mm or 450 mm.
During operation 420, an etching process is performed to pattern the hard mask layer 530, thereby forming a patterned hard mask layer 550, as shown in fig. 5B. The hard mask layer 530 may be patterned using a patterned photoresist layer 540 having defined openings 542, the openings 542 exposing a portion of the surface of the hard mask layer 530 for etching. The patterned hard mask layer 550 has defined openings or features 552 exposing a portion of the surface of the plurality of layers 520. Because the size of the openings 542 defined by the patterned photoresist layer 540 is small, e.g., less than 100 nanometers, the gas mixture and processing parameters used to etch the hard mask layer 530 are carefully selected to control the etching of the hard mask layer 530 with a good profile without damaging the underlying layers 520.
In one or more examples, the etching process of operation 420 is performed by supplying a first etching gas mixture into the plasma processing chamber while maintaining the temperature of the substrate support pedestal 135 from room temperature (e.g., about 23 degrees celsius) to up to about 150 degrees celsius.
In some embodiments, the first etching gas mixture includes at least one halogen-containing gas. The halogen-containing gas may include a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, or a combination of the foregoing. Suitable examples of halogen-containing gases include SF 6 、SiCl 4 、Si 2 Cl 6 、NF 3 、HBr、Br 2 、CHF 3 、CH 2 F 2 、CF 4 、C 2 F、C 4 F 6 、C 3 F 8 、HCl、C 4 F 8 、Cl 2 、HF、CCl 4 、CHCl 3 、CH 2 Cl 2 CH (CH) 3 Cl. In some examples, a silicon-containing gas may also be supplied in the first etching gas mixture. Suitable examples of silicon-containing gases include SiCl 4 、Si 2 Cl 6 、SiH 4 、Si 2 H 6 Etc. Further, examples of chlorine-containing gases include HCl, cl in particular 2 、CCl 4 、CHCl 3 、CH 2 Cl 2 、CH 3 Cl、SiCl 4 、Si 2 Cl 6 Etc., while examples of bromine-containing gases include HBr, br 2 Etc. A reactive gas, such as an oxygen-containing gas or a nitrogen-containing gas, e.g., O, may also be supplied to the first etching gas mixture as desired 2 、N 2 、N 2 O、NO 2 、O 3 、H 2 O or the like.
In some embodiments, the halogen-containing gas used to etch the hard mask layer 530 includes a chlorine-containing gas or a bromine-containing gas. When the first etching gas mixture is supplied into the plasma processing chamber, an inert gas may be supplied into the etching gas mixture to assist in profile control as desired. Examples of the inert gas supplied in the gas mixture include Ar, he, ne, kr, xe or the like.
In one example, a method for etching a hard maskThe first etching gas mixture of layer 530, such as tin oxide or tin carbide, includes HBr, cl 2 Ar, he or a combination of the above materials.
During operation 420, the chamber pressure of the first etching gas mixture is also adjusted. In some embodiments, the process pressure in the plasma processing chamber is adjusted from about 2 mtorr to about 100 mtorr, such as from about 3 mtorr to about 20 mtorr, such as about 6 mtorr. A radio frequency source or bias power may be applied to maintain a plasma formed in either a continuous mode or a pulsed mode, as desired, in the presence of the first etching gas mixture. For example, a radio frequency source power having a frequency of about 13.56 megahertz may be applied to the inductively coupled antenna source at an energy level of about 200 watts to about 1,000 watts, such as about 500 watts, to sustain a plasma within the plasma processing chamber. In addition, the RF bias power having a frequency of about 2 MHz to about 13.56 MHz may be applied at a power of less than 500 Watts, such as about 0 Watts to about 450 Watts, such as about 150 Watts.
In some embodiments, during the etching of operation 420, the rf bias power and the rf source power may be pulsed in the plasma processing chamber. The rf bias power and the rf source power may be pulsed into the plasma processing chamber either synchronously or asynchronously. In some examples, the rf bias power and the rf source power are pulsed asynchronously into the plasma processing chamber. For example, the RF source power may be pulsed to the process chamber prior to pulsing the RF bias power. For example, the RF bias power may be in a pulsed mode synchronized with the RF source power or have a time delay relative to the RF source power. In some examples, the rf source power and the rf bias power are pulsed between about 5% and about 75% of each duty cycle. For example, each duty cycle between each time unit is from about 0.1 milliseconds (ms) to about 10 ms.
In one example, the first etching gas mixture supplied at operation 220 includes O supplied into the chamber at a rate of about 0sccm to about 50sccm 2 And (3) gas. The first etching gas mixture further comprises a halogen-containing gas, such as HBr, supplied at a flow rate of from about 25sccm to about 250sccm, such as about 100 sccm. In one example, the halogen-containing gas includes a fluorine-containing gas. Fluorine-based etch chemistry to form SnF 4 Which is non-volatile to enhance selectivity during dielectric etching. SnF (SnF) 4 Or SnO 2 Removable by hydrogen plasma to form SnH 4 Or halogen-based plasmas (e.g. Cl 2 /HBr)。
After forming features 552 in the hard mask layer 530, a descumming or lift-off process may be performed to remove the remaining patterned photoresist layer 540.
At operation 430, further etching or patterning may be performed to continue transferring features 552 into the plurality of layers 520, thereby forming a patterned plurality of layers 560 having features 562 formed therein, as shown in FIG. 5C. In some embodiments, the etching or patterning of operation 430 is performed using the first gas mixture of operation 420. In other embodiments, the etching or patterning of operation 430 is performed using a second gas mixture that is different from the first gas mixture used during operation 420. The second gas mixture may be selected based on the type of material used to form the patterned hard mask 550 and the type of material used to form the plurality of layers 520.
At operation 440, a hard mask removal process may be performed to remove the patterned hard mask 550 from the patterned plurality of layers 560, as shown in fig. 5D. The lift-off process of operation 440 may be very selective with respect to silicon oxide and silicon nitride, which may result in no change in the critical dimensions of the patterned layers 520.
Implementations using a tin-based hard mask may include one or more of the following potential advantages. Fluorine-based etching chemistry to form non-volatile SnF 4 To improve selectivity during dielectric etching. SnF (SnF) 4 Or SnO 2 Can pass through H 2 Plasma removal to form SnH 4 Or halogen-based plasmas (e.g. Cl 2 /HBr). The tin-based hard mask film stripping process has high selectivity (post-ONO etch with no critical dimension change) relative to silicon oxide and silicon nitride. Or by wet chemicals (e.g. HCl, HNO 3 Or H 2 SO 4 ) Oxidation of tin is selectively removed.
Fig. 6 illustrates a flow diagram of a method 600 of performing a high aspect ratio feature patterning process with a tin-based liner material in accordance with one or more embodiments of the present disclosure. Figures 7A-7D illustrate cross-sectional views of a film stack 700 at various stages of a high aspect ratio feature patterning process according to method 600. The method 600 may be used to form features with target critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory elements, as desired. Alternatively, method 600 may be advantageously used to etch other types of structures.
The method 600 begins with operation 610 by providing a film stack 700 having a patterned hard mask layer 730 disposed on a plurality of layers 720, the plurality of layers 720 disposed on a substrate 710, as shown in fig. 7A. The patterned hard mask layer 730 may be patterned using a patterned photoresist layer (not shown) having defined openings that expose a portion of the hard mask layer for etching. The patterned hard mask layer 730 has defined openings or features 732 exposing a portion of the surface of the plurality of layers 720.
In one example, the patterned hard mask layer 730 may be a first type of dielectric layer selected from the group consisting of polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material. In one particular example, the first type of dielectric layer selected to form the patterned hard mask layer 730 is a carbon-containing layer, such as amorphous carbon, diamond-like carbon, siOC, or the like.
The patterned hard mask layer 730 may be formed using any suitable patterning process.
At operation 620, further etching or patterning may be performed to continue transferring features 732 into the plurality of layers 720, thereby forming a patterned plurality of layers 740 having features 742 formed therein, as shown in fig. 7B. The features 742 extend a feature depth from a top surface 744 of the patterned plurality of layers 740 to a bottom surface 746 of the features 742. The feature 742 has a width defined by at least one sidewall 748.
Any suitable etching or patterning process may be performed to form patterned plurality of layers 740. The etching or patterning of operation 620 may be performed using a gas mixture selected based on the type of material used to form the patterned hard mask layer 730 and the type of material used to form the plurality of layers 720. In some implementations, the etching or patterning of operation 620 is performed using a gas mixture and etching conditions similar to the first gas mixture and etching conditions of operation 420. In other embodiments, the etching or patterning of operation 620 is performed using a gas mixture and processing conditions that are different from the first gas mixture and etching conditions used during operation 420.
At operation 630, a liner layer 760 is formed over the patterned hard mask layer 730 (if present) and the patterned plurality of layers 740, as shown in fig. 7C. Liner layer 760 is a tin-based liner layer. Liner layer 760 comprises tin oxide, tin carbide, or a combination of the above. The liner layer 760 may be considered another spacer layer (e.g., a spacer-on-spacer scheme) that helps reduce the size of the openings 742 defined therebetween and as desired. Liner layer 760 may be formed by chemical vapor deposition, atomic layer deposition, or any other suitable deposition technique. In one example, liner layer 760 is a tin oxide or tin carbide layer formed by an atomic layer deposition process. Note that liner layer 760 as shown in fig. 7C is conformally formed over patterned hard mask layer 730 and patterned plurality of layers 740, conformally lining top surface 734 of patterned hard mask layer 730 and sidewalls 748 of patterned plurality of layers 740. The liner layer 760 further reduces the size of the features 742 defined between the sidewalls 748, which may further serve as a masking layer to transfer features to underlying or unpatterned portions of the patterned plurality of layers 740 in reduced small dimensions as desired. In one example, pad layer 760 has a thickness from about 1 nm to about 10 nm, such as from about 2 nm to about 5 nm.
At operation 640, another patterning process is performed to transfer features 742 to underlying or unpatterned portions of the patterned plurality of layers 740 to form reduced-size features 752 as shown in fig. 7D, as desired. During operation 640, a portion of liner layer 760 may be removed, for example, liner layer 760 formed on top surface 734 of patterned hard mask layer 730. The liner layer 760 and the unpatterned portions of the patterned plurality of layers 740 undergo anisotropic etching or patterning until features 752 are formed. The patterning process of operation 640 may be similar to the patterning process performed at operation 240. In some embodiments, operation 640 results in the top surface of the substrate 710 being exposed.
Implementations using tin-based liners may include one or more of the following potential advantages. The tin-based pad may reduce or prevent the dielectric via from bending in critical dimensions. The tin-based liner can be easily removed in a wet or dry plasma without damaging the critical dimensions of the feature.
The embodiments and all of the functional operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed in this specification and their structural equivalents, or in combinations of them. Embodiments described herein may be implemented as one or more non-transitory computer program products, such as one or more computer programs tangibly embodied in a machine-readable storage device, for execution by, or to control the operation of, data processing apparatus (e.g., a programmable processor, a computer, or multiple processors or computers).
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by, and apparatus may also be implemented as, special purpose logic circuitry, e.g., a field programmable gate array (field programmable gate array; FPGA) or an application specific integrated circuit (application specific integrated circuit; ASIC).
The term "data processing apparatus" includes all apparatuses, devices and machines for processing data, including for example a programmable processor, a computer or multiple processors or computers. In addition to hardware, the apparatus may include code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.
Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory elements; magnetic disks, such as internal hard disks or removable disks; magneto-optical disk; CD ROM and DVD-ROM discs. The processor and the memory may be supplemented by, or incorporated in, special purpose logic circuitry.
When introducing elements of the present disclosure, or the exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements.
The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (20)

1. A method of forming features on a substrate, comprising:
forming a mandrel layer on a substrate, wherein the mandrel layer is a tin carbide layer or a tin oxide layer;
Patterning the mandrel layer;
conformally forming a spacer layer on the patterned mandrel layer; a kind of electronic device with high-pressure air-conditioning system
The spacer layer is patterned.
2. The method of claim 1, further comprising:
the patterned mandrel layer is selectively removed from the patterned spacer layer.
3. The method of claim 1, wherein patterning the mandrel layer comprises:
supplying a first gas mixture comprising a halogen-containing gas and oxygen; a kind of electronic device with high-pressure air-conditioning system
A first rf source power setting is applied in the first gas mixture.
4. The method of claim 1, wherein the spacer layer comprises a material different from a material of the mandrel layer and is selected from silicon oxide, silicon nitride, metal oxide, or polysilicon.
5. The method of claim 1, wherein the mandrel layer has a hard mask layer formed thereon.
6. The method of claim 5, wherein the hard mask layer comprises a material selected from the group consisting of polysilicon, nanocrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, amorphous carbon, diamond-like carbon, titanium nitride, titanium oxide, titanium oxynitride, tantalum nitride, tantalum oxide, tantalum oxynitride, or any other suitable material or combination of materials.
7. The method of claim 1, wherein the substrate comprises silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or a combination thereof.
8. A method of forming features on a substrate, comprising:
forming a hard mask layer on a film stack formed over a substrate, wherein the hard mask layer comprises tin oxide or tin carbide;
supplying a first etching gas mixture to the substrate; a kind of electronic device with high-pressure air-conditioning system
The hard mask layer is etched to form a patterned hard mask layer.
9. The method of claim 8, further comprising:
supplying a second etching gas mixture to the substrate; a kind of electronic device with high-pressure air-conditioning system
The film stack exposed by the patterned hard mask layer is etched.
10. The method of claim 9, further comprising:
the hard mask layer is selectively removed.
11. The method of claim 8, wherein the first etching gas mixture comprises a halogen-containing gas.
12. The method of claim 3 or 11, wherein the halogen-containing gas is selected from the group consisting of Cl 2 Gas, HBr gas, or a combination of the foregoing.
13. The method of claim 9, wherein the first etching gas mixture further comprises a gas selected from the group consisting of N 2 、O 2 、COS、SO 2 Or a combination of the above materials.
14. A method of forming features on a substrate, comprising:
forming a patterned hard mask layer on a film stack formed over a substrate, wherein the patterned hard mask layer comprises carbon;
supplying a first etching gas mixture to the substrate;
etching the film stack exposed by the hard mask layer to form a patterned film stack; a kind of electronic device with high-pressure air-conditioning system
A liner layer is formed over the patterned hard mask layer and the patterned film stack, wherein the liner layer comprises tin oxide or tin carbide.
15. The method of claim 14, wherein the liner layer is formed by an atomic layer deposition process.
16. The method of claim 14, further comprising:
the liner layer is exposed to wet chemicals or dry plasma to remove the liner layer.
17. The method of claim 14, wherein the patterned hard mask layer comprises amorphous carbon, diamond-like carbon, or a combination thereof.
18. The method of claim 9 or 14, wherein the film stack comprises a plurality of dielectric layers.
19. The method of claim 18, wherein the film stack comprises an oxide-nitride-oxide (ONO) layer.
20. The method of claim 18, wherein the film stack comprises alternating layers of silicon and silicon germanium.
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