CN116434816A - Self-checking method and device for Flash memory built in chip and computer equipment - Google Patents
Self-checking method and device for Flash memory built in chip and computer equipment Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application relates to a self-checking method, a self-checking device, computer equipment and a storage medium of a Flash memory built in a chip, wherein the method comprises the following steps: the method comprises the steps that a chip is electrified, a Flash self-checking module is arranged in the chip, and Flash test is conducted by obtaining a configuration value generated by external hardware; judging whether the pin EN is 0, if EN=0, not performing Flash self-checking operation, and if EN=1, reading pin IO configuration information; judging whether a MODE pin is 0, if the mode=0, performing erasing/writing/reading/judging operation, if the mode=1, performing only reading/judging operation, and reading Flash information by a Flash self-checking module and performing CRC (cyclic redundancy check); judging a test result after the Flash self-test is finished, if the result is correct, pulling the DONE pin high to be 1, and if the result is incorrect, pulling the ERR pin high to be 1. The invention effectively improves the test efficiency and the test convenience of the Flash memory.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a self-checking method and apparatus for a Flash memory built in a chip, a computer device, and a storage medium.
Background
With the rapid development of the current mobile storage technology and the rapid expansion of the mobile storage market, the use amount of Flash type memories is rapidly increasing. In order to ensure long-term reliable operation of the chip, the Flash memory is tested at high speed and in detail before the product leaves the factory.
The Flash memory can only write the data in the memory cell from "1" to "0" and cannot write the data from "0" to "1", and if the operation of "0" - > "1" is to be realized, only the data of the whole sector or the whole memory can be erased, and the erasing operation takes a lot of time. In addition, the Flash memory has other characteristics, such as slow read-write speed, writing a status word before writing data, and being suitable for sequential read-write but not skip operation, which restrict the test of the Flash memory. However, in the prior art, a machine is required to issue a command through a jtag interface to test each function of a chip in sequence, and the Flash test occupies most of the time of the whole test, so that the whole test efficiency is low.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a self-checking method, device, computer device and storage medium for a Flash memory built in a chip.
A self-checking method of a Flash memory built in a chip comprises the following steps:
the method comprises the steps that a chip is electrified, a Flash self-checking module is arranged in the chip, and Flash test is conducted by obtaining a configuration value generated by external hardware;
judging whether the pin EN is 0, if EN=0, not performing Flash self-checking operation, and if EN=1, reading pin IO configuration information;
judging whether a MODE pin is 0, if the mode=0, performing erasing/writing/reading/judging operation, if the mode=1, performing only reading/judging operation, and reading Flash information by a Flash self-checking module and performing CRC (cyclic redundancy check);
judging whether an INFO pin is 0, if the INFO=0, performing read/write/page erase/full erase operation on the main storage area, and if the INFO=1, performing read/write/page erase operation on the information storage area and performing full erase operation on the main storage area and the information storage area;
judging whether the Data [3:0] pin code is 1 from the lowest bit in sequence, and if the bit is 1, executing a numerical operation corresponding to writing to Flash;
judging a test result after the Flash self-test is finished, if the result is correct, pulling the DONE pin high to be 1, and if the result is incorrect, pulling the ERR pin high to be 1.
In one embodiment, the step of determining whether the pin EN is 0, if en=0, then not performing Flash self-checking operation, and if en=1, then reading pin IO configuration information further includes:
when en=0, the upper computer can write the Flash self-checking module register through the jtag, so that Flash self-checking is enabled and configuration information is written.
In one embodiment, if mode=1 only performs the read/determine operation, the step of the Flash self-checking module reading the Flash information and performing the CRC check further includes:
comparing the read Flash information with the CRC value stored in the Flash, if the read Flash information and the CRC value are the same, performing Flash self-checking normally, and if the read Flash information and the CRC value are different, performing Flash self-checking incorrectly.
In one embodiment, the step of sequentially determining, from the lowest order bit, whether the Data [3:0] pin code is 1, and if the bit is 1, performing the writing of the corresponding numerical operation on Flash includes:
the Flash self-checking module starts to judge from the lowest bit of the Data [3:0] pin;
if the first bit is judged to be 1, writing by taking 0xFFFFFFFF as standard data and judging a result;
if the second bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0x55AA55AA as standard data and judging a result;
if the third bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0xAA55AA55 as standard data and judging a result;
if the fourth bit is judged to be 1, flash is erased again, and writing is performed by taking 0x00000000 as standard data, and a judgment result is obtained.
A self-test device for a Flash memory built in a chip, the device comprising:
the starting module is used for powering on a chip, and a Flash self-checking module is arranged in the chip and performs Flash test by acquiring a configuration value generated by external hardware;
the first judging module is used for judging whether the pin EN is 0, if EN=0, flash self-checking operation is not performed, and if EN=1, pin IO configuration information is read;
the second judging module is used for judging whether the MODE pin is 0, if MODE=0, erasing/writing/reading/judging operation is carried out, if MODE=1, only reading/judging operation is carried out, and the Flash self-checking module reads Flash information and carries out CRC check;
the third judging module is used for judging whether the INFO pin is 0, if the INFO is 0, performing read/write/page erase/full erase operation on the main storage area, and if the INFO is 1, performing read/write/page erase operation on the information storage area and performing full erase operation on the main storage area and the information storage area;
the fourth judging module is used for judging whether the Data [3:0] pin code is 1 from the lowest bit in sequence, and if the Data [3:0] pin code is 1, executing a numerical operation corresponding to the writing of Flash;
and the fifth judging module is used for judging a test result after the Flash self-test is finished, if the result is correct, pulling the DONE pin high to be 1, and if the result is incorrect, pulling the ERR pin high to be 1.
In one embodiment, the first determining module is further configured to:
when en=0, the upper computer can write the Flash self-checking module register through the jtag, so that Flash self-checking is enabled and configuration information is written.
In one embodiment, the second determining module is further configured to:
comparing the read Flash information with the CRC value stored in the Flash, if the read Flash information and the CRC value are the same, performing Flash self-checking normally, and if the read Flash information and the CRC value are different, performing Flash self-checking incorrectly.
In one embodiment, the fourth determining module is further configured to:
the Flash self-checking module starts to judge from the lowest bit of the Data [3:0] pin;
if the first bit is judged to be 1, writing by taking 0xFFFFFFFF as standard data and judging a result;
if the second bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0x55AA55AA as standard data and judging a result;
if the third bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0xAA55AA55 as standard data and judging a result;
if the fourth bit is judged to be 1, flash is erased again, and writing is performed by taking 0x00000000 as standard data, and a judgment result is obtained.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the methods described above when the computer program is executed.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
According to the self-checking method, the device, the computer equipment and the storage medium for the Flash memory built-in the chip, the Flash self-checking module is built in the chip, and the Flash self-checking module can perform Flash testing by acquiring the configuration value generated by external hardware, so that the whole Flash testing is completed by the chip hardware, the Flash correctness can be tested by using the Flash self-checking module without erasing Flash, the machine testing time is not occupied, and the testing efficiency is improved. Meanwhile, the Flash test configuration can be generated by external hardware without the configuration of a machine, and can also be configured by the machine through a jtag write register. In addition, if the test pins are packaged, the Flash test can be carried out through the pins after the chip leaves the factory, so that the test convenience is improved.
Drawings
FIG. 1 is a diagram of a architecture for a built-in Flash memory chip in one embodiment;
FIG. 2 is a flow chart of a self-checking method of a Flash memory built in a chip in one embodiment;
FIG. 3 is a flow chart of a self-checking method of a Flash memory built in a chip in another embodiment;
FIG. 4 is a block diagram of a self-test device with a Flash memory built in a chip in one embodiment;
fig. 5 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
At present, in the prior art, a machine is required to issue a command through a jtag interface to test each function of a chip in sequence, and the Flash test occupies most of the time of the whole test. The scheme completes the Flash test by the chip hardware, can be executed in parallel with other test items, does not occupy the test time of a machine, and greatly improves the test efficiency.
Specifically, refer to the architecture diagram of the built-in Flash memory chip shown in fig. 1. The chip internally comprises a Flash self-checking module, and Flash test is carried out according to the configuration value. The configuration value can be configured by a machine station through a jtag write Flash self-checking module register, and can also be pulled up/down to 1 or 0 through a pin IO.
The specific pin IO functions are described as follows:
1. MODE:0, performing erasing/writing/reading/judging operations; 1, only the read/judge operation is performed.
2、Data[3:0]：
xxx1: the FAT writes or judges by taking 0x00000000 as standard data;
xx1x, writing or judging by taking 0x55AA55AA as standard data;
x1xx, writing or judging by taking 0xAA55AA55 as standard data;
1xxx, and writing or judging by taking 0 xFFFFFFFFFF as standard data.
3. EN:0, not enabling FLASH automatic test; 1, enable.
4. INFO:0, performing operations such as reading, writing, page erasing, full erasing and the like on the main storage area; 1, performing operations such as reading, writing, page erasing and the like on an information storage area, and performing a full erasing operation on a main storage area and the information storage area.
5. Done=1 indicates that the test is complete.
6. Err=1 indicates a test abnormality.
It can be understood that the jumper cap or the switch can be used externally, and is connected with VDD to be 1 and GND to be 0; DONE and ERR can be connected with the LED lamp to display the test result. The Flash test is completed by the chip hardware, the machine test time is not occupied, the test pins are packaged, and the Flash test can be performed after the chip leaves the factory.
In one embodiment, as shown in fig. 2, a self-checking method of a Flash memory built in a chip is provided, and the method includes:
step 202, powering up a chip, wherein a Flash self-checking module is arranged in the chip, and Flash test is performed by acquiring a configuration value generated by external hardware;
step 204, judging whether the pin EN is 0, if en=0, not performing Flash self-checking operation, and if en=1, reading pin IO configuration information;
step 206, judging whether the MODE pin is 0, if mode=0, performing erasing/writing/reading/judging operation, if mode=1, performing only reading/judging operation, and the Flash self-checking module reads the Flash information and performs CRC check;
step 208, judging whether the INFO pin is 0, if info=0, performing read/write/page erase/full erase operation on the main storage area, if info=1, performing read/write/page erase operation on the information storage area, and performing full erase operation on the main storage area and the information storage area;
step 210, judging whether the Data [3:0] pin code is 1 from the lowest bit in sequence, and if the bit is 1, executing the corresponding numerical operation for Flash;
and step 212, judging a test result after the Flash self-test is finished, if the result is correct, pulling the DONE pin high to be 1, and if the result is incorrect, pulling the ERR pin high to be 1.
In this embodiment, a self-checking method of a Flash memory built in a chip is provided, a test chip architecture in the method is shown in fig. 1, and specific steps of the self-checking of the Flash memory of the chip are as follows:
firstly, powering up a chip, then judging an EN (enable) pin, and if EN=0, not performing Flash self-checking operation; if en=1, pin IO configuration information is read.
In one embodiment, the step of determining whether the pin EN is 0, if en=0, the Flash self-checking operation is not performed, and if en=1, the step of reading pin IO configuration information further includes: when en=0, the upper computer can write the Flash self-checking module register through the jtag, so that Flash self-checking is enabled and configuration information is written.
Specifically, it can be understood that when en=0, the upper computer can also write the Flash self-checking module register through the jtag, so as to enable Flash self-checking and writing configuration information.
Next, judge MODE pin: when information exists in the Flash, the CRC value is written in the Flash address finally. At this time, mode=1 only performs the read/judge operation, that is, the Flash self-checking module reads the Flash information and performs CRC check, and compares the read Flash information with the CRC value stored in Flash.
In one embodiment, if mode=1 only performs the read/judge operation, the step of the Flash self-checking module reading the Flash information and performing the CRC check further includes: comparing the read Flash information with the CRC value stored in the Flash, if the read Flash information and the CRC value are the same, performing Flash self-checking normally, and if the read Flash information and the CRC value are different, performing Flash self-checking incorrectly. Specifically, if the two are the same, the Flash self-checking is normal, and if the two are different, the Flash self-checking is wrong. When mode=0, the erasing/writing/reading/judging operation is performed.
Further judging the INFO pin to be 0, and performing operations such as reading, writing, page erasing, full erasing and the like on the main storage area; when the data is 1, the operations of reading, writing, page erasing and the like are carried out on the information storage area, and the total erasing operation is carried out on the main storage area and the information storage area.
Specifically, a general Flash has two storage areas, an information storage area and a main storage area. The information storage area stores configuration information of the chip, is set by a chip manufacturer and is not changed generally; the main memory area stores user programs and data, which can be operated by a user.
Further, data [3:0] is determined, and each bit code has a different written value, if the bit is 1, the numerical operation is written to Flash, and if the bit is 1111, four different numerical read-write operations are circularly executed.
And finally, finishing the operation of the Flash self-checking module, if the result is correct, pulling up the DONE pin to be 1, and if the result is wrong, pulling up the ERR pin to be 1. In addition, the operation result machine can also be obtained by reading the Flash self-checking module register through the jtag.
In the embodiment, the Flash self-checking module is arranged in the chip, and the Flash self-checking module can perform Flash test by acquiring the configuration value generated by external hardware, so that the whole Flash test is completed by the chip hardware, flash correctness can be tested by using the Flash self-checking module without erasing Flash, the machine test time is not occupied, and the test efficiency is improved. Meanwhile, the Flash test configuration can be generated by external hardware without the configuration of a machine, and can also be configured by the machine through a jtag write register. In addition, if the test pins are packaged, the Flash test can be carried out through the pins after the chip leaves the factory, so that the test convenience is improved.
In one embodiment, as shown in fig. 3, a self-checking method of a Flash memory with a built-in chip is provided, in the method, whether the pin code of Data [3:0] is 1 is sequentially judged from the lowest bit, and if the bit is 1, the step of executing the corresponding numerical operation on Flash includes:
step 302, the flash self-checking module starts to judge from the lowest bit of the Data [3:0] pins;
step 304, if the first bit is determined to be 1, performing writing with 0xFFFFFFFF as standard data and determining the result;
step 306, if the second bit is 1, re-erasing Flash, and executing writing by using 0x55AA55AA as standard data and judging the result;
step 308, if the third bit is 1, re-erasing Flash, and executing writing by using 0xAA55AA55 as standard data and judging the result;
in step 310, if the fourth bit is 1, flash is erased again, and writing is performed with 0x00000000 as standard data and the result is determined.
Specifically, the implementation procedure of the above steps is described as follows by way of an example:
if DATA [3:0] =0110, the Flash inspection module starts to judge from the lowest bit, and when judging that the second bit is 1, the Flash inspection module executes writing by taking 0x55AA55AA as standard DATA and judges the result; after the execution is finished, when the third bit is judged to be 1, flash is erased again, and the writing is performed by taking 0xAA55AA55 as standard data, and the result is judged.
If data=1111, 4 write operations are performed and the result is judged. It is worth to be noted that, in the execution process of the above steps, the Flash needs to be erased before each writing, then written again, and finally judged; this was cycled 4 times.
It should be understood that, although the steps in the flowcharts of fig. 1-3 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-3 may include multiple sub-steps or phases that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or phases are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or phases of other steps or other steps.
In one embodiment, as shown in fig. 4, there is provided a self-checking device 400 of a Flash memory built in a chip, the device comprising:
the starting module 401 is used for powering on a chip, wherein a Flash self-checking module is arranged in the chip, and Flash test is performed by acquiring a configuration value generated by external hardware;
the first judging module 402 is configured to judge whether the pin EN is 0, if en=0, the Flash self-checking operation is not performed, and if en=1, the pin IO configuration information is read;
a second judging module 403, configured to judge whether the MODE pin is 0, if mode=0, perform erasing/writing/reading/judging operations, if mode=1 only performs reading/judging operations, the Flash self-checking module reads Flash information and performs CRC check;
a third judging module 404, configured to judge whether the INFO pin is 0, if info=0, perform a read/write/page erase/full erase operation on the main storage area, and if info=1, perform a read/write/page erase operation on the information storage area, and perform a full erase operation on the main storage area and the information storage area;
a fourth judging module 405, configured to sequentially judge, from a least significant bit, whether the Data [3:0] pin code is 1, and if the bit is 1, execute a numerical operation corresponding to the write to Flash;
and a fifth judging module 406, configured to judge the test result after the Flash self-test is finished, pull the DONE pin high to 1 if the result is correct, and pull the ERR pin high to 1 if the result is incorrect.
In one embodiment, the first determining module 402 is further configured to:
when en=0, the upper computer can write the Flash self-checking module register through the jtag, so that Flash self-checking is enabled and configuration information is written.
In one embodiment, the second determining module 403 is further configured to:
comparing the read Flash information with the CRC value stored in the Flash, if the read Flash information and the CRC value are the same, performing Flash self-checking normally, and if the read Flash information and the CRC value are different, performing Flash self-checking incorrectly.
In one embodiment, the fourth determining module 405 is further configured to:
the Flash self-checking module starts to judge from the lowest bit of the Data [3:0] pin;
if the first bit is judged to be 1, writing by taking 0xFFFFFFFF as standard data and judging a result;
if the second bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0x55AA55AA as standard data and judging a result;
if the third bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0xAA55AA55 as standard data and judging a result;
if the fourth bit is judged to be 1, flash is erased again, and writing is performed by taking 0x00000000 as standard data, and a judgment result is obtained.
For specific limitation of the self-checking device of the Flash memory built in the chip, reference may be made to the limitation of the self-checking method of the Flash memory built in the chip hereinabove, and the description thereof will not be repeated here.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 5. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to realize a self-checking method of a Flash memory built in a chip.
It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method embodiments above when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the above method embodiments.
Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A self-checking method of a Flash memory built in a chip comprises the following steps:
the method comprises the steps that a chip is electrified, a Flash self-checking module is arranged in the chip, and Flash test is conducted by obtaining a configuration value generated by external hardware;
judging whether the pin EN is 0, if EN=0, not performing Flash self-checking operation, and if EN=1, reading pin IO configuration information;
judging whether a MODE pin is 0, if the mode=0, performing erasing/writing/reading/judging operation, if the mode=1, performing only reading/judging operation, and reading Flash information by a Flash self-checking module and performing CRC (cyclic redundancy check);
judging whether an INFO pin is 0, if the INFO=0, performing read/write/page erase/full erase operation on the main storage area, and if the INFO=1, performing read/write/page erase operation on the information storage area and performing full erase operation on the main storage area and the information storage area;
judging whether the Data [3:0] pin code is 1 from the lowest bit in sequence, and if the bit is 1, executing a numerical operation corresponding to writing to Flash;
judging a test result after the Flash self-test is finished, if the result is correct, pulling the DONE pin high to be 1, and if the result is incorrect, pulling the ERR pin high to be 1.
2. The self-checking method of a Flash memory built in a chip according to claim 1, wherein the step of determining whether the pin EN is 0, if en=0, the Flash self-checking operation is not performed, and if en=1, the step of reading pin IO configuration information further comprises:
when en=0, the upper computer can write the Flash self-checking module register through the jtag, so that Flash self-checking is enabled and configuration information is written.
3. The self-checking method of a Flash memory built in a chip according to claim 2, wherein if mode=1 only performs the reading/judging operation, the step of the Flash self-checking module reading the Flash information and performing the CRC check further comprises:
comparing the read Flash information with the CRC value stored in the Flash, if the read Flash information and the CRC value are the same, performing Flash self-checking normally, and if the read Flash information and the CRC value are different, performing Flash self-checking incorrectly.
4. The self-checking method of Flash memory built-in chip according to claim 3, wherein said step of sequentially determining from the lowest bit whether the Data [3:0] pin code is 1, and if the bit is 1, performing a numerical operation corresponding to writing to Flash comprises:
the Flash self-checking module starts to judge from the lowest bit of the Data [3:0] pin;
if the first bit is judged to be 1, writing by taking 0xFFFFFFFF as standard data and judging a result;
if the second bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0x55AA55AA as standard data and judging a result;
if the third bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0xAA55AA55 as standard data and judging a result;
if the fourth bit is judged to be 1, flash is erased again, and writing is performed by taking 0x00000000 as standard data, and a judgment result is obtained.
5. The self-checking device for the Flash memory built in the chip is characterized by comprising:
the starting module is used for powering on a chip, and a Flash self-checking module is arranged in the chip and performs Flash test by acquiring a configuration value generated by external hardware;
the first judging module is used for judging whether the pin EN is 0, if EN=0, flash self-checking operation is not performed, and if EN=1, pin IO configuration information is read;
the second judging module is used for judging whether the MODE pin is 0, if MODE=0, erasing/writing/reading/judging operation is carried out, if MODE=1, only reading/judging operation is carried out, and the Flash self-checking module reads Flash information and carries out CRC check;
the third judging module is used for judging whether the INFO pin is 0, if the INFO is 0, performing read/write/page erase/full erase operation on the main storage area, and if the INFO is 1, performing read/write/page erase operation on the information storage area and performing full erase operation on the main storage area and the information storage area;
the fourth judging module is used for judging whether the Data [3:0] pin code is 1 from the lowest bit in sequence, and if the Data [3:0] pin code is 1, executing a numerical operation corresponding to the writing of Flash;
and the fifth judging module is used for judging a test result after the Flash self-test is finished, if the result is correct, pulling the DONE pin high to be 1, and if the result is incorrect, pulling the ERR pin high to be 1.
6. The self-checking device of a Flash memory built-in chip according to claim 5, wherein the first judging module is further configured to:
when en=0, the upper computer can write the Flash self-checking module register through the jtag, so that Flash self-checking is enabled and configuration information is written.
7. The self-checking device of a Flash memory built-in chip according to claim 6, wherein the second judging module is further configured to:
comparing the read Flash information with the CRC value stored in the Flash, if the read Flash information and the CRC value are the same, performing Flash self-checking normally, and if the read Flash information and the CRC value are different, performing Flash self-checking incorrectly.
8. The self-checking device of a Flash memory built-in chip according to claim 7, wherein the fourth judging module is further configured to:
the Flash self-checking module starts to judge from the lowest bit of the Data [3:0] pin;
if the first bit is judged to be 1, writing by taking 0xFFFFFFFF as standard data and judging a result;
if the second bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0x55AA55AA as standard data and judging a result;
if the third bit is judged to be 1, re-erasing the Flash, and executing writing by taking 0xAA55AA55 as standard data and judging a result;
if the fourth bit is judged to be 1, flash is erased again, and writing is performed by taking 0x00000000 as standard data, and a judgment result is obtained.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 4 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
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| CN117608911B (en) * | 2024-01-24 | 2024-04-16 | 苏州旗芯微半导体有限公司 | Microcontroller system and communication method thereof |
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