CN116431527A - Data read-write method, system, equipment and medium for address remapping - Google Patents
Data read-write method, system, equipment and medium for address remapping Download PDFInfo
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Abstract
The invention provides a data read-write method, a system, equipment and a medium for remapping addresses, wherein the method comprises the following steps: acquiring a data read-write instruction sent by a first storage unit, and acquiring the bit width of the first storage unit according to the bit width identifier in the instruction; based on the bit width, carrying out logic shift on the number of the first storage unit to obtain a remapping address; the logic shift process is: dividing the number into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of numbers; the second array is an array formed by the data outside the first array; and reading or writing the byte data of the corresponding address to the second storage unit according to the remapping address. Based on the method, a data read-write system, equipment and medium for address remapping are also provided. The invention realizes the data read-write of the serial numbers of the storage units with different bit widths to the 32-bit system, realizes the compatibility of addressing and accelerates the operation efficiency.
Description
Technical Field
The invention belongs to the technical field of data reading and writing, and particularly relates to a data reading and writing method, system, equipment and medium for remapping addresses.
Background
The addressing mode is a mode that a processor searches for an effective address according to address information given in an instruction, and is a method for determining a data address of the instruction and an address of a next instruction to be executed. At present, the read-write mode of the central processing unit for data takes bytes as a basic addressing unit as a main stream, and in a 32-bit system, 4 bytes are accessed each time, and the access address is a multiple of 4. However, there is no lack of a module with a memory cell number as an addressing mode, the memory cell numbers are consecutive natural integers of 0, 1, 2, 3 and …, and the bit width of the memory cell may be 8 bits, 16 bits or 32 bits, which brings compatibility problems for data read-write in different addressing modes.
When a 32-bit system is accessed in a memory cell numbering mode, data reading and writing of wrong addresses are caused by different addressing modes, or system problems are caused by address misalignment.
Disclosure of Invention
In order to solve the technical problems, the invention provides a data read-write method, a system, equipment and a medium for remapping addresses, which realize the data read-write from serial numbers of storage units with different bit widths to a 32-bit system.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a data read-write method of address remapping includes the following steps:
acquiring a data read-write instruction sent by a first storage unit, and acquiring the bit width of the first storage unit according to a bit width identifier in the data read-write instruction;
based on the bit width of the first memory cell, obtaining a remapped address by logically shifting the number of the first memory cell; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array formed by data except the first array;
and reading or writing byte data of the corresponding address into the second storage unit according to the remapping address.
Further, the process of identifying Fu Panduan the bit width of the first memory cell according to the bit width in the data read/write command includes:
if the bit width identifier in the data read-write instruction is 00, the bit width representing the first memory cell is 8 bits;
if the bit width identifier in the data read-write instruction is 01, the bit width representing the first memory cell is 16 bits;
If the bit width identifier in the data read/write instruction is 10 or 11, the bit width representing the first memory cell is 32 bits.
Further, when the bit width of the first memory cell is 8 bits, the process of obtaining the remapped address includes: the number of the first storage unit is firstly logically shifted by two bits to the right, then logically shifted by two bits to the left, so that the first array is a preset character 00, and the second array is kept unchanged to obtain a remapping address; the remapped address is a 32-bit address of the second memory cell.
Further, when the bit width of the first memory cell is 8 bits, the process of reading or writing the byte data of the corresponding address includes: firstly, reading four bytes of data of a corresponding address, and if the four bytes are read operation, selecting bytes according to the lower two bits of the remapped address number; if the operation is writing operation, changing the corresponding byte into the data to be written and writing the data into the second storage unit together with the other three bytes.
Further, when the bit width of the first memory cell is 16 bits, the process of obtaining the remapped address includes: judging whether the number of the first storage unit is odd or even, if the number of the first storage unit is odd, subtracting the number of the first storage unit by one first and then shifting the logic left by one bit to obtain a remapping address; if the number of the first memory cell is even, directly logically shifting one bit left to obtain a remapped address; the remapped address is a 32-bit address of the second memory cell.
Further, when the bit width of the first memory cell is 16 bits, the process of reading or writing the byte data of the corresponding address includes: if the read operation is performed, the high-16-bit data is fetched when the number of the first storage unit is odd, and the low-16-bit data is fetched when the number of the first storage unit is even; and if the operation is a writing operation, changing the corresponding 16-bit data into data to be written and writing the data into the second storage unit along with the other 16-bit data.
Further, when the bit width of the first memory cell is 32 bits, the process of obtaining the remapped address includes: shifting the number logic of the first storage unit by two bits to the left to obtain a remapping address; the remapped address is a 32-bit address of the second memory cell.
The invention also provides a data read-write system for the address remapping, which comprises a judging module, a mapping module and a read-write module;
the judging module is used for acquiring a data read-write instruction sent by the first storage unit, and identifying Fu Panduan bit width of the first storage unit according to the bit width in the data read-write instruction;
the mapping module is used for obtaining a remapped address by logically shifting the number of the first storage unit based on the bit width of the first storage unit; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array formed by data except the first array;
The read-write module is used for reading or writing byte data of the corresponding address to the second storage unit according to the remapping address.
The invention also proposes a device comprising:
a memory for storing a computer program;
and a processor for implementing the method steps when executing the computer program.
The invention relates to a readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when executed by a processor, implements the method steps.
The effects provided in the summary of the invention are merely effects of embodiments, not all effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
the invention provides a data read-write method, a system, equipment and a medium for remapping addresses, wherein the method comprises the following steps: acquiring a data read-write instruction sent by a first storage unit, and acquiring the bit width of the first storage unit according to a bit width identifier in the data read-write instruction; based on the bit width of the first memory cell, obtaining a remapped address by logically shifting the number of the first memory cell; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array formed by data except the first array; and reading or writing the byte data of the corresponding address into the second storage unit according to the remapping address. A data read-write method based on address remapping and a data read-write system, device and medium for address remapping are also provided. The invention solves the problem of data read-write of wrong addresses caused by different addressing modes or system problems caused by misaligned addresses in the prior art, realizes the data read-write of serial numbers of storage units with different bit widths to a 32-bit system addressing, realizes the compatibility of addressing, accelerates the operation efficiency and improves the performance of the intelligent terminal.
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Fig. 1 is a flow chart of a data read-write method of address remapping according to embodiment 1 of the present invention;
FIG. 2 is a flowchart illustrating a first memory cell bit width determination according to embodiment 1 of the present invention;
FIG. 3 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 8 bits;
FIG. 4 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 16 bits;
FIG. 5 is a flow chart of the address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 32 bits;
fig. 6 is a schematic diagram of a data read-write system for address remapping according to embodiment 2 of the present invention;
fig. 7 is a schematic diagram of a data read-write device for address remapping according to embodiment 3 of the present invention.
Detailed Description
In order to clearly illustrate the technical features of the present solution, the present invention will be described in detail below with reference to the following detailed description and the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily obscure the present invention.
Example 1
The embodiment 1 of the invention provides a data read-write method for remapping addresses, which realizes the data read-write from the serial numbers of storage units with different bit widths to a 32-bit system. FIG. 1 is a flow chart of a data read-write method for address remapping;
in step S100, a data read-write command sent by the first storage unit is obtained, and the bit width of the first storage unit is identified Fu Panduan according to the bit width in the data read-write command;
according to the related identification bits in the read-write command, judging the bit width of the first storage unit accessed by the command initiator.
FIG. 2 is a flowchart illustrating a first memory cell bit width determination according to embodiment 1 of the present invention; if the bit width identifier in the data read-write instruction is 00, the bit width representing the first memory cell is 8 bits; if the bit width identifier in the data read-write instruction is 01, the bit width representing the first memory cell is 16 bits; if the bit width identifier in the data read/write instruction is 10 or 11, the bit width representing the first memory cell is 32 bits. The scope of the present invention is not limited to the bit width identifiers listed in embodiment 1, and a person skilled in the art may select an appropriate bit width identifier according to the actual situation.
In step S200, a remapped address is obtained by logically shifting the number of the first memory cell based on the bit width of the first memory cell; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array composed of data other than the first array.
In step S300, according to the remapped address, the byte data of the corresponding address is read or written into the second storage unit. When receiving the read-write command, firstly reading the 4 bytes of data of the corresponding address, and respectively 00, 01, 10 and 11 from low to high in byte number.
The present invention maps a first memory cell that is 8-bit, 16-bit, or 32-bit wide to a 32-bit memory system, i.e., a second memory cell.
When the bit width of the first memory cell is 8 bits, the process of obtaining the remapped address comprises the following steps: the number of the first storage unit is firstly logically shifted by two bits to the right, then logically shifted by two bits to the left, so that the first array is a preset character 00, and the second array is kept unchanged to obtain a remapping address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 8 bits, the process of reading or writing the byte data of the corresponding address includes: firstly, reading four bytes of data of a corresponding address, and if the four bytes are read operation, selecting bytes according to the lower two bits of the remapped address number; if the operation is writing operation, changing the corresponding byte into the data to be written and writing the data into the second storage unit together with the other three bytes.
FIG. 3 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 8 bits;
for a first memory cell having a bit width of 8 bits, the binary expression of the number of the first memory cell is xxxxxyy, where x=0 or 1; y=0 or 1. After a logical shift of 2 bits to the right and a logical shift of 2 bits to the left, the corresponding 32-bit address xxxxx00 is obtained. In the logic shift process, the address xxxxx of the first storage unit is kept unchanged, the number yy of the first storage unit is changed into a preset character 00, and then the corresponding 32-bit address xxxxx00 can be obtained.
The corresponding 4 bytes of data are fetched as { B3B 2B 1B 0}, and then a byte is selected according to the two lower bits yy of the number: b0 is selected when yy is 00, B1 is selected when yy is 01, B2 is selected when yy is 10, and B3 is selected when yy is 11. If the selected byte data is directly output for the read command, if Bx (x=0, 1,2, 3) is replaced with the data to be written for the write command, and the data is written back into the remapped address together with other 3 byte data, such as { B3 new data B1B 0 }.
When the bit width of the first memory cell is 16 bits, the process of obtaining the remapped address comprises the following steps: judging whether the number of the first storage unit is odd or even, if the number of the first storage unit is odd, subtracting the number of the first storage unit by one first and then shifting the logic left by one bit to obtain a remapping address; if the number of the first memory cell is even, directly logically shifting one bit left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 16 bits, the process of reading or writing the byte data of the corresponding address includes: if the read operation is performed, the high-16-bit data is fetched when the number of the first storage unit is odd, and the low-16-bit data is fetched when the number of the first storage unit is even; and if the operation is a writing operation, changing the corresponding 16-bit data into data to be written and writing the data into the second storage unit along with the other 16-bit data.
FIG. 4 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 16 bits;
for the first memory cell with the bit width of 16 bits, if the binary number of the first memory cell is xxxxxx1, if the binary number is odd, obtaining a 32-bit corresponding address xxxxxx00 by subtracting one bit left again, and taking out the high 16-bit data. If the number is even number xxxxx0, shifting left one bit to obtain a 32-bit corresponding address xxxxx00, and taking out the low 16-bit data. If the selected two-byte data is directly output for the read command, the fetched 16-bit data is replaced by the data to be written for the write command, and the data is written back into the remapped address together with the other 16-bit data.
When the bit width of the first memory cell is 32 bits, the process of obtaining the remapped address comprises the following steps: shifting the number logic of the first storage unit by two bits to the left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location. For address remapping of 32-bit width, the data is read or written directly.
FIG. 5 is a flow chart of the address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 32 bits; for the first memory cell with the bit width of 32 bits, if the binary number of the first memory cell is xxxxxx, directly shifting the binary number of xxxxxxxxxxxxxx by two left bits to obtain a corresponding 32-bit address xxxxxx00, if a read command is issued, directly taking out address data, and if a write command is issued, directly writing the data into the 32-bit address.
The data read-write method of the address remapping provided by the embodiment 1 of the invention solves the problem of data read-write of the wrong address caused by different addressing modes or the problem of system caused by misalignment of addresses in the prior art, realizes the data read-write of the serial numbers of the storage units with different bit widths to the 32-bit system addressing, realizes the compatibility of addressing, accelerates the operation efficiency and improves the performance of the intelligent terminal.
Example 2
Based on the data read-write method of the address remapping according to embodiment 1 of the present invention, embodiment 2 of the present invention further provides a data read-write system of the address remapping, as shown in fig. 6, which is a schematic diagram of the data read-write system of the address remapping according to embodiment 2 of the present invention; the system comprises a judging module, a mapping module and a read-write module;
the judging module is used for acquiring a data read-write instruction sent by the first storage unit and identifying Fu Panduan bit width of the first storage unit according to the bit width in the data read-write instruction;
the mapping module is used for obtaining a remapped address by logically shifting the number of the first storage unit based on the bit width of the first storage unit; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array formed by data except the first array;
the read-write module is used for reading or writing byte data of the corresponding address into the second storage unit according to the remapping address.
The process of realizing the judging module in the embodiment 2 of the invention comprises the following steps: if the bit width identifier in the data read-write instruction is 00, the bit width representing the first memory cell is 8 bits; if the bit width identifier in the data read-write instruction is 01, the bit width representing the first memory cell is 16 bits; if the bit width identifier in the data read/write instruction is 10 or 11, the bit width representing the first memory cell is 32 bits.
The mapping module and the read-write module are realized together as follows: the present invention maps a first memory cell that is 8-bit, 16-bit, or 32-bit wide to a 32-bit memory system, i.e., a second memory cell.
When the bit width of the first memory cell is 8 bits, the process of obtaining the remapped address comprises the following steps: the number of the first storage unit is firstly logically shifted by two bits to the right, then logically shifted by two bits to the left, so that the first array is a preset character 00, and the second array is kept unchanged to obtain a remapping address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 8 bits, the process of reading or writing the byte data of the corresponding address includes: firstly, reading four bytes of data of a corresponding address, and if the four bytes are read operation, selecting bytes according to the lower two bits of the remapped address number; if the operation is writing operation, changing the corresponding byte into the data to be written and writing the data into the second storage unit together with the other three bytes.
When the bit width of the first memory cell is 16 bits, the process of obtaining the remapped address comprises the following steps: judging whether the number of the first storage unit is odd or even, if the number of the first storage unit is odd, subtracting the number of the first storage unit by one first and then shifting the logic left by one bit to obtain a remapping address; if the number of the first memory cell is even, directly logically shifting one bit left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 16 bits, the process of reading or writing the byte data of the corresponding address includes: if the read operation is performed, the high-16-bit data is fetched when the number of the first storage unit is odd, and the low-16-bit data is fetched when the number of the first storage unit is even; and if the operation is a writing operation, changing the corresponding 16-bit data into data to be written and writing the data into the second storage unit along with the other 16-bit data.
When the bit width of the first memory cell is 32 bits, the process of obtaining the remapped address comprises the following steps: shifting the number logic of the first storage unit by two bits to the left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location. For address remapping of 32-bit width, the data is read or written directly.
The data read-write system for remapping addresses provided by the embodiment 2 of the invention solves the problem of data read-write of wrong addresses caused by different addressing modes or system problems caused by misaligned addresses in the prior art, realizes the data read-write of serial numbers of storage units with different bit widths to a 32-bit system, realizes the compatibility of addressing, accelerates the operation efficiency and improves the performance of an intelligent terminal.
Example 3
The present invention also proposes a device, as shown in fig. 7, which is a schematic diagram of a data read-write device for address remapping according to embodiment 3 of the present invention, including:
a memory for storing a computer program;
the processor is used for realizing the following steps when executing the computer program:
FIG. 1 is a flow chart of a data read-write method for address remapping;
in step S100, a data read-write command sent by the first storage unit is obtained, and the bit width of the first storage unit is identified Fu Panduan according to the bit width in the data read-write command;
according to the related identification bits in the read-write command, judging the bit width of the first storage unit accessed by the command initiator.
FIG. 2 is a flowchart illustrating a first memory cell bit width determination according to embodiment 1 of the present invention; if the bit width identifier in the data read-write instruction is 00, the bit width representing the first memory cell is 8 bits; if the bit width identifier in the data read-write instruction is 01, the bit width representing the first memory cell is 16 bits; if the bit width identifier in the data read/write instruction is 10 or 11, the bit width representing the first memory cell is 32 bits. The scope of the present invention is not limited to the bit width identifiers listed in embodiment 1, and a person skilled in the art may select an appropriate bit width identifier according to the actual situation.
In step S200, a remapped address is obtained by logically shifting the number of the first memory cell based on the bit width of the first memory cell; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array composed of data other than the first array.
In step S300, according to the remapped address, the byte data of the corresponding address is read or written into the second storage unit. When receiving the read-write command, firstly reading the 4 bytes of data of the corresponding address, and respectively 00, 01, 10 and 11 from low to high in byte number.
The present invention maps a first memory cell that is 8-bit, 16-bit, or 32-bit wide to a 32-bit memory system, i.e., a second memory cell.
When the bit width of the first memory cell is 8 bits, the process of obtaining the remapped address comprises the following steps: the number of the first storage unit is firstly logically shifted by two bits to the right, then logically shifted by two bits to the left, so that the first array is a preset character 00, and the second array is kept unchanged to obtain a remapping address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 8 bits, the process of reading or writing the byte data of the corresponding address includes: firstly, reading four bytes of data of a corresponding address, and if the four bytes are read operation, selecting bytes according to the lower two bits of the remapped address number; if the operation is writing operation, changing the corresponding byte into the data to be written and writing the data into the second storage unit together with the other three bytes.
FIG. 3 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 8 bits;
for a first memory cell having a bit width of 8 bits, the binary expression of the number of the first memory cell is xxxxxyy, where x=0 or 1; y=0 or 1. After a logical shift of 2 bits to the right and a logical shift of 2 bits to the left, the corresponding 32-bit address xxxxx00 is obtained. In the logic shift process, the address xxxxx of the first storage unit is kept unchanged, the number yy of the first storage unit is changed into a preset character 00, and then the corresponding 32-bit address xxxxx00 can be obtained.
The corresponding 4 bytes of data are fetched as { B3B 2B 1B 0}, and then a byte is selected according to the two lower bits yy of the number: b0 is selected when yy is 00, B1 is selected when yy is 01, B2 is selected when yy is 10, and B3 is selected when yy is 11. If the selected byte data is directly output for the read command, if Bx (x=0, 1,2, 3) is replaced with the data to be written for the write command, and the data is written back into the remapped address together with other 3 byte data, such as { B3 new data B1B 0 }.
When the bit width of the first memory cell is 16 bits, the process of obtaining the remapped address comprises the following steps: judging whether the number of the first storage unit is odd or even, if the number of the first storage unit is odd, subtracting the number of the first storage unit by one first and then shifting the logic left by one bit to obtain a remapping address; if the number of the first memory cell is even, directly logically shifting one bit left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 16 bits, the process of reading or writing the byte data of the corresponding address includes: if the read operation is performed, the high-16-bit data is fetched when the number of the first storage unit is odd, and the low-16-bit data is fetched when the number of the first storage unit is even; and if the operation is a writing operation, changing the corresponding 16-bit data into data to be written and writing the data into the second storage unit along with the other 16-bit data.
FIG. 4 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 16 bits;
for the first memory cell with the bit width of 16 bits, if the binary number of the first memory cell is xxxxxx1, if the binary number is odd, obtaining a 32-bit corresponding address xxxxxx00 by subtracting one bit left again, and taking out the high 16-bit data. If the number is even number xxxxx0, shifting left one bit to obtain a 32-bit corresponding address xxxxx00, and taking out the low 16-bit data. If the selected two-byte data is directly output for the read command, the fetched 16-bit data is replaced by the data to be written for the write command, and the data is written back into the remapped address together with the other 16-bit data.
When the bit width of the first memory cell is 32 bits, the process of obtaining the remapped address comprises the following steps: shifting the number logic of the first storage unit by two bits to the left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location. For address remapping of 32-bit width, the data is read or written directly.
FIG. 5 is a flow chart of the address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 32 bits; for the first memory cell with the bit width of 32 bits, if the binary number of the first memory cell is xxxxxx, directly shifting the binary number of xxxxxxxxxxxxxx by two left bits to obtain a corresponding 32-bit address xxxxxx00, if a read command is issued, directly taking out address data, and if a write command is issued, directly writing the data into the 32-bit address.
The data read-write equipment for remapping addresses provided by the embodiment 3 of the invention solves the problem of data read-write of wrong addresses caused by different addressing modes or system problems caused by misalignment of addresses in the prior art, realizes the data read-write of serial numbers of storage units with different bit widths to a 32-bit system, realizes the compatibility of addressing, accelerates the operation efficiency and improves the performance of the intelligent terminal.
It is necessary to explain that: the technical scheme of the invention also provides electronic equipment, which comprises: a communication interface capable of information interaction with other devices such as a network device and the like; and the processor is connected with the communication interface to realize information interaction with other devices, and is used for executing the data read-write method of address remapping provided by one or more of the technical schemes when running the computer program, and the computer program is stored on the memory. Of course, in practice, the various components in the electronic device are coupled together by a bus system. It will be appreciated that a bus system is used to enable connected communications between these components. The bus system includes a power bus, a control bus, and a status signal bus in addition to the data bus. The memory in the embodiments of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device. It will be appreciated that the memory can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random AccessMemory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronousDynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr sdram, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory. The method disclosed in the embodiments of the present application may be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The processor may be a general purpose processor, a DSP (Digital Signal Processing, meaning a chip capable of implementing digital signal processing techniques), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium having a memory, and the processor reads the program in the memory and performs the steps of the method in combination with its hardware. The processor executes the program to implement the corresponding flow in each method of the embodiments of the present application, and for brevity, will not be described in detail herein.
Example 4
The invention also provides a readable storage medium, the readable storage medium stores a computer program, and the computer program when executed by a processor realizes the following steps:
FIG. 1 is a flow chart of a data read-write method for address remapping;
in step S100, a data read-write command sent by the first storage unit is obtained, and the bit width of the first storage unit is identified Fu Panduan according to the bit width in the data read-write command;
according to the related identification bits in the read-write command, judging the bit width of the first storage unit accessed by the command initiator.
FIG. 2 is a flowchart illustrating a first memory cell bit width determination according to embodiment 1 of the present invention; if the bit width identifier in the data read-write instruction is 00, the bit width representing the first memory cell is 8 bits; if the bit width identifier in the data read-write instruction is 01, the bit width representing the first memory cell is 16 bits; if the bit width identifier in the data read/write instruction is 10 or 11, the bit width representing the first memory cell is 32 bits. The scope of the present invention is not limited to the bit width identifiers listed in embodiment 1, and a person skilled in the art may select an appropriate bit width identifier according to the actual situation.
In step S200, a remapped address is obtained by logically shifting the number of the first memory cell based on the bit width of the first memory cell; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array composed of data other than the first array.
In step S300, according to the remapped address, the byte data of the corresponding address is read or written into the second storage unit. When receiving the read-write command, firstly reading the 4 bytes of data of the corresponding address, and respectively 00, 01, 10 and 11 from low to high in byte number.
The present invention maps a first memory cell that is 8-bit, 16-bit, or 32-bit wide to a 32-bit memory system, i.e., a second memory cell.
When the bit width of the first memory cell is 8 bits, the process of obtaining the remapped address comprises the following steps: the number of the first storage unit is firstly logically shifted by two bits to the right, then logically shifted by two bits to the left, so that the first array is a preset character 00, and the second array is kept unchanged to obtain a remapping address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 8 bits, the process of reading or writing the byte data of the corresponding address includes: firstly, reading four bytes of data of a corresponding address, and if the four bytes are read operation, selecting bytes according to the lower two bits of the remapped address number; if the operation is writing operation, changing the corresponding byte into the data to be written and writing the data into the second storage unit together with the other three bytes.
FIG. 3 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 8 bits;
for a first memory cell having a bit width of 8 bits, the binary expression of the number of the first memory cell is xxxxxyy, where x=0 or 1; y=0 or 1. After a logical shift of 2 bits to the right and a logical shift of 2 bits to the left, the corresponding 32-bit address xxxxx00 is obtained. In the logic shift process, the address xxxxx of the first storage unit is kept unchanged, the number yy of the first storage unit is changed into a preset character 00, and then the corresponding 32-bit address xxxxx00 can be obtained.
The corresponding 4 bytes of data are fetched as { B3B 2B 1B 0}, and then a byte is selected according to the two lower bits yy of the number: b0 is selected when yy is 00, B1 is selected when yy is 01, B2 is selected when yy is 10, and B3 is selected when yy is 11. If the selected byte data is directly output for the read command, if Bx (x=0, 1,2, 3) is replaced with the data to be written for the write command, and the data is written back into the remapped address together with other 3 byte data, such as { B3 new data B1B 0 }.
When the bit width of the first memory cell is 16 bits, the process of obtaining the remapped address comprises the following steps: judging whether the number of the first storage unit is odd or even, if the number of the first storage unit is odd, subtracting the number of the first storage unit by one first and then shifting the logic left by one bit to obtain a remapping address; if the number of the first memory cell is even, directly logically shifting one bit left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location.
When the bit width of the first memory cell is 16 bits, the process of reading or writing the byte data of the corresponding address includes: if the read operation is performed, the high-16-bit data is fetched when the number of the first storage unit is odd, and the low-16-bit data is fetched when the number of the first storage unit is even; and if the operation is a writing operation, changing the corresponding 16-bit data into data to be written and writing the data into the second storage unit along with the other 16-bit data.
FIG. 4 is a flow chart of address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 16 bits;
for the first memory cell with the bit width of 16 bits, if the binary number of the first memory cell is xxxxxx1, if the binary number is odd, obtaining a 32-bit corresponding address xxxxxx00 by subtracting one bit left again, and taking out the high 16-bit data. If the number is even number xxxxx0, shifting left one bit to obtain a 32-bit corresponding address xxxxx00, and taking out the low 16-bit data. If the selected two-byte data is directly output for the read command, the fetched 16-bit data is replaced by the data to be written for the write command, and the data is written back into the remapped address together with the other 16-bit data.
When the bit width of the first memory cell is 32 bits, the process of obtaining the remapped address comprises the following steps: shifting the number logic of the first storage unit by two bits to the left to obtain a remapped address; the remapped address is a 32-bit address of the second memory location. For address remapping of 32-bit width, the data is read or written directly.
FIG. 5 is a flow chart of the address remapping data read/write when the bit width of the first memory cell according to embodiment 1 of the present invention is 32 bits; for the first memory cell with the bit width of 32 bits, if the binary number of the first memory cell is xxxxxx, directly shifting the binary number of xxxxxxxxxxxxxx by two left bits to obtain a corresponding 32-bit address xxxxxx00, if a read command is issued, directly taking out address data, and if a write command is issued, directly writing the data into the 32-bit address.
The data read-write equipment for remapping addresses provided by the embodiment 4 of the invention solves the problem of data read-write of wrong addresses caused by different addressing modes or system problems caused by misalignment of addresses in the prior art, realizes the data read-write of serial numbers of storage units with different bit widths to a 32-bit system, realizes the compatibility of addressing, accelerates the operation efficiency and improves the performance of an intelligent terminal.
The embodiments of the present application also provide a storage medium, i.e. a computer storage medium, in particular a computer readable storage medium, for example comprising a memory storing a computer program executable by a processor for performing the steps of the aforementioned method. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, or CD-ROM.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code. Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partly contributing to the prior art, and the computer software product may be stored in a storage medium, and include several instructions to cause an electronic device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.
The description of the relevant parts in the storage medium for data reading and writing of address remapping provided in embodiment 4 of the present application may refer to the detailed description of the corresponding parts in the data reading and writing method of address remapping provided in embodiment 1 of the present application, which is not repeated here.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is inherent to. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In addition, the parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of the corresponding technical solutions in the prior art, are not described in detail, so that redundant descriptions are avoided.
While the specific embodiments of the present invention have been described above with reference to the drawings, the scope of the present invention is not limited thereto. Other modifications and variations to the present invention will be apparent to those of skill in the art upon review of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. On the basis of the technical scheme of the invention, various modifications or variations which can be made by the person skilled in the art without the need of creative efforts are still within the protection scope of the invention.
Claims (10)
1. The data read-write method of the address remapping is characterized by comprising the following steps:
acquiring a data read-write instruction sent by a first storage unit, and acquiring the bit width of the first storage unit according to a bit width identifier in the data read-write instruction;
based on the bit width of the first memory cell, obtaining a remapped address by logically shifting the number of the first memory cell; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array formed by data except the first array;
And reading or writing byte data of the corresponding address into the second storage unit according to the remapping address.
2. The method for writing and reading data according to claim 1, wherein the step of identifying Fu Panduan the bit width of the first memory cell according to the bit width in the data writing and reading command comprises:
if the bit width identifier in the data read-write instruction is 00, the bit width representing the first memory cell is 8 bits;
if the bit width identifier in the data read-write instruction is 01, the bit width representing the first memory cell is 16 bits;
if the bit width identifier in the data read/write instruction is 10 or 11, the bit width representing the first memory cell is 32 bits.
3. The method for reading and writing data according to claim 2, wherein when the bit width of the first memory cell is 8 bits, the process of remapping the address includes: the number of the first storage unit is firstly logically shifted by two bits to the right, then logically shifted by two bits to the left, so that the first array is a preset character 00, and the second array is kept unchanged to obtain a remapping address; the remapped address is a 32-bit address of the second memory cell.
4. A method for reading and writing data according to claim 3, wherein when the bit width of the first memory cell is 8 bits, the process of reading or writing byte data of the corresponding address comprises: firstly, reading four bytes of data of a corresponding address, and if the four bytes are read operation, selecting bytes according to the lower two bits of the remapped address number; if the operation is writing operation, changing the corresponding byte into the data to be written and writing the data into the second storage unit together with the other three bytes.
5. The method for reading and writing data according to claim 2, wherein when the bit width of the first memory cell is 16 bits, the process of remapping the address includes: judging whether the number of the first storage unit is odd or even, if the number of the first storage unit is odd, subtracting the number of the first storage unit by one first and then shifting the logic left by one bit to obtain a remapping address; if the number of the first memory cell is even, directly logically shifting one bit left to obtain a remapped address; the remapped address is a 32-bit address of the second memory cell.
6. The method for reading and writing data according to claim 5, wherein when the bit width of the first memory cell is 16 bits, the process of reading or writing the byte data of the corresponding address comprises: if the read operation is performed, the high-16-bit data is fetched when the number of the first storage unit is odd, and the low-16-bit data is fetched when the number of the first storage unit is even; and if the operation is a writing operation, changing the corresponding 16-bit data into data to be written and writing the data into the second storage unit along with the other 16-bit data.
7. The method for reading and writing data according to claim 2, wherein when the bit width of the first memory cell is 32 bits, the process of remapping the address includes: shifting the number logic of the first storage unit by two bits to the left to obtain a remapping address; the remapped address is a 32-bit address of the second memory cell.
8. The data read-write system for remapping the address is characterized by comprising a judging module, a mapping module and a read-write module;
the judging module is used for acquiring a data read-write instruction sent by the first storage unit, and identifying Fu Panduan bit width of the first storage unit according to the bit width in the data read-write instruction;
the mapping module is used for obtaining a remapped address by logically shifting the number of the first storage unit based on the bit width of the first storage unit; the process of logical shifting includes: dividing the number of the first storage unit into a first array and a second array; the second array is kept unchanged through logic shift, and the first array is a preset character; the first array is an array formed by preset low bits of the first storage unit number; the second array is an array formed by data except the first array;
the read-write module is used for reading or writing byte data of the corresponding address to the second storage unit according to the remapping address.
9. An apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the method steps of any one of claims 1 to 7 when executing said computer program.
10. A readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the method steps of any of claims 1 to 7.
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