CN116414766A

CN116414766A - Heterogeneous system inter-core time synchronization method, heterogeneous system and mobile terminal

Info

Publication number: CN116414766A
Application number: CN202111673804.4A
Authority: CN
Inventors: 于士超
Original assignee: Beijing Simm Computing Technology Co ltd
Current assignee: Beijing Simm Computing Technology Co ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-07-11

Abstract

The invention discloses a heterogeneous system inter-core time synchronization method, a heterogeneous system and a mobile terminal, wherein the synchronization method applied to a main processor comprises the following steps: transmitting at least two read instructions to a slave processor, receiving a plurality of read data returned by the slave processor, and acquiring main processing time for receiving the read data when the read instructions are transmitted, wherein the read data comprises slave processing time for the slave processor to respond to the read instructions; acquiring a master time slot according to a plurality of master processing times, acquiring a slave time slot according to a plurality of slave processing times, and calculating a slot difference value of the master time slot and the slave time slot; and in response to the time slot difference value being greater than the time slot threshold value, acquiring a first synchronization compensation value of the main processor, correcting the first presentation time of the main processor according to the first synchronization compensation value, and outputting the corrected first presentation time and the second presentation time of the auxiliary processor. According to the method and the device, the slave processor with accurate time slot timing is used for synchronizing and correcting the master processor, so that the time synchronization precision of the master processor and the slave processor is effectively improved.

Description

Heterogeneous system inter-core time synchronization method, heterogeneous system and mobile terminal

Technical Field

The present invention relates to the technical field of heterogeneous systems, and in particular, to a heterogeneous system, a mobile terminal, a computer storage medium, and a computer device.

Background

A conventional Central Processing Unit (CPU) is not suitable for dedicated tasks such as graphic computation and neural network computation as a general-purpose processor, so that a processor for accelerating hardware and the central processing unit together form a heterogeneous system, and are increasingly favored by an internet enterprise server. However, the timing rates of the different processors may vary, which may cause non-uniformity in the time references between the different processors within the heterogeneous system.

Disclosure of Invention

To solve at least one of the above problems, a first embodiment of the present invention provides a method for synchronizing inter-core time of a heterogeneous system, including:

s1: transmitting at least two read instructions to a slave processor, receiving a plurality of read data returned by the slave processor, and acquiring main processing time for receiving the read data when the read instructions are transmitted, wherein the read data comprises slave processing time for the slave processor to respond to the read instructions;

s2: acquiring a master time slot according to a plurality of master processing times, acquiring a slave time slot according to a plurality of slave processing times, and calculating a time slot difference value between the master time slot and the slave time slot;

S3: and responding to the time slot difference value being larger than a time slot threshold value, acquiring a first synchronous compensation value of the main processor, correcting the first display time of the main processor according to the first synchronous compensation value, and outputting the corrected first display time and the second display time of the auxiliary processor.

According to the embodiment, a synchronous test instruction set is sent to a slave processor through a master processor, and a plurality of returned read data are received, so that the master processing time of the master processor and the slave processing time of the slave processor are obtained, a master time slot is obtained according to the master processing time, a slave time slot is obtained according to the slave processing time, a time slot difference value is calculated according to the master time slot and the slave time slot, whether the master processor and the slave processor are synchronous or not is judged according to the time slot difference value, and if the master processor and the slave processor are not synchronous, a synchronous compensation value is calculated, and the display time of the master processor and the display time of the slave processor are output; in other words, the time synchronization of the slave processor and the time correction of the master processor are performed by timing the time period more accurately, so that the time synchronization precision of the master processor and the slave processor is effectively improved, the operation performance of the heterogeneous system is conveniently analyzed according to the display time of the master processor and the slave processor, and the method has practical application value.

In an alternative embodiment, the step S1 further includes:

the step S1 further comprises the following steps:

s101: sending a first read instruction to a slave processor at a first master processing time, such that the slave processor returns first read data after receiving the first read instruction, the first read data including a first slave time;

s102: in response to receiving the first read data returned by the slave processor, sending a second read instruction, so that after the slave processor receives the second read instruction, second read data is returned, wherein the second read data comprises a second slave time;

s103: receiving second read data returned by the slave processor at a third master processing time;

the S2 further includes:

s201: acquiring the main time slot according to the first main processing time and the third main processing time;

s202: acquiring the slave time slot according to the first slave time and the second slave time;

s203: and calculating a time slot difference value according to the master time slot and the slave time slot.

In the embodiment, the master processor sends the read instruction to the slave processor and acquires the read data twice in succession, so that three master processing times on the master processor side and two slave processing times on the slave processor side are obtained, the master time slot of the master processor and the slave time slot of the slave processor are calculated, and the time slot difference of the master processor and the slave processor is acquired so as to facilitate the subsequent time synchronization operation. According to the embodiment, the instruction is used as a timing reference, so that the timing accuracy is effectively improved.

In an alternative embodiment, the step S1 further includes:

s01: initializing a storage queue and a test counter;

the S2 further includes:

s221: acquiring a plurality of main time slots, storing the main time slots in the storage queue according to the sequence of numerical values, and adding 1 to the count value of the test counter each time the main time slots are acquired;

s222: responding to the count value of the test counter being smaller than a preset test count threshold value, judging whether the current main time slot is converged according to a preset convergence judging formula, and if the current main time slot is not converged, sending a reading instruction to a slave processor to acquire the main time slot again; if the main time slot converges, jumping to S223;

s223: and calculating a time slot difference value according to the current master time slot and the slave time slot.

In the embodiment, a plurality of groups of synchronous test instructions are sent to the slave processor through the master processor, each group of synchronous test instructions comprises a master processor sending a read instruction to the slave processor twice continuously and acquiring read data, so that three master processing times of the master processor side and two slave processing times of the slave processor side are obtained, whether the master time slot of an instruction period is obtained or not is judged by converging the master time slot of the master processor side, the slave time slot of the slave processor side is acquired on the basis of acquiring the accurate master time slot, and the time slot difference between the master processor and the slave processor is acquired so as to facilitate subsequent time synchronous operation. Namely, the embodiment can accurately acquire the instruction time of the master processor for reading the slave processor by using the K times of optimal method, namely, acquire the accurate master time slot so as to improve the timing accuracy.

In an alternative embodiment, the acquiring, by the main processor, the main time slot according to the first main processing time and the third main processing time further includes:

the master processor obtaining the slave time slot from the first slave time and the second slave time further comprises:

wherein Δt is ₁ For the first main time slot, Δt ₂ For the second main time slot, Δt _m As master time slot, t _m1 For the first main processing time, t _m2 For the second main processing time, t _m3 For the third main processing time, Δt _m As the master time slot, Δt _s To be from time slot, t _s1 For the first slave time, t _s2 And is the second slave time.

According to the embodiment, on the basis of acquiring accurate main processing time and accurate slave processing time, a mean value calculation method is used for acquiring the main time slot and the slave time slot, so that timing accuracy is further improved.

In an alternative embodiment of the present invention,

the first synchronization compensation value is: t is t _cpu ＝Δt _m -Δt _s ；

The corrected first presentation time is: t is t _v1 ＝t _m1 +t _cpu ；

The second display time is: t is t _v2 ＝t _m1 +t _soc ；

Wherein t is _cpu For the first synchronization compensation value, t _soc For the second synchronous compensation value, Δt _m As the master time slot, Δt _s To be from time slot, t _v1 For the first presentation time, t _v2 For the second presentation time, t _m1 Is the first main processing time.

The present embodiment uses the time slot difference of the master time slot and the slave time slot as the synchronization compensation value on the master processor side, that is, uses the time synchronization of the slave processor with more accurate time period timing and corrects the time of the master processor, in other words, synchronizes and corrects the time of the master processor with the slave time slot of the slave processor; meanwhile, the time of sending the first reading instruction at the side of the main processor is taken as a timing starting point, the display time of the main processor is corrected by combining the synchronous compensation value of the main processor, and the display time of the main processor and the display time of the slave processor are output, so that the time synchronous precision of the main processor and the slave processor is effectively improved, the operation performance of the heterogeneous system is conveniently analyzed according to the display time of the main processor and the slave processor, and the method has practical application value.

In an alternative embodiment, the step S3 further includes:

outputting the first presentation time and the second presentation time if the time slot difference is less than the time slot threshold, wherein

The first display time is: t is t _v1 ＝t _m1 ；

The second display time is: t is t _v2 ＝t _m1 +Δt _s ；

Wherein t is _v1 For the first presentation time, t _v2 For the second presentation time, t _m1 For the first main processing time, Δt _s Is the slave time slot.

In this embodiment, when the time slot difference is smaller than the time slot threshold, that is, when the master processor and the slave processor are time-synchronized, the first read instruction sending time on the master processor side is used as a timing start point, on the one hand, the presentation time of the master processor is output, and on the other hand, the presentation time of the slave processor is output in combination with the slave time slot of the slave processor, so that the operation performance of the heterogeneous system is conveniently analyzed according to the presentation times of the master processor and the slave processor.

In an alternative embodiment, the read instruction includes:

a first instruction that reads a count register of the slave processor that stores a count value of a cycle counter; and

and reading a second instruction of the frequency register of the slave processor.

The embodiment further reads the frequency value of the slave processor on the basis of the time value of the slave processor read by the master processor, so as to be suitable for the situation that the frequency of the slave processor is changed, namely, the time precision of the slave time slot of the slave processor is further improved by reading the frequency value of the slave processor, so that the time slot synchronization of the slave processor is used and the synchronization compensation value of the master processor is corrected, the time synchronization precision of the master processor and the slave processor is improved, and the operation performance of the heterogeneous system is conveniently analyzed according to the presentation time of the master processor and the slave processor.

In an alternative embodiment, the synchronization method further comprises:

continuously reading the count value of the count register of the slave processor;

and according to a plurality of count values, verifying whether the slave processor operates normally or not by using a preset statistical verification method, and if the slave processor does not operate normally, sending alarm information and stopping the slave processor.

According to the embodiment, the count value of the count register of the slave processor is continuously read by the master processor, and whether the slave processor operates normally is verified by using a statistical verification method according to the read count value, so that the timing accuracy of the slave processor is further improved, the time synchronization accuracy of the master processor and the slave processor is improved, and the operation performance of the heterogeneous system can be conveniently analyzed according to the display time of the master processor and the slave processor.

In an alternative embodiment, the time slot threshold is less than or equal to 20% of the slave time slot.

According to the embodiment, the slave time slot is used as a timing reference, and the time slot threshold is set according to the slave time slot, so that the judging accuracy of whether the master processor and the slave processor are synchronous is further improved, the time synchronization accuracy of the master processor and the slave processor is improved, and the operation performance of the heterogeneous system can be conveniently analyzed according to the display time of the master processor and the slave processor.

A second embodiment of the present invention provides a heterogeneous system applying the synchronization method of the first embodiment, the heterogeneous system including a master processor and at least one slave processor, the master processor being configured to:

The heterogeneous system of the embodiment sends a synchronous test instruction set to a slave processor through a master processor and receives a plurality of returned read data, so that the master processing time of the master processor and the slave processing time of the slave processor are obtained, a master time slot is obtained according to the master processing time, a slave time slot is obtained according to the slave processing time, a time slot difference value is calculated according to the master time slot and the slave time slot, whether the master processor and the slave processor are synchronous or not is judged according to the time slot difference value, and if the master processor and the slave processor are not synchronous, a synchronous compensation value is calculated, and the display time of the master processor and the display time of the slave processor are output; in other words, the time synchronization of the slave processor and the time correction of the master processor are performed by timing the time period more accurately, so that the time synchronization precision of the master processor and the slave processor in the heterogeneous system is effectively improved, the operation performance of the heterogeneous system is conveniently analyzed according to the display time of the master processor and the slave processor, and the method has practical application value.

In an alternative embodiment, the main processor of the heterogeneous system is further configured to:

the step S1 further comprises the following steps:

s103: receiving second read data returned by the slave processor at a third master processing time; the S2 further includes:

According to the embodiment, the main processor sends the reading instruction to the slave processor and acquires the reading data twice in succession, so that three main processing times of the main processor side and two slave processing times of the slave processor side are obtained, and the timing accuracy is effectively improved.

In an alternative embodiment, the set of synchronous test instructions comprises a plurality of sets of synchronous test instructions, each set of synchronous test instructions comprising two read instructions, the main processor of the heterogeneous system being further configured to:

the step S1 further includes:

s01: initializing a storage queue and a test counter;

the S2 further includes:

In the embodiment, the main processor sends a plurality of groups of synchronous test instructions to the slave processor, so that an accurate main time slot is effectively acquired, namely the embodiment can accurately acquire the instruction time of the main processor for reading the slave processor by using the K times of optimal method, in other words, the timing accuracy is improved by acquiring the accurate main time slot.

A third embodiment of the present invention provides a mobile terminal to which the synchronization method of the first embodiment is applied, including a master processor and at least one sensor, each sensor including a slave processor, the master processor being configured to:

The mobile terminal of the embodiment sends a synchronous test instruction set to a sensor slave processor through a master processor and receives a plurality of returned read data, so that the master processing time of the master processor and the slave processing time of the slave processor are obtained, a master time slot is obtained according to the master processing time, a slave time slot is obtained according to the slave processing time, a time slot difference value is calculated according to the master time slot and the slave time slot, whether the master processor and the slave processor are synchronous or not is judged according to the time slot difference value, and if the master processor and the slave processor are not synchronous, a synchronous compensation value is calculated, and the display time of the master processor and the display time of the slave processor are output; in other words, the time synchronization of the slave processor and the time correction of the master processor are performed by timing the time period more accurately, so that the time synchronization precision of the master processor and the slave processor in the mobile terminal is effectively improved, the operation performance of the heterogeneous system is conveniently analyzed according to the display time of the master processor and the slave processor, and the method has practical application value.

A fourth embodiment of the invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in the first embodiment.

A fifth embodiment of the invention provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of the first embodiment when executing the program.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a flow chart of a synchronization method according to an embodiment of the invention;

FIG. 2 shows a schematic diagram of the heterogeneous system according to an embodiment of the present invention;

FIG. 3 shows a partial lane diagram of a synchronization method according to an embodiment of the invention;

FIG. 4 shows a flow chart of a K sub-optimal method according to one embodiment of the invention;

FIG. 5 shows a partial lane diagram of a synchronization method according to another embodiment of the invention;

fig. 6 shows a schematic structural diagram of a computer device according to another embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the present invention, the present invention will be further described with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.

In the prior art, different processors include different architectures and instruction sets, often packaged in the form of a system-on-chip SoC (System on Chip) to improve efficiency and save cost. Also for cost and complexity considerations, often there is no dedicated timing device on the SoC but instead a cycle counter.

In the actual running process, the SoC processor is connected with the server through a PCIe bus or other high-speed buses, and the server and the heterogeneous multi-core SoC processor are provided with respective timing systems. The time information on the respective processors cannot be summed up according to a unified time system, so that the runtime performance analysis of the heterogeneous system cannot be performed.

Aiming at the situation, the inventor has proved through a great deal of researches and experiments that the reason why the heterogeneous system cannot analyze the running performance is that the CPU of the main processor has a clock, and can time an accurate time point, for example, a time point from a certain month, a certain minute, a certain second, a certain millisecond, a certain microsecond, a certain nanosecond and the like to a nanosecond; the SoC processor can only count a certain period of time through the period counter, and the timing rates of different SoC processors have differences, so that the main processor CPU and the SoC processor cannot output the presentation time for the main processor CPU and the presentation time for the SoC processor due to the problem of non-uniform time references, and therefore the two times cannot be unified on a time axis, and then specific operation performance analysis cannot be performed.

Particularly, the frequencies of the CPU and the SoC of the main processor can reach more than 1GHz at present, and if the timing is performed by using the self-contained period counter of the SoC processor, the timing precision can reach the nanosecond level, so that the precision requirement and the instantaneity requirement on the time synchronization of the CPU and the SoC of the main processor are further improved.

In view of the above-described problems and the reasons for the same, as shown in fig. 1, an embodiment of the present invention provides a method for synchronizing inter-core time of a heterogeneous system.

In this embodiment, first, a plurality of read instructions are sent to the slave processor and a plurality of returned read data are received by the master processor, for example, the master processor sends a read instruction to the slave processor and receives read data returned from the slave processor, then the master processor sends a read instruction to the slave processor and receives read data returned from the slave processor, and in multiple interactions between the master processor and the slave processor, a plurality of master processing times of the master processor and a plurality of slave processing times of the slave processor can be obtained from the read data, wherein the master processing time includes a time when the master processor sends the read instruction and a time when the slave processor receives the read data, and the slave processing time is a time when the slave processor receives the read instruction in response to the read instruction after receiving the read instruction of the master processor, and the time is recorded in the read data and returned to the master processor.

In this embodiment, for each read instruction, it is assumed that the time required for transmission of the read instruction and transmission of the read data is the same, that is, the time for the read instruction to reach the slave processor from the master processor is the same as the time for the read data to reach the master processor from the slave processor, for example, the time for the master processor to send the read instruction is denoted as t1, the time for the master processor to receive the read data is denoted as t2, and thus the time difference between t2 and t1 divided by 2 is denoted as the master time slot; similarly, the slave time slots can be acquired according to a plurality of slave processing times, and the method is specific: for example, the time when the slave processor receives the first read instruction is denoted as t3, and since the master processor continuously transmits the read instructions to the slave processor, the time when the master processor receives the read data returned by the first read instruction and the time when the second read instruction is transmitted are defined as the same time node, the time when the slave processor receives the second read instruction is denoted as t4, and the time difference between t4 and t3 is divided by 2 to be the slave time slot.

In an optional embodiment, the master processor sends a read instruction to the slave processor, so as to read a value of a count register corresponding to a cycle counter of the slave processor, that is, the read instruction sent by the master processor is an instruction for reading the register; the main processor receives an instruction that the read data returned by the slave processor is the data fetch from a register of the slave processor and is also a register instruction; thereby avoiding the influence of time precision caused by transfer through the memory in the reading process. In other words, the embodiment has the advantages of short instruction period, quick response time and effective improvement of timing precision and timing efficiency through the register operation of the master processor and the slave processor.

It should be noted that, in this embodiment, the main processing time is a specific time recorded by a clock of the main processor, and the main time slot is obtained by calculating using a difference value between two specific times; the slave processing time is a count value of a cycle counter of the slave processor, and the slave time slot is calculated by using a difference value of the two count values.

Considering that the specific time of the master processor is susceptible to inter-process switching to affect the time precision, the slave processor is only used for executing specific functions, and the timing precision is high, and the synchronization and correction of the master processor and the slave processor are carried out based on the slave time gap of the slave processor.

In the present embodiment, a master time slot is acquired from a master processing time, a slave time slot is acquired from a slave processing time, and a slot difference is calculated from the master time slot and the slave time slot.

And secondly, the main processor judges whether the main processor and the auxiliary processor are synchronous or not according to the time slot difference value, for example, whether the time slot difference value meets the synchronous requirement or not is judged through a preset time slot threshold value. Specifically, when the time slot difference value is greater than the time slot threshold value, the master processor and the slave processor are considered to be unsynchronized, and the master processing time of the master processor needs to be synchronized and corrected; and otherwise, when the time slot difference value is smaller than or equal to the time slot threshold value, the master processor and the slave processor are considered to be synchronous, and synchronization and correction operations are not needed.

In this embodiment, when the master processor and the slave processor are judged to be out of synchronization, the time synchronization of the slave processor and the time of the master processor are corrected by more accurate time period timing, that is, the synchronization and correction of the master processor and the slave processor are performed based on the slave time gap of the slave processor, so that the problem that the time between the processors is out of synchronization due to the difference of the processing rates between the processors is solved, and the time synchronization precision of the master processor and the slave processor is effectively improved.

Specifically, the compensation value of the master processor is calculated according to the master time slot and the slave time slot, so as to compensate the time of the master processor, and meanwhile, the compensation value of the slave processor is calculated for the starting time node according to the specific time of the master processor.

Finally, the master processor corrects the first presentation time of the master processor and outputs the corrected first presentation time of the master processor and the second presentation time of the slave processor.

In this embodiment, on the basis of obtaining the compensation values of the master processor and the slave processor, a specific time of the master processor is taken as a start node to obtain the display time of the master processor and the display time of the slave processor, that is, the display time of the master processor and the display time of the slave processor are unified on a time axis, so that the operation performance of the heterogeneous system can be conveniently analyzed according to the display time of the master processor and the slave processor, and the method has practical application value.

It should be noted that, the number of the read instructions sent from the master processor to the slave processor is not specifically limited, and may be two or more, and those skilled in the art should select the number of the read instructions according to the actual application requirement, so as to obtain the master time slot of the master processor and the slave time slot of the slave processor as design criteria, which are not described herein.

It should be further noted that, when the master processor initiates the read instruction to the slave processor, the present application is not specifically limited, and may be set to perform synchronization judgment and correction according to a fixed time, or may be set to perform synchronization judgment and correction according to a time when the master processor invokes the slave processor, which should be set by a person skilled in the art according to actual application requirements, so as to improve synchronization accuracy of the master processor and the slave processor as a design criterion, and will not be described herein again.

In a specific example, as shown in fig. 2, a heterogeneous system of the present application includes a master processor and a plurality of slave processors, where the number of the slave processors is not specifically limited, and may be one slave processor or a plurality of slave processors, which is not described herein.

As shown in fig. 3, the time synchronization process of the master processor and one slave processor is described in detail:

s1, sending at least two read instructions to a slave processor, receiving a plurality of read data returned by the slave processor, and acquiring main processing time for receiving the read data when the read instructions are sent, wherein the read data comprises slave processing time for the slave processor to respond to the read instructions;

In particular, as shown in FIG. 3,

the first step is that the master processor sends a first read command to a slave processor at a first master processing time tm1, so that the slave processor returns first read data after receiving the first read command, the first read data including a first slave time t _S1 。

A second step of sending a second read command in response to receiving the first read data returned from the slave processor, such that the slave processor returns a second read data including a second slave time t after receiving the second read command _S2 . In this step, the master processor immediately transmits a second read command to the slave processor after receiving the first read data at the second master processing time tm2, that is, if the time of receiving the first read data is the second master processing time, the time of transmitting the second read command is also the second master processing time.

Third, the master processor receives the second read data returned by the slave processor at a third master processing time tm 3.

In this embodiment, the master processor sends the read command to the slave processor and receives the read data twice in succession, and the master processor obtains the time nodes of the three master processors, which are respectively the first master processing time of a specific time tm1, a second main processing time tm2, and a third main processing time tm3; meanwhile, the master processor obtains time nodes of two slave processors according to the read data, wherein the time nodes are respectively counted values of cycle counters of the slave processors: first slave time t _S1 And a second slave time t _S2 。

S2, acquiring a master time slot according to a plurality of master processing times, acquiring a slave time slot according to a plurality of slave processing times, and calculating a time slot difference value between the master time slot and the slave time slot.

In particular, as shown in FIG. 3,

and step four, the main processor acquires the main time slot according to the first main processing time and the third main processing time.

And fifthly, the master processor acquires the slave time slot according to the first slave time and the second slave time.

And sixthly, the main processor calculates a time slot difference value according to the main time slot and the slave time slot.

In this embodiment, the main processor sends the first read command as a time slot Δt, and receives the read data as a time slot Δt, so as to obtain a first main time slot:

meanwhile, the main processor receives the first read data and sends the second read command as the same time node, and then the main processor sends the second read command as a time slot Δt to receive one read data as a time slot Δt, so as to obtain a second main time slot:

The main time slot is acquired by using a mean value calculation method:

that is, the main processor obtains the main time slot delta t of the main processor by sending the read instruction to the slave processor and receiving the read data twice in succession _m 。

Similarly, the first read command is received from the processor and the first read data is sent as a time slot Δt, and the second read command is received from the processor and the second read data is sent as a time slot Δt, so that the slave time slot is obtained:

wherein t is _s1 For the first slave time, t _s2 And is the second slave time.

Based on the obtained master time slot Δt _m And from time slot Δt _s Calculating a time slot difference delta t _m -Δt _s It should be noted that the time slot difference may be either positive or negative, and is only used to characterize the time difference between the master processor and the slave processor.

It is noted that the master time slot may be obtained by a first master processing time and a third master processing time, as will be appreciated by those skilled in the art, e.g. by

And (5) obtaining.

S3, responding to the time slot difference value being larger than a time slot threshold value, acquiring a first synchronous compensation value of the main processor, correcting the first display time of the main processor according to the first synchronous compensation value, and outputting the corrected first display time and the second display time of the auxiliary processor. In this step, it is determined whether the time slot difference is greater than a preset time slot threshold, and if the time slot difference is greater than the time slot threshold, a first synchronization compensation value of the master processor is obtained, and the first presentation time of the master processor is corrected according to the first synchronization compensation value, and the corrected first presentation time and the second presentation time of the slave processor are output.

Specifically, whether the time slot difference value meets the synchronization condition is judged by a preset time slot threshold value, and when the time slot difference value is larger than the time slot threshold value, the main processor and the slave processor are considered to be asynchronous, and the main processing time of the main processor needs to be synchronized and corrected. The present embodiment synchronizes and corrects the time of the master processor by timing the time period more accurately, that is, synchronizing and correcting the master processor and the slave processor with reference to the slave time slot of the slave processor.

In the present embodiment, the master time slot Δt _m And from time slot Δt _s Calculating a time slot difference delta t _m -Δt _s As a first synchronization compensation value of the main processor:

t _cpu ＝Δt _m -Δt _s ；

further, to improve the time synchronization accuracy of the master processor and the slave processor, in an alternative embodiment, the time slot threshold is less than or equal to 20% of the slave time slot.

Based on the first synchronization compensation value of the master processor, the presentation time of the master processor and the presentation time of the slave processor are acquired by taking the specific time of the master processor sending the first read instruction to the slave processor as the start node,

the first display time of the main processor is as follows: t is t _v1 ＝t _m1 +t _cpu ；

The second presentation time of the slave processor is: t is t _v2 ＝t _m1 +Δt _s ；

Thus, the time synchronization process of the master processor and one slave processor is completed.

According to the embodiment, a read instruction is sent to a slave processor through a master processor twice continuously, read data are obtained, so that three master processing times of the master processor side and two slave processing times of the slave processor side are obtained, a master time slot of the master processor side and a slave time slot of the slave processor side are calculated by taking an operating instruction period as a timing reference, a time slot difference between the master processor and the slave processor is obtained, and a preset time slot threshold is used for judging the time slot difference to determine whether the master processor and the slave processor are synchronous or not; when the main processor and the slave processor are not synchronous, calculating compensation values of the main processor and the slave processor by using the slave time slot as a reference, and then sending a specific time of a first reading instruction to the slave processor by the main processor as a starting node, and acquiring a first display time of the main processor by using the first synchronous compensation value of the main processor as a correction value, thereby effectively improving timing accuracy; and meanwhile, the first display time of the main processor and the second display time of the slave processor are unified on a time axis, so that the operation performance of the heterogeneous system can be conveniently analyzed according to the display time of the main processor and the slave processor, and the method has practical application value.

Meanwhile, because the first presentation time which is output by the main processor and represents the main processor time and the second presentation time which represents the slave processor time are synchronized and corrected, in the multi-core heterogeneous system with a plurality of processors, the main processor can respectively perform time synchronization and correction with the plurality of slave processors; the master processor can repeatedly perform time synchronization and correction with respect to a certain slave processor. Specifically, for example, during the operation of the master processor, before different slave processors are invoked to perform different functions, the synchronization method is used to perform synchronization correction to output the presentation time of the master processor and the presentation time of the slave processor with accurate timing.

In view of further improving the accuracy of the master time slot of the master processor, the master time slot is acquired using a K times-optimal method, in an alternative embodiment, as shown in fig. 4, the master processor may send multiple sets of synchronous test instructions to the slave processor, where each set of synchronous test instructions is two read instructions; and the main processor is used for continuously sending a reading instruction to the auxiliary processor twice and acquiring the reading data as one data acquisition, three main processing time can be acquired in each data acquisition process, the main time slots can be acquired according to the three main processing time of the main processor and are stored in a storage queue according to the sequence of numerical values, so that whether the main time slots are converged or not can be judged by utilizing a convergence judgment formula, and when the main time slots meet the convergence judgment formula, the auxiliary time slots are calculated and the time slot difference is acquired, so that the timing accuracy is further improved.

In a specific example, a specific explanation is given as shown in fig. 4:

s1 further comprises the following steps: s01: the main processor initializes a store queue and a test counter.

The present embodiment initializes the store queue and the test counter before the master processor sends a read instruction to the slave processor, for example, empties the store queue to store a plurality of master time slots, clears the test counter, sets a test count threshold, for example, sets the test count threshold to 10.

S1 is a process of data acquisition, and S1 may further include: s121: sending a first read instruction to a slave processor at a first master processing time, such that the slave processor returns first read data after receiving the first read instruction, the first read data including a first slave time; s122: in response to receiving the first read data returned by the slave processor, sending a second read instruction, so that after the slave processor receives the second read instruction, second read data is returned, wherein the second read data comprises a second slave time; s123: and receiving second read data returned by the slave processor at a third master processing time.

As shown in fig. 5, the present embodiment uses the main processor to send the read instruction to the slave processor twice in succession and obtains the read data as one data acquisition, and obtains three main times of the main processor, for example, in the first group of data acquisition, three main times tm1, tm2 and tm3 of the main processor are obtained, and in the nth data acquisition, three main times tm1', tm2' and tm3' of the main processor are obtained.

S2 further comprises: s221: acquiring a plurality of main time slots, storing the main time slots in the storage queue according to the sequence of numerical values, and adding 1 to the count value of the test counter each time the main time slots are acquired; s222: responding to the count value of the test counter being smaller than a preset test count threshold, judging whether the main time slot is converged according to a preset convergence judging formula, and if the main time slot is not converged, sending a reading instruction to a slave processor to acquire the main time slot again; if the main time slot converges, jumping to S223; s223: and calculating a time slot difference value according to the current master time slot and the slave time slot.

S2 further comprises: and in response to the count value of the test counter not being smaller than the preset test count threshold, jumping to S01, namely exiting the program, initializing the storage queue again and restarting to collect data after the test counter is initialized again.

In this embodiment, in each data acquisition, the main time slots are acquired according to three main times and stored in the storage queue in order of magnitude, for example, the main time slots Δt acquired by the three main times tm1, tm2 and tm3 of the main processor at the time of the first data acquisition _m Store in store queue Q [0]]In the main time slot Δt acquired at the nth acquisition of the three main times tm1', tm2' and tm3' of the main processor _m ' and each master time slot Δt in the store queue _m Numerical comparison is performed and the minimum Δt _m Store in store queue Q [0]]In order to facilitate the subsequent determination of whether convergence is occurring.

In one embodiment, assuming a test count threshold of 10, then:

firstly, judging whether the count value of the test counter is greater than or equal to the test count threshold 10, if the count value of the test counter is greater than or equal to the test count threshold 10, considering that the data acquisition has abnormal conditions, exiting the program and sending a read instruction to the slave processor again by the main processor, and if the count value of the test counter is less than the test count threshold 10, continuing to acquire the data.

And secondly, judging whether the main time slot meets a convergence judging formula, for example, whether the main time slot meets (1 + [ epsilon ]) Q [0] = Q [ K-1], wherein Q [ n ] is a storage queue, K is a test counting threshold value, Q [ K-1] is the K main time slot acquired currently, Q [0] is the minimum main time slot in the queue, E is a convergence parameter, when the main time slot meets the convergence judging formula, acquiring an accurate main time slot, acquiring slave time slots according to two slave time acquired at the time of the data acquisition, and calculating a slot difference value.

The embodiment utilizes the main time slot with higher accuracy to acquire the time slot difference value with higher accuracy so as to further judge whether the time slot difference value is larger than the time slot threshold value, further acquire a first synchronous compensation value of the main processor under the condition that the time slot difference value is larger than the time slot threshold value, and correct the first display time of the main processor according to the first synchronous compensation value; thereby further improving the timing accuracy and the timing precision.

In an alternative embodiment, the read instructions include, considering that there is a change in the operating frequency from the processor: a first instruction that reads a count register of the slave processor that stores a count value of a cycle counter; and a second instruction to read a frequency register of the slave processor.

In this embodiment, when the slave processor changes the operating frequency, the time value represented by the count value of the cycle counter changes, and in order to further ensure time synchronization correction of the master processor and the slave processor, the master processor is configured to read not only the count register storing the count value in the slave processor but also the frequency register of the slave processor to obtain the frequency value of the slave processor, so as to accurately acquire the slave time gap of the slave processor. Namely, the time precision of the slave time slot of the slave processor is further improved by reading the frequency value of the slave processor, so that the slave time slot synchronization of the slave processor is used, and the synchronization compensation value of the master processor is corrected, the time synchronization precision of the master processor and the slave processor is improved, and the operation performance of the heterogeneous system is conveniently analyzed according to the presentation time of the master processor and the slave processor.

In an alternative embodiment, the master processor continuously reads the count value of the count register of the slave processor in consideration of the abnormal operation of the slave processor; and the main processor verifies whether the slave processor operates normally or not by using a preset statistical verification method according to a plurality of counting values, and if the slave processor does not operate normally, the main processor sends alarm information and stops the slave processor.

In this embodiment, the count value of the count register of the slave processor is continuously read by the master processor, whether the slave processor operates normally is verified according to a statistical verification method, for example, the obtained count value is verified by using a P-value verification method, the P-value obtained by calculation is compared with the corresponding statistic, so as to determine the possibility of abnormality of the slave processor, when the P-value does not meet the corresponding statistic change, the slave processor is considered to be in an abnormal operation state, at this time, the master processor stops the operation of the slave processor, and the master processor sends alarm information so as to prompt a user to perform fault detection in time, and particularly, the master processor can be set to stop operation so as to avoid more serious faults.

It should be noted that, the time for continuously reading the count value of the counter register of the slave processor is not limited in this embodiment, and may be any time node, and those skilled in the art should understand that when the time for continuously reading the count value of the counter register of the slave processor to determine whether the slave processor has a fault is different from the time for collecting the time difference between the master processor and the slave processor, or the verification process of the slave processor is different from the synchronization correction process of the master processor, the influence of the slave processor verification on the synchronization correction can be avoided, that is, the time precision of the synchronization correction is further improved.

Considering that the time slot difference between the master time slot of the master processor and the slave time slot of the slave processor is less than or equal to the time slot threshold, in an alternative embodiment, if the time slot difference is less than the time slot threshold, the first presentation time and the second presentation time are output, where the time of the master processor does not need to be corrected, and the output first presentation time is: t is t _v1 ＝t _m1 The method comprises the steps of carrying out a first treatment on the surface of the The second display time is: t is t _v2 ＝t _m1 +Δt _s The method comprises the steps of carrying out a first treatment on the surface of the Wherein t is _v1 For the first presentation time, t _v2 For the second presentation time, t _m1 For the first main processing time, Δt _s Is the slave time slot.

In this embodiment, when the time slot difference is smaller than the time slot threshold, that is, when the master processor and the slave processor are time-synchronized, the first read instruction sending time on the master processor side is taken as a timing start point, on the one hand, the presentation time of the master processor is output, and on the other hand, the presentation time of the slave processor is output in combination with the slave time slot of the slave processor, that is, the presentation time of the master processor and the presentation time of the slave processor are unified on a time axis, so that the operation performance of the heterogeneous system is conveniently analyzed according to the presentation times of the master processor and the slave processor.

Corresponding to the synchronization method provided by the above embodiments, an embodiment of the present application further provides a heterogeneous system applying the above synchronization method, and since the heterogeneous system provided by the embodiment of the present application corresponds to the synchronization method provided by the above several embodiments, the foregoing embodiment is also applicable to the heterogeneous system provided by the embodiment, and will not be described in detail in the present embodiment.

As shown in fig. 2, an embodiment of the present application further provides a heterogeneous system applying the above synchronization method, where the heterogeneous system includes a master processor and at least one slave processor, and the master processor is configured to:

The heterogeneous system of the embodiment sends a synchronous test instruction set to a slave processor through a master processor and receives a plurality of returned read data, so that the master processing time of the master processor and the slave processing time of the slave processor are obtained, a master time slot is obtained according to the master processing time, a slave time slot is obtained according to the slave processing time, a time slot difference value is calculated according to the master time slot and the slave time slot, whether the master processor and the slave processor are synchronous or not is judged according to the time slot difference value, and if the master processor and the slave processor are not synchronous, a synchronous compensation value is calculated, and the display time of the master processor and the display time of the slave processor are output; in other words, the time synchronization of the slave processor and the time correction of the master processor are performed by timing the time period more accurately, so that the time synchronization precision of the master processor and the slave processor in the heterogeneous system is effectively improved, the operation performance of the heterogeneous system is conveniently analyzed according to the display time of the master processor and the slave processor, and the method has practical application value. The specific implementation direction of this embodiment is referred to the foregoing embodiments, and will not be described herein.

The step S1 further comprises the following steps:

the S2 further includes:

According to the embodiment, the main processor sends the reading instruction to the slave processor and acquires the reading data twice in succession, so that three main processing times of the main processor side and two slave processing times of the slave processor side are obtained, and the timing accuracy is effectively improved. The specific implementation direction of this embodiment is referred to the foregoing embodiments, and will not be described herein.

In an alternative embodiment, the step S1 further includes:

s01: initializing a storage queue and a test counter;

the S2 further includes:

In an alternative embodiment, each acquisition of a master time slot and a slave time slot includes: :

s121: sending a first read instruction to a slave processor at a first master processing time, such that the slave processor returns first read data after receiving the first read instruction, the first read data including a first slave time;

S122: in response to receiving the first read data returned by the slave processor, sending a second read instruction, so that after the slave processor receives the second read instruction, second read data is returned, wherein the second read data comprises a second slave time;

s123: and receiving second read data returned by the slave processor at a third master processing time.

In the embodiment, the main processor sends a plurality of groups of synchronous test instructions to the slave processor, so that an accurate main time slot is effectively acquired, namely the embodiment can accurately acquire the instruction time of the main processor for reading the slave processor by using the K times of optimal method, in other words, the timing accuracy is improved by acquiring the accurate main time slot. The specific implementation direction of this embodiment is referred to the foregoing embodiments, and will not be described herein.

Based on the synchronization method of the foregoing embodiments, an embodiment of the present application further provides a mobile terminal to which the synchronization method of the first embodiment is applied, including a master processor and at least one sensor, each sensor including a slave processor, where the master processor is configured to:

In this embodiment, the mobile terminal is a smart phone or a tablet personal computer, and includes a main processor and a plurality of sensors, where the sensors include an optical sensor, a gravity sensor, an infrared sensor, a magnetic sensor, a temperature sensor, a gyroscope, an acceleration sensor, an inertial sensor, and the like, and each sensor includes a slave processor, and the smart phone can output display time in synchronization between the main processor and each slave processor so as to analyze the running performance between heterogeneous systems.

Specifically, the mobile terminal sends a synchronous test instruction set to a sensor slave processor through a master processor and receives a plurality of returned read data, so that the master processing time of the master processor and the slave processing time of the slave processor are obtained, a master time slot is obtained according to the master processing time, a slave time slot is obtained according to the slave processing time, a time slot difference value is calculated according to the master time slot and the slave time slot, whether the master processor and the slave processor are synchronous or not is judged according to the time slot difference value, and if the master processor and the slave processor are not synchronous, a synchronous compensation value is calculated, and the display time of the master processor and the display time of the slave processor are output; in other words, the time synchronization of the slave processor and the time correction of the master processor are performed by timing the time period more accurately, so that the time synchronization precision of the master processor and the slave processor in the mobile terminal is effectively improved, the operation performance of the heterogeneous system is conveniently analyzed according to the display time of the master processor and the slave processor, and the method has practical application value. The specific implementation direction of this embodiment is referred to the foregoing embodiments, and will not be described herein.

Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements: s1: transmitting at least two read instructions to a slave processor, receiving a plurality of read data returned by the slave processor, and acquiring main processing time for receiving the read data when the read instructions are transmitted, wherein the read data comprises slave processing time for the slave processor to respond to the read instructions; s2: acquiring a master time slot according to a plurality of master processing times, acquiring a slave time slot according to a plurality of slave processing times, and calculating a time slot difference value between the master time slot and the slave time slot; s3: and responding to the time slot difference value being larger than a time slot threshold value, acquiring a first synchronous compensation value of the main processor, correcting the first display time of the main processor according to the first synchronous compensation value, and outputting the corrected first display time and the second display time of the auxiliary processor.

In practical applications, the computer-readable storage medium may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this embodiment, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

As shown in fig. 6, another embodiment of the present invention provides a schematic structural diagram of a computer device. The computer device 12 shown in fig. 6 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.

As shown in FIG. 6, the computer device 12 is in the form of a general purpose computing device. Components of computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, a bus 18 that connects the various system components, including the system memory 28 and the processing units 16.

Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, and a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Computer device 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by computer device 12 and includes both volatile and nonvolatile media, removable and non-removable media.

The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and/or cache memory 32. The computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 6, commonly referred to as a "hard disk drive"). Although not shown in fig. 6, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 18 through one or more data medium interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of embodiments of the invention.

A program/utility 40 having a set (at least one) of program modules 42 may be stored in, for example, memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 42 generally perform the functions and/or methods of the embodiments described herein.

The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the computer device 12, and/or any devices (e.g., network card, modem, etc.) that enable the computer device 12 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 22. Moreover, computer device 12 may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through network adapter 20. As shown in fig. 6, the network adapter 20 communicates with other modules of the computer device 12 via the bus 18. It should be appreciated that although not shown in fig. 6, other hardware and/or software modules may be used in connection with computer device 12, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

The processor unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, for example, to implement a heterogeneous system inter-core time synchronization method provided by an embodiment of the present invention.

It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A method for synchronizing inter-core time of a heterogeneous system, which is suitable for a main processor, comprising:

2. The synchronization method according to claim 1, wherein,

the step S1 further comprises the following steps:

the S2 further includes:

3. The synchronization method according to claim 1, wherein,

the step S1 further includes:

s01: initializing a storage queue and a test counter;

the S2 further includes:

4. A synchronization method according to any one of the claims 2-3, characterized in that,

The corrected first presentation time is: t is t _v1 ＝t _m1 +t _cpu ；

The second display time is: t is t _v2 ＝t _m1 +Δt _s ；

5. The synchronization method according to any one of claims 2-4, wherein S3 further comprises:

Outputting the first presentation time and the second presentation time in response to the time slot difference being less than the time slot threshold, wherein

The first display time is: t is t _v1 ＝t _m1 ；

The second display time is: t is t _v2 ＝t _m1 +Δt _s ；

6. The synchronization method according to any one of claims 1-5, wherein the read instruction comprises:

7. The synchronization method according to any one of claims 1-6, characterized in that the synchronization method further comprises:

8. The synchronization method according to any one of claims 1-7, wherein the time slot threshold is equal to or less than 20% of the slave time slot.

9. A heterogeneous system applying the synchronization method of any of claims 1-8, the heterogeneous system comprising a master processor and at least one slave processor, the master processor configured to:

10. A mobile terminal applying the synchronization method of any of claims 1-8, comprising a master processor and at least one sensor, each sensor comprising a slave processor, the master processor configured to: