CN116414210A - Application system and method of low-power-consumption storage device - Google Patents

Application system and method of low-power-consumption storage device Download PDF

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Publication number
CN116414210A
CN116414210A CN202111650265.2A CN202111650265A CN116414210A CN 116414210 A CN116414210 A CN 116414210A CN 202111650265 A CN202111650265 A CN 202111650265A CN 116414210 A CN116414210 A CN 116414210A
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memory
special memory
special
operating system
state
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CN202111650265.2A
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江作杰
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Beijing Ingenic Semiconductor Co Ltd
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Beijing Ingenic Semiconductor Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides an application system and a method of a low-power consumption storage device by adding a special memory with low power consumption and a related dormancy and restoration circuit so as to provide simple and rapid preservation and restoration functions, wherein the special memory is added outside a core power supply, a special process of an operating system is utilized to preserve important parameters on the special memory, and then the operating system controls the special memory to enter a deep dormancy mode; in order to ensure that the special memory can normally recover the use state, monitoring logic is added in an auxiliary power domain, so that the special memory can recover the working state in the period that the operating system needs to recover, and important parameter information is read out to the operating system. The method only slightly increases the complexity of the system and the complexity of verification, and can flexibly meet various requirements of an operating system.

Description

Application system and method of low-power-consumption storage device
Technical Field
The present invention relates to the field of memory technologies, and in particular, to an application system and method of a low power consumption memory device.
Background
As chip technology enters deep submicron, power consumption is higher and higher, deep sleep state in the system has become an important function of the system, especially in embedded application environments sensitive to power consumption.
Typical methods include storing important information on a nonvolatile storage medium; or more gating clocks are added in the core power domain to reduce the active state of the core power domain, thereby reducing the power consumption in the standby state.
Prior art schemes include storing important control information on non-volatile storage media, such as Flash controllers, etc.; or adding a gating clock in the core power domain, etc. to reduce power consumption. However, because the Flash controller has slow reading speed and relatively complex control logic, the verification time of the system is continuously increased, the complexity of the system is continuously improved, the gating clock scheme needs to be modified for a plurality of designs, the complexity of the system is also continuously improved, and the verification difficulty is continuously increased.
Furthermore, the common terminology in the prior art is as follows:
gating clock: the clock circuit which can be dynamically opened and closed can be closed to save power consumption when the system does not work; when the system resumes operation, the clock is turned on to operate normally. Nonvolatile storage medium: after the power is turned off, the storage device for storing the content, such as Flash, can be reserved.
Core power domain: the normal operating power domain of the chip supplies power to most of the circuits.
Disclosure of Invention
In order to solve the above problems, the present method aims at: by adding a special memory with extremely low power consumption and a related dormancy and restoration circuit, a simple and rapid preservation and restoration function is provided, and the method can flexibly meet various demands of an operating system by only slightly increasing the complexity of a system and the complexity of verification.
Specifically, the invention provides an application system of a low-power-consumption storage device, which comprises the steps of adding a special memory outside a core power supply domain, storing important parameters on the special memory by utilizing a special process of an operating system, and controlling the special memory to enter a deep sleep state mode by the operating system; in order to ensure that the special memory can normally recover the use state, monitoring logic is added in an auxiliary power domain, so that the special memory can recover the working state in the period that the operating system needs to recover, and important parameter information is read out to the operating system.
The detection logic is used for detecting whether an external wake-up signal exists or not, and if the wake-up signal is changed from 0 to 1, the circuit judges that wake-up is needed;
the monitoring logic further includes a dedicated memory sleep and restore circuit: the special memory enters a deep sleep state and needs a power supply service circuit to generate related control signals; the dedicated memory is in a deep sleep state to resume an operating state, and a power supply service circuit is also required to generate relevant control signals.
The deep sleep state of the private memory is: the memory keeps data not lost and enters a deep sleep state, at the moment, the memory cannot read and write, only the energy consumption of an internal core circuit is maintained, and the consumption current is of a nanoampere level;
the deep sleep recovery time of the dedicated memory is: the memory can not enter the working state immediately from the deep sleep state, and the service circuit is required to configure related signals and wait for a specified time; the waiting deep sleep recovery time is 100 nanoseconds;
the working state of the special memory is as follows: in a normal read-write state, the consumption current is 10 times higher than that in a deep sleep state, and the consumption current is at a microampere level.
The special memory is a low-power-consumption memory, and is extremely low in power consumption in a dormant state; the dedicated memory is a standard on-chip memory unit.
The dedicated process is a dormant process.
The auxiliary power domain is: the chip enters the standby power domain and is only powered by a small number of necessary logics.
The application also relates to an application method of the low-power-consumption storage device, which comprises the following steps:
s1, operating a system on a chip, wherein the operating system prepares important parameter data after calculating that the chip is to be subjected to deep sleep, and informs a special memory to receive the parameter data;
s2, the special memory wakes up from a deep sleep state after receiving the notification, enters an available working state after waiting for the recovery time, and returns operating system information;
s3, the operating system obtains information that the special memory enters a usable working state, and then writes the parameter data into an internal core array of the special memory one by one;
s4, after all parameter data enter a special memory, the special memory enters a low power consumption state again, namely a deep sleep state, and at the moment, the special memory does not accept a read-write request;
s5, after the external environment sends out a wake-up signal, the external wake-up signal enters an auxiliary power domain, and the special memory enters an available working state after waiting for recovery time to perform read-write operation, namely, the memory enters a working mode by enabling a working signal line;
s6, the operating system reads out the needed data from the special memory according to the need;
s7, after the data are read out, the special memory is put into a low-power consumption state again;
s8, the operating system decides whether to update the data in the special memory again according to the saved content.
In the step S5, the external wake-up signal is an input signal received by a nand gate in the auxiliary power domain.
The step S8 further includes, if there is no new saved data, always using the information backed up in the dedicated storage without saving the data again, so as to accelerate the sleep process; if there is a data update, the backup data is added.
Thus, the present application has the advantages that: the method of the special low-power-consumption memory can be well matched with the operating system to complete the deep sleep function, can reduce the standby power consumption of the core power domain, and can simply and rapidly respond to the writing and reading requests of the operating system process.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate and together with the description serve to explain the invention.
Fig. 1 is a schematic diagram of a dedicated memory for the method of the present application.
FIG. 2 is a schematic flow chart of the method of the present invention.
Detailed Description
In order that the technical content and advantages of the present invention may be more clearly understood, a further detailed description of the present invention will now be made with reference to the accompanying drawings.
Aiming at the defect that the existing deep sleep scheme of the system does not have a special low-power-consumption memory, the application system and the method of the low-power-consumption memory device are provided. Adding a special extremely low power consumption memory and a related dormancy and restoration circuit in an auxiliary power domain outside a core power domain according to the dormancy requirement of the whole system; during the non-working period, the device can be in a nanoampere level closing state; during working, the important parameter data is written in cooperation with the system process, and then the system enters a nanoampere level closing state; most of the time, the system is in a closed state with almost no power consumption, and the system is only in a very limited time, and is matched with the process of the operating system to write parameters and read parameter data, so that the state is recovered. And the core power domain realizes the reading of parameters and the working state, so that the parameters needing to be backed up are selected to enter the extremely low power consumption memory.
Technical terms referred to in this application include:
auxiliary power domain: the chip enters the standby power domain and is only powered by a very small number of necessary logics. The working state of the special memory: in a normal read-write state, the consumption current is 10 times higher than that in a deep sleep state, and the consumption current is at a microampere level.
Dedicated memory deep sleep state: the memory keeps data not lost and enters a deep sleep state, at the moment, the memory can not read and write, only the energy consumption of an internal core circuit is maintained, and the consumption current is of a nanoampere level.
Dedicated memory deep sleep resume time: the memory cannot immediately enter an operating state from a deep sleep state, requires a service circuit to configure related signals, and waits for a prescribed time.
Dedicated memory sleep and restore circuitry: the memory enters a dormant state, and a service circuit is required to generate related control signals; the memory is restored to an operating state and the service circuit is also required to generate relevant control signals.
As shown in FIG. 1, the system according to the present application is to add a dedicated memory outside the core power domain, save important parameters to the dedicated memory by using a dedicated process of the operating system, and then control the dedicated memory to enter a deep sleep state mode by the operating system; in order to ensure that the special memory can be normally restored to the use state, a monitoring logic for detecting whether an external wake-up signal exists is added in an auxiliary power domain, so that the special memory can be ensured to restore to the working state in the period that an operating system needs to be restored, and important parameter information is read out to the operating system.
As shown in fig. 2, the method of the present application provides a design method for such a very low power memory circuit and associated sleep and restore circuit. The method comprises the following steps:
s1, after the operation system calculates that deep dormancy is needed, preparing important parameter data, and informing a special memory to receive the parameter data; the special memory is an on-chip SRAM provided by a back-end chip manufacturer and is a standard on-chip memory unit;
s2, the special memory wakes up from a deep sleep state after receiving the notification, and enters an available working state after waiting for a recovery time, which can be generally 100ns, and returns operating system information;
s3, the operating system obtains information that the special memory enters a usable working state, and then writes the parameter data into an internal core array of the memory one by one;
s4, after all parameter data enter a special memory, the special memory enters a low power consumption state again, namely a deep sleep state, and at the moment, the special memory does not accept a read-write request;
s5, after the external environment sends out a wake-up signal, the external wake-up signal enters an auxiliary power domain, and the special memory is set to be generally 100ns after waiting for the recovery time, and enters a readable and writable working state, namely, the memory is enabled to enter a working mode through an enabling working signal line;
s6, the operating system reads out the needed data from the special memory according to the need;
s7, after the data are read out, the special memory is put into a low-power consumption state again;
s8, the operating system decides whether to update the special memory again according to the saved content. If no new data is stored, the information backed up in the special storage is always used, and the data is not required to be stored again, so that the dormancy process is accelerated; if there is a data update, the backup data is added.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations can be made to the embodiments of the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. An application system of a low-power-consumption storage device is characterized in that a special memory is added outside a core power supply domain, an important parameter is saved on the special memory by utilizing a special process of an operating system, and then the operating system controls the special memory to enter a deep sleep state mode; in order to ensure that the special memory can be normally restored to the use state, a monitoring logic for detecting whether an external wake-up signal exists is added in an auxiliary power domain, so that the special memory can be ensured to restore to the working state in the period that an operating system needs to be restored, and important parameter information is read out to the operating system.
2. The application system of a low power memory device of claim 1, wherein the monitor logic further comprises a dedicated memory sleep and restore circuit: the special memory enters a deep sleep state and needs a power supply service circuit to generate related control signals; the special memory is in a deep sleep and resumes working state, and the power supply service circuit is required to generate a related control signal, and in the detection logic, if the Wakeup signal is changed from 0 to 1, the circuit judges that the wake-up is required.
3. The application system of a low power memory device of claim 2, wherein the deep sleep state of the dedicated memory is: the memory keeps data not lost and enters a deep sleep state, at the moment, the memory cannot read and write, only the energy consumption of an internal core circuit is maintained, and the consumption current is of a nanoampere level;
the deep sleep recovery time of the dedicated memory is: the memory can not enter the working state immediately from the deep sleep state, and the service circuit is required to configure related signals and wait for a specified time;
the waiting deep sleep recovery time is 100 nanoseconds;
the working state of the special memory is as follows: in a normal read-write state, the consumption current is 10 times higher than that in a deep sleep state, and the consumption current is at a microampere level.
4. The application system of a low power memory device according to claim 1, wherein the dedicated memory is a low power memory, which is very low power in a sleep state; the dedicated memory is a standard on-chip memory unit.
5. The application system of a low power memory device of claim 1, wherein the dedicated process is a sleep process.
6. The application system of a low power memory device of claim 1, wherein said auxiliary power domain is: the chip enters the standby power domain and is only powered by a small number of necessary logics.
7. A method for applying a low power consumption memory device, the method comprising the steps of:
s1, operating a system on a chip, wherein the operating system prepares important parameter data after calculating that the chip is to be subjected to deep sleep, and informs a special memory to receive the parameter data;
s2, the special memory wakes up from a deep sleep state after receiving the notification, enters an available working state after waiting for the recovery time, and returns operating system information;
s3, the operating system obtains information that the special memory enters a usable working state, and then writes the parameter data into an internal core array of the special memory one by one;
s4, after all parameter data enter a special memory, the special memory enters a low power consumption state again, namely a deep sleep state, and at the moment, the special memory does not accept a read-write request;
s5, after the external environment sends out a wake-up signal, the external wake-up signal enters an auxiliary power domain, and the special memory enters an available working state after waiting for recovery time to perform read-write operation, namely, the memory enters a working mode by enabling a working signal line;
s6, the operating system reads out the needed data from the special memory according to the need;
s7, after the data are read out, the special memory is put into a low-power consumption state again;
s8, the operating system decides whether to update the data in the special memory again according to the saved content.
8. The method according to claim 7, wherein in the step S5, the external wake-up signal is an input signal received by a nand gate in an auxiliary power domain.
9. The method according to claim 7, wherein the step S8 further comprises, if there is no new data to be saved, always using the information backed up in the dedicated memory without saving the data again, thereby accelerating the hibernation process; if there is a data update, the backup data is added.
10. The method of claim 7, wherein the wait recovery time is 100ns.
CN202111650265.2A 2021-12-30 2021-12-30 Application system and method of low-power-consumption storage device Pending CN116414210A (en)

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Application Number Priority Date Filing Date Title
CN202111650265.2A CN116414210A (en) 2021-12-30 2021-12-30 Application system and method of low-power-consumption storage device

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Application Number Priority Date Filing Date Title
CN202111650265.2A CN116414210A (en) 2021-12-30 2021-12-30 Application system and method of low-power-consumption storage device

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CN116414210A true CN116414210A (en) 2023-07-11

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