CN116399489B - High-temperature silicon-based photoelectric pressure sensing chip for system-on-chip integration - Google Patents
High-temperature silicon-based photoelectric pressure sensing chip for system-on-chip integration Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 56
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/24—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet
- G01L1/242—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet the material being an optical fibre
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L11/00—Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by means not provided for in group G01L7/00 or G01L9/00
- G01L11/02—Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by means not provided for in group G01L7/00 or G01L9/00 by optical means
- G01L11/025—Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by means not provided for in group G01L7/00 or G01L9/00 by optical means using a pressure-sensitive optical fibre
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Optical Integrated Circuits (AREA)
Abstract
The application discloses a high-temperature silicon-based photoelectric pressure sensing chip integrated towards a system on a chip, which comprises the following steps: the method comprises a Fabry-Perot cavity deep etching step, a sacrificial layer filling step, an optical waveguide manufacturing step, a sacrificial layer releasing step and an airtight packaging step. The application adopts a microelectronic deep etching method to directly manufacture the Fabry-Perot cavity in the vertical direction on the silicon wafer on the insulator, and utilizes the monocrystalline silicon of the device layer and the silicon dioxide of the buried oxide layer of the silicon wafer on the insulator to manufacture the silicon-based optical waveguide for transmitting the light beam, thereby being completely compatible with the microelectronic process and having higher production efficiency. Meanwhile, the manufacturing process directly manufactures the silicon-based photoelectron sensing chip on the silicon wafer, is beneficial to realizing the monolithic integration of photoelectric mixing of the silicon-based microelectronic chip on the wafer, and further improves the performance of the system. In addition, the silicon-based Fabry-Perot pressure sensing chip manufactured on the wafer can work in a high-temperature environment with the temperature of more than 120 ℃.
Description
Technical Field
The application belongs to the technical field of electronics, and particularly relates to a high-temperature silicon-based photoelectric pressure sensing chip for system-on-a-chip integration.
Background
Since the fabry-perot Luo Faming multi-beam interferometer, a variety of fabry-perot sensors based on the multi-beam interference principle have been developed, and the fabry-perot pressure sensor is one of typical applications. The traditional Fabry-Perot pressure sensor mainly comprises an optical fiber, namely a vacuum Fabry-Perot cavity containing a pressure sensitive membrane and an optical fiber. The optical fiber Fabry-Perot type pressure sensor has the advantages of strong electromagnetic interference resistance, high measurement precision and capability of working in a high-temperature environment. But the processing of the vacuum Fabry-Perot cavity and the assembly of the optical fiber and the vacuum Fabry-Perot cavity are generally carried out by the traditional mechanical processing mode. The production efficiency is low, and the monolithic integration with the integrated circuit chip cannot be realized.
With the development of microelectronic fabrication processes and silicon-based optoelectronic technologies, the monolithic integration of photonic devices and electronic devices on silicon wafers by microelectronic processes has become a hotspot for research. The photoelectric hybrid integrated circuit integrates the photoelectric device and the microelectronic device, and realizes the combination of the advantages of the integrated circuit technology and the optical interconnection technology. On one hand, the photoelectric hybrid integration greatly shortens the interconnection length and improves the integration level; on the other hand, the optical interconnection improves the communication speed and the transmission bandwidth of a big data system and improves the performance of an integrated circuit system. In addition, the silicon-based optoelectronic device can be manufactured rapidly, in large batch and with high precision based on the microelectronic manufacturing process, and the production efficiency of the optoelectronic device is remarkably improved.
Disclosure of Invention
The embodiment of the application aims to provide a high-temperature silicon-based photoelectric pressure sensing chip integrated towards a system on a wafer, which is characterized in that a vertical Fabry-Perot cavity is directly manufactured on a silicon-on-insulator (SOI) wafer by a microelectronic deep etching method instead of a traditional optical fiber type device structure and a manufacturing process, and meanwhile, a silicon-based optical waveguide for light beam transmission is manufactured on device layer monocrystalline silicon and buried oxide silicon dioxide of the SOI wafer. Compared with the traditional manufacturing method of the optical fiber Fabry-Perot pressure sensor, the manufacturing method provided by the application is completely compatible with an integrated circuit process, can realize photoelectric hybrid integration on a crystal, and greatly improves the production efficiency and the system performance.
According to a first aspect of an embodiment of the present application, there is provided a high temperature silicon-based photoelectric pressure sensing chip integrated on a wafer, the method for manufacturing the chip comprising:
deep etching of the Fabry-Perot cavity: photoetching and deeply etching silicon, silicon dioxide with an oxygen-buried layer and substrate silicon on a silicon wafer on an insulator to form an open Fabry-Perot cavity, a vertical pressure sensitive membrane and an air inlet groove;
and a sacrificial layer filling step: filling sacrificial layer materials with temporary supporting function in the Fabry-Perot cavity and the air inlet groove of the opening, and depositing a sealing layer on the front surface of the wafer;
and an optical waveguide manufacturing step: photoetching a device layer of a wafer to form a core layer of the monocrystalline silicon optical waveguide, depositing a silicon dioxide layer on the upper surface of the wafer, and wrapping the core layer to form a cladding layer of the monocrystalline silicon optical waveguide;
sacrificial layer release step: removing the sacrificial layer material which plays a temporary supporting role from the Fabry-Perot cavity of the opening and filling the air inlet groove;
and (3) airtight packaging: and sealing the Fabry-Perot cavity of the opening under vacuum condition.
Further, in the step of filling the sacrificial layer, the sacrificial layer material is filled by adopting a mode of alternately spin-coating and baking photoresist for a plurality of times or a mode of spraying photoresist.
Further, the optical waveguide manufacturing step includes:
photoetching a device layer of a silicon-on-insulator wafer to form a core layer of the monocrystalline silicon optical waveguide;
depositing a silicon dioxide layer on the front surface of the silicon wafer on the insulator, and wrapping the core layer by using silicon dioxide of an oxygen buried layer of the silicon wafer on the insulator to form a cladding layer of the monocrystalline silicon optical waveguide;
the deep trench is formed into a process plane by temporarily filling material in the optical waveguide region.
Further, the axis of the core layer coincides with the central axis of the vertical pressure sensitive membrane.
Further, the sacrificial layer releasing step includes:
photoetching the open Fabry-Perot cavity and the silicon dioxide layer above the air inlet groove to form a Fabry-Perot cavity release hole and an air inlet groove release hole of the sacrificial layer material respectively;
and removing the temporarily supported sacrificial layer material through the Fabry-Perot cavity release hole and the air inlet groove release hole.
Further, in the airtight packaging step, the open fabry-perot cavity release hole is sealed by depositing a sealing structure under vacuum conditions; the sealing structure comprises metal paste, glass paste, polyimide, SU8, BCB, silicon dioxide, epoxy resin, a metal coating, a glass wafer containing sodium ions and a silicon wafer; the deposition method of the sealing structure comprises screen printing, flip bonding, chemical vapor deposition, sacrificial layer adhesion effect method, anodic bonding, hot-press bonding and laser local heating.
According to a second aspect of the embodiment of the present application, there is provided a fabry-perot pressure sensing chip with a differential function, monolithically integrated with a capacitive pressure sensing chip by the fabry-perot pressure sensing chip with a vertical sensitive membrane, the method for manufacturing the pressure sensor comprising:
deep etching of the Fabry-Perot cavity: photoetching and deeply etching silicon, silicon dioxide with an oxygen-buried layer and substrate silicon on a silicon wafer on an insulator to form an open Fabry-Perot cavity, a vertical pressure sensitive membrane and an air inlet groove;
and a sacrificial layer filling step: filling sacrificial layer materials with temporary supporting function in the Fabry-Perot cavity and the air inlet groove of the opening, and depositing a sealing layer on the front surface of the wafer;
and an optical waveguide manufacturing step: photoetching a device layer of a wafer to form a core layer of the monocrystalline silicon optical waveguide, depositing a silicon dioxide layer on the upper surface of the wafer, and wrapping the core layer to form a cladding layer of the monocrystalline silicon optical waveguide;
a first sacrificial layer release step: removing a sacrificial layer material filled in the air inlet groove and having a temporary supporting effect;
parallel plate capacitance manufacturing step: depositing a silicon dioxide layer with an electric insulation and isolation function on the inner wall of the air inlet groove, and depositing a metal layer on the outer side wall of the Fabry-Perot cavity and the opposite side wall of the Fabry-Perot cavity to serve as a polar plate of a parallel plate capacitor;
a second sacrificial layer release step: removing sacrificial layer materials which play a temporary supporting role from the Fabry-Perot cavity of the opening;
and (3) airtight packaging: and sealing the Fabry-Perot cavity of the opening under vacuum condition.
Further, the parallel plate capacitor manufacturing step includes:
depositing a silicon dioxide layer with an electric insulation and isolation function on the inner wall of the air inlet groove;
depositing a metal layer on the outer side wall of the sealed vacuum Fabry-Perot cavity and the opposite side wall of the vacuum Fabry-Perot cavity to serve as a polar plate of the parallel plate capacitor;
and leading out the polar plate of the parallel plate capacitor to the upper surface of the wafer to form a bonding pad.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
firstly, a microelectronic deep etching method is adopted to directly manufacture a Fabry-Perot cavity in the vertical direction on an SOI wafer, and meanwhile, a silicon-based optical waveguide for light beam transmission is manufactured by utilizing device layer monocrystalline silicon and buried oxide layer silicon dioxide of the SOI wafer, so that the method is completely compatible with a microelectronic process and can be used for large-scale batch production;
secondly, the manufacturing process directly manufactures the silicon-based photoelectron sensing chip on the silicon wafer, which is beneficial to realizing the monolithic integration of photoelectric mixing of the silicon-based microelectronic chip on the wafer and improving the performance of the system;
third, the silicon-based Fabry-Perot pressure sensing chip manufactured on the wafer can work in a high-temperature environment with the temperature of more than 120 ℃.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a flow chart of a manufacturing process of a high temperature silicon-based photoelectric pressure sensing chip integrated on a wafer, wherein (a) in FIG. 1 to (h) in FIG. 1 are wafer sectional views in each flow;
FIG. 2 is a flow chart of a manufacturing process of a high temperature silicon-based photoelectric pressure sensor chip integrated on a wafer, wherein (a) in FIG. 2 to (g) in FIG. 2 are top views of wafers in each flow;
FIG. 3 is a schematic diagram of a three-dimensional structure of a high temperature silicon-based photoelectric pressure sensor chip integrated on a wafer;
fig. 4 is a schematic diagram of an operating principle of a high-temperature silicon-based photoelectric pressure sensor chip integrated on a wafer, wherein (a) in fig. 4 is a cross-sectional view of the wafer, and (b) in fig. 4 is a top view of the wafer;
fig. 5 is a schematic structural diagram of a fabry-perot pressure sensing chip with differential function;
fig. 6 is a schematic structural diagram of a dual-sided fabry-perot pressure sensor chip with differential functionality.
Reference numerals: the SOI wafer 1, an oxygen-buried layer silicon dioxide 2, a Fabry-Perot cavity 3, a vertical pressure sensitive membrane 4, an air inlet groove 5, a sacrificial layer material 6, an upper surface silicon dioxide layer 7, a core layer 8, a cladding layer 9, a material 10, a Fabry-Perot cavity release hole 11, an air inlet groove release hole 12, a sealing structure 13, a vacuum Fabry-Perot cavity 14, a first interface 15, a second interface 16, a silicon dioxide layer 17 and a polar plate 18.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
The following description will take the fabry-perot pressure sensing chip based on the SOI as an example, but the application scope of the present application is not limited to the fabry-perot pressure sensing chip and the SOI wafer, and is also applicable to the manufacture of other sensing chips having a vertical direction sensitive structure.
Fig. 1 shows a cross-sectional view (left) and a top view (right) of a fabrication process flow of a fabry-perot pressure sensing chip with vertical sensitive film based on an SOI wafer. The chip is manufactured in this embodiment with the SOI wafer 1 having a thicker device layer as the material ((a) in fig. 1).
Deep etching of the Fabry-Perot cavity 3: on the device layer of the SOI wafer 1, device layer silicon, buried oxide layer silicon dioxide 2 and substrate silicon are etched by photolithography and deep etching to form an open Fabry-Perot cavity 3, a vertical pressure sensitive membrane 4 and an air inlet groove 5 ((b) in FIG. 1 and (a) in FIG. 2).
And a sacrificial layer filling step: a sacrificial layer material 6 with a temporary supporting function is filled in the open Fabry-Perot cavity 3 and the air inlet groove 5, and a sealing layer is deposited on the front surface of the wafer; the method comprises the following steps:
firstly, the sacrificial layer material 6 with temporary supporting function is filled in the open Fabry-Perot cavity 3 and the air inlet groove 5, preferably in a mode of alternately spin-coating, baking photoresist or spraying photoresist for a plurality of times. Then, a sealing layer is deposited on the front side of the SOI wafer, wherein the material of the sealing layer includes but is not limited to polyimide, SU8, BCB, silicon dioxide, and the upper surface silicon dioxide layer 7 is preferably deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) (fig. 1 (c), fig. 2 (b)).
And an optical waveguide manufacturing step: photoetching a device layer of a wafer to form a core layer 8 of the monocrystalline silicon optical waveguide, depositing a silicon dioxide layer on the upper surface of the wafer, and wrapping the core layer 8 to form a cladding layer 9 of the monocrystalline silicon optical waveguide; the method comprises the following steps:
the device layer of the SOI wafer is lithographically etched to form a core layer 8 of monocrystalline silicon optical waveguide ((d) in fig. 1, (c) in fig. 2), wherein the axis of the core layer 8 should coincide with the central axis of the vertical pressure sensitive membrane 4.
A silicon dioxide layer is deposited on the upper surface of the SOI wafer by PECVD, and the core layer 8 is wrapped with the buried oxide layer silicon dioxide 2 of the SOI wafer, thereby forming a cladding layer 9 of the single crystal silicon optical waveguide ((e) in fig. 1, and (d) in fig. 2).
The optical waveguide region is temporarily filled with material 10 to form a process plane for deep trench formation, preferably by alternately spin-coating, baking or spraying photoresist a plurality of times.
Sacrificial layer release step: removing the sacrificial layer material 6 which plays a temporary supporting role from the Fabry-Perot cavity 3 and the air inlet groove 5 which are provided with the openings;
specifically, the open fabry-perot cavity 3, the upper surface silicon dioxide layer 7 above the air intake groove 5 are lithographically etched, and the fabry-perot cavity release hole 11 and the air intake groove release hole 12 of the sacrificial layer material 6 are formed, respectively (f) in fig. 1, and (e) in fig. 2). The temporarily supported sacrificial layer material 6 and the temporarily filled material 10 of the optical waveguide region are removed preferably with acetone or a desmear solution (fig. 1 (g), fig. 2 (f)).
And (3) airtight packaging: sealing the open Fabry-Perot cavity 3 under vacuum;
specifically, under vacuum condition, the fabry-perot cavity release hole 11 is sealed by depositing a sealing structure 13, as shown in (h) in fig. 1 and (g) in fig. 2, an absolute vacuum fabry-perot cavity 14 with a vertical sensitive membrane is formed, and meanwhile, the high-temperature silicon-based photoelectric pressure sensing chip integrated towards the system on a chip is formed. The material of the sealing structure 13 includes, but is not limited to, metal paste, glass paste, polyimide, SU8, BCB, silicon dioxide, epoxy, metal plating, sodium ion-containing glass wafer, silicon wafer, etc. Deposition methods of the sealing structure 13 include, but are not limited to, screen printing, flip chip bonding, chemical vapor deposition, sacrificial layer adhesion effect methods, anodic bonding, thermocompression bonding, laser localized heating, and the like.
Fig. 3 is a schematic three-dimensional structure diagram of a high-temperature silicon-based photoelectric pressure sensing chip integrated on a wafer, and fig. 4 is a schematic working principle diagram of a high-temperature silicon-based photoelectric pressure sensing chip integrated on a wafer. As shown in fig. 3 and 4, the working principle of the fabry-perot pressure sensing chip with the vertical sensitive film is that when a light beam enters from the core layer 8 of the single crystal silicon optical waveguide to the vacuum fabry-perot cavity 14, the incident light beam will generate reflection at the first interface 15 and the second interface 16, and the two reflected light beams interfere. When the external pressure is increased, the central deformation of the vertical pressure sensitive membrane 4 is increased, and the cavity length of the vacuum Fabry-Perot cavity 14 is shortened. The pressure applied to the vertical pressure sensitive membrane 4 can be calculated by demodulating and determining the variation of the cavity length. The process steps are carried out on the silicon wafer, and the monocrystalline silicon optical waveguide and the silicon-based Fabry-Perot cavity which form the Fabry-Perot pressure sensing chip are both made of high-temperature resistant materials, so that the Fabry-Perot pressure sensing chip can work in a high-temperature environment with the temperature of more than 120 ℃. In addition, the vertical deep-slot parallel plate capacitor structure occupies a small chip area, does not depend on complex silicon-silicon and silicon-glass bonding processes, and is beneficial to realizing photoelectric monolithic integration on a wafer with a signal processing part.
The application also provides a Fabry-Perot type pressure sensing chip with a vertical sensitive membrane and a capacitive pressure sensing chip which are monolithically integrated, wherein the Fabry-Perot type pressure sensing chip is shown in fig. 5 and has a differential function. The preparation method of the pressure sensor comprises the following steps:
deep etching of the Fabry-Perot cavity 3: photoetching and deeply etching silicon, silicon dioxide with an oxygen-buried layer 2 and substrate silicon on a silicon-on-insulator wafer to form an open Fabry-Perot cavity 3, a vertical pressure sensitive membrane 4 and an air inlet groove 5;
and a sacrificial layer filling step: a sacrificial layer material 6 with a temporary supporting function is filled in the open Fabry-Perot cavity 3 and the air inlet groove 5, and a sealing layer is deposited on the front surface of the wafer;
and an optical waveguide manufacturing step: photoetching a device layer of a wafer to form a core layer 8 of the monocrystalline silicon optical waveguide, depositing a silicon dioxide layer on the upper surface of the wafer, and wrapping the core layer 8 to form a cladding layer 9 of the monocrystalline silicon optical waveguide;
a first sacrificial layer release step: removing the sacrificial layer material 6 filled in the air inlet groove 5 and serving as temporary support;
parallel plate capacitance manufacturing step: a silicon dioxide layer 17 with an electric insulation and isolation function is deposited on the inner wall of the air inlet groove 5, and a metal layer is deposited on the outer side wall of the Fabry-Perot cavity 3 and the opposite side wall of the Fabry-Perot cavity as a polar plate 18 of a parallel plate capacitor;
a second sacrificial layer release step: removing the sacrificial layer material 6 which plays a temporary supporting role from the Fabry-Perot cavity 3 with the opening;
and (3) airtight packaging: the open fabry-perot cavity 3 is sealed under vacuum.
Specifically, the difference between the method and the method for manufacturing the high-temperature silicon-based photoelectric pressure sensing chip integrated on the wafer is that after the optical waveguide manufacturing step, the sacrificial layer material in the air inlet groove is required to be released firstly, and the silicon dioxide layer 17 with the electric insulation and isolation functions is deposited on the inner wall of the air inlet groove 5; then, depositing a metal layer on the outer side wall of the Fabry-Perot cavity 3 and the opposite side wall thereof to serve as a polar plate 18 of the parallel plate capacitor; the plate 18 is then led out to the wafer upper surface to form a pad 19. The sacrificial layer material in the open fabry-perot cavity and the material 10 temporarily filling the optical waveguide region are released again.
The working principle of the photoelectric integrated Fabry-Perot type pressure sensing chip with the differential function is that when the external pressure is increased, the central deformation amount of the pressure sensitive membrane 4 in the vertical direction is increased, and the cavity length of the vacuum Fabry-Perot cavity 14 is shortened; and the pitch of the parallel plate capacitor becomes larger, that is, the width pitch of the air intake groove 5 becomes larger. Therefore, the corresponding pressure change can be obtained by detecting the phase change and the capacitance change of the reflected light caused by the short cavity length and the large space, and the pressure signal is further amplified.
Fig. 6 is a schematic structural diagram of a dual-sided fabry-perot pressure sensor chip with differential functionality. The cavity length of the Fabry-Perot cavity on the absolute pressure side is shortened under the action of pressure, and the cavity length of the Fabry-Perot cavity on the side communicated with the external gas is lengthened, so that a differential structure is formed, and the differential structure has the function of further amplifying pressure signals.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (7)
1. The high-temperature silicon-based photoelectric pressure sensing chip integrated towards the system on a chip is characterized in that the preparation method of the chip comprises the following steps:
(1) Deep etching of the Fabry-Perot cavity: photoetching and deeply etching silicon, silicon dioxide with an oxygen-buried layer and substrate silicon on a silicon wafer on an insulator to form an open Fabry-Perot cavity, a vertical pressure sensitive membrane and an air inlet groove;
(2) And a sacrificial layer filling step: filling sacrificial layer materials with temporary supporting function in the Fabry-Perot cavity and the air inlet groove of the opening, and depositing a sealing layer on the front surface of the wafer;
(3) And an optical waveguide manufacturing step: photoetching a device layer of a wafer to form a core layer of the monocrystalline silicon optical waveguide, depositing a silicon dioxide layer on the upper surface of the wafer, and wrapping the core layer to form a cladding layer of the monocrystalline silicon optical waveguide;
(4) Sacrificial layer release step: removing the sacrificial layer material which plays a temporary supporting role from the Fabry-Perot cavity of the opening and filling the air inlet groove; the method comprises the following steps: photoetching the open Fabry-Perot cavity and the silicon dioxide layer above the air inlet groove to form a Fabry-Perot cavity release hole and an air inlet groove release hole of the sacrificial layer material respectively; removing the temporarily supported sacrificial layer material through the Fabry-Perot cavity release hole and the air inlet groove release hole;
(5) And (3) airtight packaging: and sealing the Fabry-Perot cavity of the opening under vacuum condition.
2. The chip of claim 1, wherein in the sacrificial layer filling step, the sacrificial layer material is filled by alternately spin-coating, baking a photoresist, or spraying a photoresist a plurality of times.
3. The chip of claim 1, wherein the optical waveguide fabrication step comprises:
photoetching a device layer of a silicon-on-insulator wafer to form a core layer of the monocrystalline silicon optical waveguide;
depositing a silicon dioxide layer on the front surface of the silicon wafer on the insulator, and wrapping the core layer by using silicon dioxide of an oxygen buried layer of the silicon wafer on the insulator to form a cladding layer of the monocrystalline silicon optical waveguide;
the deep trench is formed into a process plane by temporarily filling material in the optical waveguide region.
4. A chip as claimed in claim 3, wherein the axis of the core coincides with the central axis of the vertically oriented pressure sensitive membrane.
5. The chip of claim 1, wherein in the hermetically sealing step, the open fabry-perot cavity is sealed by depositing a sealing structure under vacuum; the sealing structure comprises metal paste, glass paste, polyimide, SU8, BCB, silicon dioxide, epoxy resin, a metal coating, a glass wafer containing sodium ions and a silicon wafer; the deposition method of the sealing structure comprises screen printing, flip bonding, chemical vapor deposition, sacrificial layer adhesion effect method, anodic bonding, hot-press bonding and laser local heating.
6. The Fabry-Perot type pressure sensing chip with the differential function is characterized in that the Fabry-Perot type pressure sensing chip with the vertical sensitive membrane is monolithically integrated with the capacitive pressure sensing chip, and the preparation method of the pressure sensor comprises the following steps:
(1) Deep etching of the Fabry-Perot cavity: photoetching and deeply etching silicon, silicon dioxide with an oxygen-buried layer and substrate silicon on a silicon wafer on an insulator to form an open Fabry-Perot cavity, a vertical pressure sensitive membrane and an air inlet groove;
(2) And a sacrificial layer filling step: filling sacrificial layer materials with temporary supporting function in the Fabry-Perot cavity and the air inlet groove of the opening, and depositing a sealing layer on the front surface of the wafer;
(3) And an optical waveguide manufacturing step: photoetching a device layer of a wafer to form a core layer of the monocrystalline silicon optical waveguide, depositing a silicon dioxide layer on the upper surface of the wafer, and wrapping the core layer to form a cladding layer of the monocrystalline silicon optical waveguide;
(4) A first sacrificial layer release step: removing a sacrificial layer material filled in the air inlet groove and having a temporary supporting effect; the method comprises the following steps: photoetching the open Fabry-Perot cavity and the silicon dioxide layer above the air inlet groove to form a Fabry-Perot cavity release hole and an air inlet groove release hole of the sacrificial layer material respectively; removing the temporarily supported sacrificial layer material through the Fabry-Perot cavity release hole and the air inlet groove release hole;
(5) Parallel plate capacitance manufacturing step: depositing a silicon dioxide layer with an electric insulation and isolation function on the inner wall of the air inlet groove, and depositing a metal layer on the outer side wall of the Fabry-Perot cavity and the opposite side wall of the Fabry-Perot cavity to serve as a polar plate of a parallel plate capacitor;
(6) A second sacrificial layer release step: removing sacrificial layer materials which play a temporary supporting role from the Fabry-Perot cavity of the opening;
(7) And (3) airtight packaging: and sealing the Fabry-Perot cavity of the opening under vacuum condition.
7. The chip of claim 6, wherein the parallel plate capacitor fabrication step comprises:
depositing a silicon dioxide layer with an electric insulation and isolation function on the inner wall of the air inlet groove;
depositing a metal layer on the outer side wall of the sealed vacuum Fabry-Perot cavity and the opposite side wall of the vacuum Fabry-Perot cavity to serve as a polar plate of the parallel plate capacitor;
and leading out the polar plate of the parallel plate capacitor to the upper surface of the wafer to form a bonding pad.
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