CN116346060B - Signal gain adjusting circuit - Google Patents
Signal gain adjusting circuit Download PDFInfo
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- CN116346060B CN116346060B CN202310277018.5A CN202310277018A CN116346060B CN 116346060 B CN116346060 B CN 116346060B CN 202310277018 A CN202310277018 A CN 202310277018A CN 116346060 B CN116346060 B CN 116346060B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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Abstract
The invention discloses a signal gain adjusting circuit, which comprises a gain adjusting module, a signal rectifying module, a level comparing module, a NAND gate, a first diode, a second diode and a clock signal generating module, wherein the signal rectifying module is connected with the gain adjusting module; the output end of the signal rectifying module is connected with the input end of the level comparison module, the first output end and the second output end of the level comparison module are connected with the gain adjustment module, the first input end of the clock signal generation module is connected with the first output end of the level comparison module, the second input end of the clock signal generation module is connected with the second output end of the level comparison module, and the output end of the clock signal generation module is connected with the gain adjustment module. The invention only needs to automatically detect the signal level through the level comparison module and feeds back the signal level to the digital adjustable resistor according to the detection result, so that the digital adjustable resistor can adjust the resistance value of the digital adjustable resistor up or down, and the signal gain of the gain adjustment module is automatically adjusted.
Description
Technical Field
The present invention relates to the field of signal gain technologies, and in particular, to a signal gain adjusting circuit.
Background
The signal input adjustment gain in the signal system device is very necessary, and most circuits need to use an automatic gain control circuit, but a mechanical potentiometer is commonly used in the prior art to adjust the signal gain, i.e. the potentiometer needs to be manually adjusted by people in the prior art scheme to realize the gain adjustment of the circuit, i.e. the prior art cannot realize the automatic adjustment of the signal gain of the circuit.
Disclosure of Invention
The embodiment of the invention provides a signal gain adjusting circuit, which solves the problem that the signal gain of the circuit cannot be automatically adjusted in the prior art.
The embodiment of the invention provides a signal gain adjusting circuit, which comprises a gain adjusting module, a signal rectifying module, a level comparing module, a NAND gate, a first diode, a second diode and a clock signal generating module;
the gain adjustment module comprises a first capacitor, a first resistor, a first amplifier and a digital adjustable resistor;
the first end of the first capacitor is connected with an external signal source, the second end of the first capacitor is connected with the first end of a first resistor, the second end of the first resistor is connected with the inverting input end of a first amplifier and the VH pin of a digital adjustable resistor respectively, the non-inverting input end of the first amplifier is grounded, the output end of the first amplifier is used for outputting a signal after gain adjustment, the output end of the first amplifier is connected with the VW pin of the digital adjustable resistor and the input end of a signal rectifying module respectively, the output end of the signal rectifying module is connected with the input end of a level comparison module, the first output end of the level comparison module, a first diode and the U/D pin of the digital adjustable resistor are sequentially connected, the second output end of the level comparison module, a NAND gate, a second diode and the U/D pin of the digital adjustable resistor are sequentially connected, the first input end of a clock signal generating module is connected with the first output end of the level comparison module, the output end of the clock signal generating module is connected with the output end of the clock signal generating module;
the signal rectifying module is used for rectifying the level when receiving the level output by the first amplifier and inputting the rectified level to the level comparing module;
the level comparison module is used for outputting a high level to the NAND gate through a second output end of the level comparison module when judging that the rectified level is greater than a preset upper limit level so as to enable the NAND gate to output a low level, and the low level enters a U/D pin of the digital adjustable resistor after passing through a second diode so as to enable the digital adjustable resistor to enter a resistance value down regulation mode; the level comparison module is further used for outputting a high level through a first output end of the level comparison module when judging that the rectified level is smaller than a preset lower limit, and the high level enters a U/D pin of the digital adjustable resistor after passing through a first diode so as to enable the digital adjustable resistor to enter a resistance value up-regulation mode;
the clock signal generating module is used for generating a clock signal so that the clock signal is input to the digital adjustable resistor through the output end of the clock signal generating module when the second input end of the clock signal generating module receives the high level output by the second output end of the level comparing module or when the first input end of the clock signal generating module receives the high level output by the first output end of the level comparing module;
the digital adjustable resistor is used for reducing the resistance value of the digital adjustable resistor when entering a resistance value down-regulation mode and receiving a clock signal output by the output end of the clock signal generation module so as to reduce the signal gain output by the gain regulation module; the digital adjustable resistor is also used for increasing the resistance value of the digital adjustable resistor when the digital adjustable resistor enters a resistance value up-regulation mode and receives a clock signal output by the output end of the clock signal generation module, so that the signal gain output by the gain adjustment module is increased.
Preferably, the first output end of the level comparison module, the first diode and the U/D pin of the digitally adjustable resistor are sequentially connected, and specifically include:
the first output end of the level comparison module is connected with the positive electrode of the first diode, and the negative electrode of the first diode is connected with the U/D pin of the digital adjustable resistor.
Preferably, the second output end of the level comparison module, the nand gate, the second diode and the U/D pin of the digitally adjustable resistor are sequentially connected, and specifically include:
the second output end of the level comparison module is respectively connected with the first input end of the NAND gate and the second input end of the NAND gate, the output end of the NAND gate is connected with the positive electrode of the second diode, and the negative electrode of the second diode is connected with the U/D pin of the digital adjustable resistor.
Preferably, the VSS pin of the digital tunable resistor is grounded, the VCC pin of the digital tunable resistor is connected to an external power supply, and the CS pin of the digital tunable resistor is grounded.
Preferably, the signal rectification module comprises a second resistor, a third resistor, a fourth resistor, a third diode, a fourth diode, a second capacitor and a second amplifier;
the first end of the second resistor is used as an input end of the signal rectifying module, the second end of the second resistor is respectively connected with the first end of the third resistor, the positive electrode of the third diode and the inverting input end of the second amplifier, and the non-inverting input end of the second amplifier is grounded;
the negative pole of third diode with the output of second amplifier is connected, the output of second amplifier still inserts the anodal of fourth diode, the negative pole of fourth diode with the second end of third resistance is connected, the negative pole of fourth diode still is connected respectively with the first port of second electric capacity and the first port of fourth resistance, the second port of second electric capacity and the second port of fourth resistance are all grounded, the first port of fourth resistance is as the output of signal rectification module.
Preferably, the level comparison module includes a first comparator, a second comparator, a fifth resistor, a sixth resistor and a seventh resistor,
the inverting input end of the first comparator and the non-inverting input end of the second comparator are both used as the input end of the level comparison module, the non-inverting input end of the first comparator is respectively connected with a first port of a fifth resistor, a first port of a seventh resistor and an external power supply, a second port of the seventh resistor is connected with the external power supply, the inverting input end of the second comparator is respectively connected with the second port of the fifth resistor, the first port of the sixth resistor and the external power supply, the second port of the sixth resistor is connected with the external power supply, and the output port of the first comparator and the output port of the second comparator are both used as the output port of the level comparison module.
Preferably, the clock signal generating module includes a fifth diode, a sixth diode, a first and gate, a second and gate, a timer chip, an eighth resistor, a ninth resistor, a tenth resistor, a third capacitor, a fourth capacitor, and a fifth capacitor;
the first end of the third capacitor is connected with the second end of the ninth resistor, the VCC pin of the timer chip and the REST pin of the timer chip, the second end of the third capacitor is grounded, the GND pin of the timer chip is grounded, the UC pin of the timer chip is connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second end of the fifth capacitor;
the OUT pin of the timer chip is connected with the first end of the eighth resistor, the second end of the eighth resistor is connected with the second input end of the first and gate and the first input end of the second and gate respectively, the first input end of the first and gate is used as the second input end of the clock signal generating module, the second input end of the second and gate is used as the first input end of the clock signal generating module, the output end of the first and gate is connected with the positive electrode of the sixth diode, the output end of the second and gate is connected with the positive electrode of the fifth diode, and the negative electrode of the sixth diode is connected with the negative electrode of the fifth diode to form the output end of the clock signal generating module.
Preferably, the method further comprises: a sixth capacitor;
and the output end of the first amplifier outputs the signal with the gain adjusted through a sixth capacitor.
The invention has the following beneficial effects:
the embodiment of the invention provides a signal gain adjusting circuit, which comprises a gain adjusting module, a signal rectifying module, a level comparing module, a NAND gate, a first diode, a second diode and a clock signal generating module; the gain adjustment module comprises a first capacitor, a first resistor, a first amplifier and a digital adjustable resistor; the method comprises the steps that a level signal of an external signal source enters a signal rectification module through a gain adjustment module, so that when the signal rectification module receives the signal level output by the gain adjustment module, the signal level is rectified, and the rectified level is input to a level comparison module; the level comparison module can detect the rectified level and judge whether the rectified level is larger than a preset upper limit voltage or smaller than the preset upper limit voltage, and when the rectified level is judged to be larger than the preset upper limit voltage, the second output end of the level comparison module outputs high level to the NAND gate so that the NAND gate outputs low level, and the low level enters the U/D pin of the digital adjustable resistor after passing through the second diode so that the digital adjustable resistor enters a resistance value down-regulation mode; when the rectified level is judged to be smaller than a preset lower limit level, a high level is output through a first output end of the level comparison module, and the high level enters a U/D pin of the digital adjustable resistor after passing through a first diode so that the digital adjustable resistor enters a resistance value up-regulation mode; the invention can detect the level of the signal through the level comparison module, and when the level of the signal is too large or too small, the resistance adjustment mode of the digital adjustable resistor is also changed automatically, and the digital adjustable resistor also changes the resistance value of the digital adjustable resistor through the clock signal generated by the clock signal generation module, namely, when the digital adjustable resistor enters the resistance value down adjustment mode and receives the clock signal output by the output end of the clock signal generation module, the resistance value of the digital adjustable resistor is reduced, so that the signal gain output by the gain adjustment module is reduced; when the resistance value up-regulating mode is entered and the clock signal output by the output end of the clock signal generating module is received, the resistance value of the digital adjustable resistor is increased, so that the signal gain output by the gain regulating module is increased, and the signal gain of the gain regulating module is automatically regulated. The invention only needs to automatically detect the signal level through the level comparison module and feed back the signal level to the digital adjustable resistor according to the detection result, so that the digital adjustable resistor can adjust the self resistance up or down so as to achieve the purpose of automatically adjusting the signal gain.
Drawings
Fig. 1 is a schematic circuit diagram of a signal gain adjusting circuit according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, a schematic circuit connection diagram of a signal gain adjusting circuit according to an embodiment of the present invention is shown,
the embodiment of the invention provides a signal gain adjusting circuit, which comprises a gain adjusting module, a signal rectifying module, a level comparing module, a NAND gate U6A, a first diode D1, a second diode D2 and a clock signal generating module;
the gain adjustment module comprises a first capacitor C1, a first resistor R1, a first amplifier U1A and a digital adjustable resistor;
in a preferred embodiment, the digitally tunable resistor is an X9C104 chip.
The first end of the first capacitor C1 is connected with an external signal source, the second end of the first capacitor C1 is connected with the first end of a first resistor R1, the second end of the first resistor R1 is respectively connected with the inverting input end of a first amplifier U1A and the VH pin of a digital adjustable resistor, the non-inverting input end of the first amplifier U1A is grounded, the output end of the first amplifier U1A is used for outputting a signal after gain adjustment, the output end of the first amplifier U1A is respectively connected with the VW pin of the digital adjustable resistor U4 and the input end of a signal rectifying module, the output end of the signal rectifying module is connected with the input end of a level comparison module, the first output end of the level comparison module, the U/D pin of the first diode D1 and the digital adjustable resistor are sequentially connected, the second output end of the level comparison module, the NAND gate U6A, the second diode D2 and the U/D pin of the digital adjustable resistor are sequentially connected, the first output end of the level comparison module is connected with the first clock generating module, the first clock output end of the level comparison module is connected with the first clock output end of the level comparison module, and the output end of the digital adjustable resistor is connected with the first clock module;
specifically, a first output end of the level comparison module is connected with an anode of the first diode D1, and a cathode of the first diode D1 is connected with a U/D pin of the digital adjustable resistor; the second output end of the level comparison module is respectively connected with the first input end of the NAND gate U6A and the second input end of the NAND gate U6A, the output end of the NAND gate U6A is connected with the positive electrode of the second diode D2, and the negative electrode of the second diode D2 is connected with the U/D pin of the digital adjustable resistor.
The signal rectifying module is used for rectifying the level when receiving the level output by the first amplifier U1A and inputting the rectified level to the level comparing module;
the level comparison module is used for outputting a high level to the NAND gate U6A through a second output end of the level comparison module when judging that the rectified level is greater than a preset upper limit level so as to enable the NAND gate U6A to output a low level, and the low level enters a U/D pin of the digital adjustable resistor after passing through a second diode D2 so as to enable the digital adjustable resistor to enter a resistance value down-regulation mode; the level comparison module is further used for outputting a high level through a first output end of the level comparison module when judging that the rectified level is smaller than a preset lower limit level, and the high level enters a U/D pin of the digital adjustable resistor after passing through a first diode D1 so as to enable the digital adjustable resistor to enter a resistance value up-regulation mode;
the clock signal generating module is used for generating a clock signal so that the clock signal is input to the digital adjustable resistor through the output end of the clock signal generating module when the second input end of the clock signal generating module receives the high level output by the second output end of the level comparing module or when the first input end of the clock signal generating module receives the high level output by the first output end of the level comparing module;
the digital adjustable resistor is used for reducing the resistance value of the digital adjustable resistor when entering a resistance value down-regulation mode and receiving a clock signal output by the output end of the clock signal generation module so as to reduce the signal gain output by the gain regulation module; the digital adjustable resistor is also used for increasing the resistance value of the digital adjustable resistor when the digital adjustable resistor enters a resistance value up-regulation mode and receives a clock signal output by the output end of the clock signal generation module, so that the signal gain output by the gain adjustment module is increased.
In a preferred embodiment, the VSS pin of the digital tunable resistor is grounded, the VCC pin of the digital tunable resistor is connected to an external power source, and the CS pin of the digital tunable resistor is grounded.
In a preferred embodiment, the signal rectification module includes a second resistor R2, a third resistor R3, a fourth resistor RR4, a third diode D3, a fourth diode D4, a second capacitor C2, and a second amplifier U1B;
the first end of the second resistor R2 is used as an input end of the signal rectification module, the second end of the second resistor R2 is respectively connected with the first end of the third resistor R3, the positive electrode of the third diode D3 and the inverting input end of the second amplifier U1B, and the non-inverting input end of the second amplifier U1B is grounded;
the negative pole of third diode D3 with the output of second amplifier U1B, the output of second amplifier U1B still inserts the positive pole of fourth diode D4, the negative pole of fourth diode D4 with the second end of third resistance R3 is connected, the negative pole of fourth diode D4 still is connected with the first port of second electric capacity C2 and the first port of fourth resistance R4 respectively, the second port of second electric capacity C2 and the second port of fourth resistance R4 are all grounded, the first port of fourth resistance R4 is as the output of signal rectification module.
In a preferred embodiment, the level comparison module includes a first comparator U5A, a second comparator U5B, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;
the inverting input end of the first comparator U5A and the non-inverting input end of the second comparator U5B are both used as the input end of the level comparison module, the non-inverting input end of the first comparator U5A is respectively connected with a first port of a fifth resistor R5, a first port of a seventh resistor R7 and an external power supply, a second port of the seventh resistor R7 is connected with the external power supply, the inverting input end of the second comparator U5B is respectively connected with a second port of the fifth resistor R5, a first port of a sixth resistor R6 and the external power supply, and a second port of the sixth resistor R6 is connected with the external power supply, and an output port of the first comparator U5A and an output port of the second comparator U5B are both used as the output ports of the level comparison module.
In a preferred embodiment, the clock signal generating module includes a fifth diode D5, a sixth diode D6, a first and gate U3A, a second and gate U3B, a timer chip U2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5;
in a preferred embodiment, the timer chip U2 is an EN555 chip for generating a clock signal;
the TH pin and the TR pin of the timer chip U2 are respectively connected to the first end of the fifth capacitor C5 and the first end of the tenth resistor R10, the second end of the tenth resistor R10 is respectively connected to the DI pin of the timer chip U2 and the first end of the ninth resistor R9, the second end of the ninth resistor R9 is connected to the VCC pin of the timer chip U2, the VCC pin of the timer chip U2 is also connected to an external power supply, the first end of the third capacitor C3 is respectively connected to the second end of the ninth resistor R9, the VCC pin of the timer chip U2 and the REST pin of the timer chip U2, the second end of the third capacitor C3 is grounded, the GND pin of the timer chip U2 is grounded, the UC pin of the timer chip U2 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is connected to the second end of the fifth capacitor C5;
the OUT pin of the timer chip U2 is connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is connected to the second input end of the first and gate U3A and the first input end of the second and gate U3B, the first input end of the first and gate U3A is used as the second input end of the clock signal generating module, the second input end of the second and gate U3B is used as the first input end of the clock signal generating module, the output end of the first and gate U3A is connected to the positive electrode of the sixth diode D6, the output end of the second and gate U3B is connected to the positive electrode of the D5 of the fifth diode, and the negative electrode of the sixth diode D6 is connected to the negative electrode of the fifth diode D5 to form the output end of the clock signal generating module.
In a preferred embodiment, the present invention further comprises: a sixth capacitance C6; the output end of the first amplifier U1A outputs the signal after gain adjustment through a sixth capacitor C6.
Specifically, the circuit implementation principle of the invention is as follows: the digital adjustable resistor is an X9C104 chip and is a 100-stage adjustable resistor, and the resistance value is divided into 100 stages. The resistance is adjustable by pin 1 (INC), and pin 2 (U/D). When pin 2 (U/D) is high, pin 1 (INC) is clocked, the internal resistance is increased by 1, and the resistance of the resistor is maximized for 100 clocks. Pin 1 (INC) is a clock when pin 2 (U/D) is low, the internal resistance is reduced by 1, and the resistance of the 100 clock resistor is minimized.
In a preferred embodiment, the gain adjustment module is an inverting amplifier formed by the first amplifier U1A and the first resistor R1 and the digitally adjustable resistor U4. And the inverting amplifier count formula: gain av=resistance value of digitally adjustable resistor U4/resistance value of first resistor R1.
The method comprises the steps that an external signal source outputs a signal to enter a gain adjusting circuit, the gain adjusting circuit inputs the level of the signal into a signal rectifying module through the output end of a first amplifier, and the signal rectifying module is used for rectifying the level and inputting a rectified level value (marked as VIN voltage) into a level comparing module when receiving the level output by the first amplifier U1A;
the level comparison module can detect the rectified level and judge whether the rectified level is larger than a preset upper limit voltage or smaller than the preset upper limit voltage;
specifically, as shown in fig. 1, the input signal level value is labeled as VIN voltage, the preset upper limit voltage is labeled as VREF1 level, and the preset lower limit voltage is labeled as VREF2 level;
the invention automatically adjusts the principle of the digital adjustable resistor when the input signal is overlarge: when the rectified level is judged to be greater than the preset upper limit level, that is, the voltage of the positive input end VIN is greater than the level of the preset upper limit voltage VREF1, the pin 7 (i.e., the output end) of the second comparator U5B outputs a high level, a 0 signal (low level) is output through the NAND gate U6A and then enters the U/D pin of the digital adjustable resistor through the second diode D2, so that the digital adjustable resistor U4 enters a resistance value down-regulating mode; at this time, the signal gain of the gain control circuit is reduced, and at this time, the output 0 signal (low level) of the pin 1 of the first comparator U5A has no influence on the U/D pin of the digital adjustable resistor U4, and the digital adjustable resistor U4 is still in a resistance value down-regulation mode;
because the first comparator U5A pin 1 outputs a 0 signal (low level), then the second and gate U3B is in an off state, then the clock signal generated by the clock signal cannot go from the second and gate U3B to the/INC pin of the digital adjustable resistor U4, but because the pin 7 of the second comparator U5B (i.e., the second output terminal of the level comparison module) outputs a high level, then the clock signal generated by the clock signal goes from the first and gate U3A to the/INC pin of the digital adjustable resistor U4 to make the internal resistance value of the digital adjustable resistor decrease by 1 one clock when the pin 2 (U/D) of the digital adjustable resistor U4 is low and the pin 1 (INC) to make the resistance value of the digital adjustable resistor decrease, thereby making the signal gain output by the gain adjustment module decrease.
The invention automatically adjusts the digital adjustable resistor when the input signal is too small, which comprises the following steps: when the rectified level is judged to be smaller than a preset lower limit level, namely the voltage of an inverted input end VIN is smaller than the level of a preset lower limit voltage VREF2, the pin 1 of the first comparator U5A outputs a high level, and a 1 signal (namely the high level) is output to the U/D pin of the digital adjustable resistor U4 through the first diode D1 so that the digital adjustable resistor enters a resistance value up-regulation mode; at this time, the signal gain of the gain control circuit is increased, and at this time, the output of a 0 signal (low level) by the pin 7 of the second comparator U5B has no influence on the U/D pin of the digital adjustable resistor U4, and the digital adjustable resistor U4 is still in a resistance value up-regulation mode;
because the first comparator U5B pin 7 outputs a 0 signal (low level), the first and gate U3A is in an off state, the clock signal generated by the clock signal cannot go from the first and gate U3A to the/INC pin of the digital adjustable resistor U4, but because the pin 1 of the first comparator U5A (i.e., the first output terminal of the level comparison module) outputs a high level, the clock signal generated by the clock signal goes from the second and gate U3B to the/INC pin of the digital adjustable resistor U4, so that the internal resistance value is increased by 1 to make the resistance value of the digital adjustable resistor U4 become larger when the pin 2 (U/D) of the digital adjustable resistor U4 is high and the pin 1 (INC) goes by one clock, thereby making the signal gain output by the gain adjustment module increase.
The invention can detect the level of the signal through the level comparison module, and when the level of the signal is too large or too small, the resistance adjustment mode of the digital adjustable resistor is also changed automatically, and the digital adjustable resistor also changes the resistance value of the digital adjustable resistor through the clock signal generated by the clock signal generation module.
When the digital adjustable resistor enters a resistance value down-regulation mode and receives a clock signal output by the output end of the clock signal generation module, the resistance value of the digital adjustable resistor is reduced, so that the signal gain output by the gain adjustment module is reduced; when the resistance value up-regulating mode is entered and the clock signal output by the output end of the clock signal generating module is received, the resistance value of the digital adjustable resistor is increased, so that the signal gain output by the gain regulating module is increased, and the signal gain of the gain regulating module is automatically regulated.
The invention only needs to automatically detect the signal level through the level comparison module and feed back the signal level to the digital adjustable resistor according to the detection result, so that the digital adjustable resistor can adjust the self resistance up or down so as to achieve the purpose of automatically adjusting the signal gain.
The invention does not need to adopt a singlechip or an ADC (digital to analog converter) to control the gain of the signal, but only needs to detect the signal level through the level comparison module and feed back the signal level to the digital resistor according to the detection result, thereby enabling the digital resistor to adjust the resistance value of the digital resistor up or down so as to achieve the purpose of adjusting the signal gain and reducing the cost of a control circuit of the signal gain.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (7)
1. The signal gain adjusting circuit is characterized by comprising a gain adjusting module, a signal rectifying module, a level comparing module, a NAND gate, a first diode, a second diode and a clock signal generating module;
the gain adjustment module comprises a first capacitor, a first resistor, a first amplifier and a digital adjustable resistor;
the first end of the first capacitor is connected with an external signal source, the second end of the first capacitor is connected with the first end of a first resistor, the second end of the first resistor is connected with the inverting input end of a first amplifier and the VH pin of a digital adjustable resistor respectively, the non-inverting input end of the first amplifier is grounded, the output end of the first amplifier is used for outputting a signal after gain adjustment, the output end of the first amplifier is connected with the VW pin of the digital adjustable resistor and the input end of a signal rectifying module respectively, the output end of the signal rectifying module is connected with the input end of a level comparison module, the first output end of the level comparison module, a first diode and the U/D pin of the digital adjustable resistor are sequentially connected, the second output end of the level comparison module, a NAND gate, a second diode and the U/D pin of the digital adjustable resistor are sequentially connected, the first input end of a clock signal generating module is connected with the first output end of the level comparison module, the output end of the clock signal generating module is connected with the output end of the clock signal generating module;
the signal rectifying module comprises a second resistor, a third resistor, a fourth resistor, a third diode, a fourth diode, a second capacitor and a second amplifier; the first end of the second resistor is used as an input end of the signal rectifying module, the second end of the second resistor is respectively connected with the first end of the third resistor, the positive electrode of the third diode and the inverting input end of the second amplifier, and the non-inverting input end of the second amplifier is grounded; the negative electrode of the third diode is connected with the output end of the second amplifier, the output end of the second amplifier is also connected with the positive electrode of the fourth diode, the negative electrode of the fourth diode is connected with the second end of the third resistor, the negative electrode of the fourth diode is also respectively connected with the first port of the second capacitor and the first port of the fourth resistor, the second port of the second capacitor and the second port of the fourth resistor are both grounded, and the first port of the fourth resistor is used as the output end of the signal rectifying module;
the signal rectifying module is used for rectifying the level when receiving the level output by the first amplifier and inputting the rectified level to the level comparing module;
the level comparison module is used for outputting a high level to the NAND gate through a second output end of the level comparison module when judging that the rectified level is greater than a preset upper limit level so as to enable the NAND gate to output a low level, and the low level enters a U/D pin of the digital adjustable resistor after passing through a second diode so as to enable the digital adjustable resistor to enter a resistance value down regulation mode; the level comparison module is further used for outputting a high level through a first output end of the level comparison module when judging that the rectified level is smaller than a preset lower limit, and the high level enters a U/D pin of the digital adjustable resistor after passing through a first diode so as to enable the digital adjustable resistor to enter a resistance value up-regulation mode;
the clock signal generating module is used for generating a clock signal so that the clock signal is input to the digital adjustable resistor through the output end of the clock signal generating module when the second input end of the clock signal generating module receives the high level output by the second output end of the level comparing module or when the first input end of the clock signal generating module receives the high level output by the first output end of the level comparing module;
the digital adjustable resistor is used for reducing the resistance value of the digital adjustable resistor when entering a resistance value down-regulation mode and receiving a clock signal output by the output end of the clock signal generation module so as to reduce the signal gain output by the gain regulation module; the digital adjustable resistor is also used for increasing the resistance value of the digital adjustable resistor when the digital adjustable resistor enters a resistance value up-regulation mode and receives a clock signal output by the output end of the clock signal generation module, so that the signal gain output by the gain adjustment module is increased.
2. The signal gain adjustment circuit of claim 1, wherein the first output terminal of the level comparison module, the first diode and the U/D pin of the digitally adjustable resistor are connected in sequence, specifically comprising:
the first output end of the level comparison module is connected with the positive electrode of the first diode, and the negative electrode of the first diode is connected with the U/D pin of the digital adjustable resistor.
3. The signal gain adjustment circuit of claim 1, wherein the second output terminal of the level comparison module, the nand gate, the second diode and the U/D pin of the digitally adjustable resistor are sequentially connected, specifically comprising:
the second output end of the level comparison module is respectively connected with the first input end of the NAND gate and the second input end of the NAND gate, the output end of the NAND gate is connected with the positive electrode of the second diode, and the negative electrode of the second diode is connected with the U/D pin of the digital adjustable resistor.
4. The signal gain adjustment circuit of claim 1, wherein the VSS pin of the digital adjustable resistor is grounded, the VCC pin of the digital adjustable resistor is connected to an external power source, and the CS pin of the digital adjustable resistor is grounded.
5. A signal gain adjustment circuit according to claim 1, wherein the level comparison module comprises a first comparator, a second comparator, a fifth resistor, a sixth resistor, and a seventh resistor,
the inverting input end of the first comparator and the non-inverting input end of the second comparator are both used as the input end of the level comparison module, the non-inverting input end of the first comparator is respectively connected with a first port of a fifth resistor, a first port of a seventh resistor and an external power supply, a second port of the seventh resistor is connected with the external power supply, the inverting input end of the second comparator is respectively connected with the second port of the fifth resistor, the first port of the sixth resistor and the external power supply, the second port of the sixth resistor is connected with the external power supply, and the output port of the first comparator and the output port of the second comparator are both used as the output port of the level comparison module.
6. The signal gain adjustment circuit of claim 1, wherein the clock signal generation module comprises a fifth diode, a sixth diode, a first and gate, a second and gate, a timer chip, an eighth resistor, a ninth resistor, a tenth resistor, a third capacitor, a fourth capacitor, and a fifth capacitor;
the first end of the third capacitor is connected with the second end of the ninth resistor, the VCC pin of the timer chip and the REST pin of the timer chip, the second end of the third capacitor is grounded, the GND pin of the timer chip is grounded, the UC pin of the timer chip is connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second end of the fifth capacitor;
the OUT pin of the timer chip is connected with the first end of the eighth resistor, the second end of the eighth resistor is connected with the second input end of the first and gate and the first input end of the second and gate respectively, the first input end of the first and gate is used as the second input end of the clock signal generating module, the second input end of the second and gate is used as the first input end of the clock signal generating module, the output end of the first and gate is connected with the positive electrode of the sixth diode, the output end of the second and gate is connected with the positive electrode of the fifth diode, and the negative electrode of the sixth diode is connected with the negative electrode of the fifth diode to form the output end of the clock signal generating module.
7. The signal gain adjustment circuit of claim 1, further comprising: a sixth capacitor;
and the output end of the first amplifier outputs the signal with the gain adjusted through a sixth capacitor.
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