CN116320806A - High-speed column readout circuit and method for CMOS image sensor - Google Patents
High-speed column readout circuit and method for CMOS image sensor Download PDFInfo
- Publication number
- CN116320806A CN116320806A CN202211597226.5A CN202211597226A CN116320806A CN 116320806 A CN116320806 A CN 116320806A CN 202211597226 A CN202211597226 A CN 202211597226A CN 116320806 A CN116320806 A CN 116320806A
- Authority
- CN
- China
- Prior art keywords
- switch
- circuit
- switches
- capacitor
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The invention relates to a column readout circuit of a CMOS image sensor, in particular to a high-speed column readout circuit for the CMOS image sensor, which solves the technical problems that the signal readout speed of the existing column readout circuit is low, double-end voltage signal output cannot be carried out, and the output range cannot be externally adjusted. The invention comprises m branches, a holding and amplifying circuit and a multiplexer, wherein the multiplexer has a two-stage amplifying function, and the time-sharing reading of m branch sampling signals is realized by using the multiplexer. The branch circuit comprises a column buffer circuit and a related double sampling circuit, the column buffer circuit adopts fixed capacitors, and different amplification factors are obtained by changing the proportional relation of the two fixed capacitors so as to realize first-stage amplification; the related double sampling circuit and the holding and amplifying circuit adopt programmable capacitors, and a gain amplifier is formed by combining the programmable capacitors to realize second-stage amplification. The proportional relation of the programmable capacitors is changed by external control, so that the amplification factor of the column readout circuit is changed accordingly, and the output range is flexibly adjusted.
Description
Technical Field
The present invention relates to a column readout circuit of a CMOS image sensor, and more particularly, to a high-speed column readout circuit and method for a CMOS image sensor.
Background
CMOS image sensors are widely used in smart phones, industry, medical and scientific research fields. In a CMOS image sensor, a readout circuit is located between a pixel array and an analog-to-digital converter, and plays an important role in suppressing noise and amplifying signals. Readout circuits can generally be divided into three categories: pixel serial readout, column parallel readout, and pixel parallel readout circuits. The column parallel readout circuit is the most widely used readout circuit structure in CMOS image sensors because it can achieve a good tradeoff in terms of performance such as speed, area, power consumption, etc. of CMOS image sensors.
With the continuous development of CMOS image sensors, higher requirements are also put on the performance of column readout circuits: firstly, in order to increase the frame frequency of the CMOS image sensor, a column readout circuit is required to have a higher signal readout speed; secondly, the column readout circuit has a correlated double sampling function so as to eliminate the fixed mode noise of the pixel circuit; thirdly, the column readout circuit has a signal amplifying function so as to expand the dynamic range of the CMOS image sensor; fourth, because of the limited area within the CMOS image sensor chip, column readout circuits are required to achieve as high accuracy and speed as possible within a limited space.
Conventional column readout circuits are typically balanced and comprehensively optimized among a plurality of performance parameters, but often suffer from the following problems or requirements:
(1) The source follower in the pixel has weaker driving capability generally, and the signal reading speed is slower due to the fact that the sampling capacitor is directly connected;
(2) Because the output of the column readout circuit is directly connected with the input of the analog-to-digital converter, the current analog-to-digital converter design mostly adopts analog differential input to inhibit circuit noise, so the column readout circuit is required to be capable of converting a single-ended voltage signal output by a pixel into a double-ended analog differential voltage signal;
(3) To ensure that the analog to digital converter is capable of full scale output, the output range of the column readout circuit is matched to the input range of the analog to digital converter, and the design deviation of the circuit often causes that the requirement is difficult to achieve, so that the output range of the column readout circuit needs to be externally adjustable.
Disclosure of Invention
The invention aims to solve the technical problems that the signal reading speed of the existing column reading circuit is low, the output of a double-end analog differential voltage signal cannot be carried out, and the output range cannot be externally adjusted, and provides a high-speed column reading circuit and a high-speed column reading method for a CMOS image sensor.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a high-speed column readout circuit for a CMOS image sensor, characterized by: the sampling circuit comprises m branches used for buffering sampling, a holding and amplifying circuit and a multiplexer, wherein m is an integer greater than or equal to 1;
the branch circuit comprises a column buffer circuit and a related double sampling circuit;
the input ends of the m column buffer circuits are connected with the output ends of the pixel circuits and are used for buffering and amplifying photogenerated signals and reset signals of the pixel circuits, so that the reading speed of the pixel signals is improved; the output ends of the m column buffer circuits are respectively connected with the data input ends of m related double sampling circuits;
the m correlated double sampling circuits sample the photo-generated signals and the reset signals output by the m column buffer circuits respectively, and the subtraction of the photo-generated signals and the reset signals is realized through charge sharing so as to eliminate the fixed mode noise of the pixel circuit; the m correlated double sampling circuits adopt gain-adjustable amplifiers, and the output ends of the amplifiers are connected with the input ends of the holding and amplifying circuits;
the output end of the multiplexer is respectively connected with the control input ends of the m related double sampling circuits and is used for reading signals of the related double sampling circuits in the m branches to the holding and amplifying circuits in a time-sharing manner;
the holding and amplifying circuit is used for holding and amplifying signals sampled and output by m relevant double circuits, and adopts an amplifier with adjustable gain to convert single-ended unipolar voltage signals into double-ended bipolar voltage signals and output the double-ended bipolar voltage signals.
Further, the column buffer circuit includes a single-ended amplifier AMP, three switches S1 to S3, and two capacitors C1 and C2;
one ends of the m switches S1 are connected with the output end of the pixel circuit, and the other ends of the switches S1 are respectively connected with the left polar plate of the capacitor C1 and one end of the switch S2;
the right polar plate of the capacitor C1 is connected with the input end of the single-ended amplifier AMP, the left polar plate of the capacitor C2 and one end of the switch S3;
the output end of the single-ended amplifier AMP is connected with the right polar plate of the capacitor C2, the other end of the switch S3 and the other end of the switch S2; the output of the single-ended amplifier AMP is connected to the input of the associated double sampling circuit of the corresponding branch.
Further, the correlated double sampling circuit comprises seven switches S4-S10 and two adjustable capacitors C3 and C4;
one end of the switch S4 and one end of the switch S5 are connected with the output end of the single-ended amplifier AMP of the column buffer circuit in the corresponding branch;
the other end of the switch S4 is connected with the left polar plate of the adjustable capacitor C3 at one end of the switch S8; the right polar plate of the adjustable capacitor C3 is connected with one end of a switch S6 and one end of a switch S9, and the other end of the switch S6 is connected with an external input reference voltage signal VREF;
the other end of the switch S5 is connected with the left polar plate of the adjustable capacitor C4; the right polar plate of the adjustable capacitor C4 is connected with one end of the switch S7 and one end of the switch S10, and the other end of the switch S7 is grounded;
the other ends of the m switches S9 are connected with one input end of the holding and amplifying circuit, and the other ends of the m switches S10 are connected with the other input end of the holding and amplifying circuit;
the multiplexer includes 3 selectors having m outputs;
the m outputs of the 3 selectors are respectively connected with the switches S8, S9 and S10 of the relevant double sampling circuits in the m branches, and are used for respectively controlling the on and off of the switches S8, S9 and S10 in the m relevant double sampling circuits, and the signals of the relevant double sampling circuits in the m branches are read out to the holding and amplifying circuit in a time sharing mode.
Further, the holding and amplifying circuit comprises a fully differential operational amplifier OP-AMP, seven switches S11-S17 and two adjustable capacitors C5 and C6;
one end of the switch S11 is connected with the other ends of the m switches S9 and is simultaneously connected with the positive input end of the fully differential operational amplifier OP-AMP and the left polar plate of the adjustable capacitor C5;
one end of the switch S12 is connected with the other ends of the m switches S10 and is simultaneously connected with the inverting input end of the fully differential operational amplifier OP-AMP and the left polar plate of the adjustable capacitor C6;
the reverse phase output end VOUTN of the fully differential operational amplifier OP-AMP is connected with one end of a switch S15 and one end of a switch S17, the normal phase output end VOUTP is connected with one end of a switch S16 and the other end of the switch S17, an input common-mode voltage signal VCMI is connected with the other end of a switch S11 and the other end of a switch S12, and an output common-mode voltage signal VCMO is connected with one end of a switch S13 and one end of a switch S14;
the right polar plate of the adjustable capacitor C5 is connected with the other end of the switch S15 and the other end of the switch S13, and the right polar plate of the adjustable capacitor C6 is connected with the other end of the switch S16 and the other end of the switch S14;
the fully differential operational amplifier OP-AMP has a non-inverting output VOUTP and an inverting output VOUTN for outputting bipolar voltage signals.
Further, the capacitor C3, the capacitor C4, the capacitor C5 and the capacitor C6 are programmable capacitors.
Further, the capacitance value of the capacitor C3 is equal to the capacitance value of the capacitor C4;
the capacitance value of the capacitor C5 is equal to the capacitance value of the capacitor C6.
Further, the external input reference voltage signal VREF is adjustable.
Further, the operation timings of the switches S1 to S17 are as follows:
time t 0: closing the switches S2 and S3 of all branches, turning off the other switches, and resetting the column buffer circuit;
time t 1: closing the switches S1, S4 and S6 of all branches, and turning off the other switches to sample the pixel photogenerated signals;
time t 2: closing the switches S2 and S3 of all branches, turning off the other switches, and resetting the column buffer circuit;
time t 3: closing the switches S1, S5 and S7 of all branches, turning off the other switches, and sampling pixel reset signals;
time t 4-1: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-1: the switch S8, the switch S9, the switch S10, the switch S15 and the switch S16 of the branch circuit 1 are closed, and the rest switches are turned off to read sampling signals;
time t 4-2: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-2: the switch S8, the switch S9, the switch S10, the switch S15 and the switch S16 of the branch circuit 2 are closed, and the rest switches are turned off to read sampling signals;
…
time t 4-m: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-m: the switches S8, S9, S10, S15 and S16 of the branch m are closed, and the rest switches are turned off to read the sampling signals.
The high-speed column readout method for the CMOS image sensor is based on the high-speed column readout circuit for the CMOS image sensor, and is characterized by comprising the following steps of:
step 1, adjusting the states of m column buffer circuits, and resetting the states;
step 3, resetting floating diffusion point capacitors CFD of the pixel circuits, adjusting states of m column buffer circuits, and resetting the m column buffer circuits again;
step 4, adjusting the states of m column buffer circuits to be in an amplified state, and sampling a reset signal Vrst of a pixel circuit;
step 5, adjusting the state of the holding and amplifying circuit, and resetting the state;
step 6, selecting the branch 1 through a multiplexer, adjusting the state of the related double sampling circuit of the branch, and adjusting the state of the holding and amplifying circuit to finish the reading of the photogenerated signal and the reset signal of the branch 1;
and 7, resetting the holding and amplifying circuit, selecting the next branch through the multiplexer, and returning to the step 6 until the reading of the photo-generated signals and the reset signals of the m branches is completed, thereby realizing one-time column reading of the sampling signals of the CMOS image sensor.
Compared with the prior art, the invention has the following beneficial technical effects:
1. the invention solves the problem of weak driving capability of the source follower of the pixel circuit by adding the column buffer circuit module between the pixel circuit and the related double sampling circuit, thereby further improving the signal reading speed and being applicable to a high-frame-frequency CMOS image sensor;
2. the invention adopts the holding and amplifying circuit to realize the output of the double-end bipolar voltage signal;
3. the related double sampling circuits and the holding and amplifying circuits are combined by adopting the gain-adjustable amplifier, and the external adjustable output voltage range of the column readout circuit can be realized by adjusting the amplification factor;
4. the number ratio of the column buffer circuit, the related double sampling circuit and the holding and amplifying circuit is m:1, wherein m is more than or equal to 1, the column buffer circuit, the related double sampling circuit and the holding and amplifying circuit can be applicable to analog-digital converter circuits with different input ranges and different sizes, and the application flexibility of a column readout circuit is improved;
5. the related double sampling circuit and the holding and amplifying circuit can be matched to realize the programmable gain amplifying function of reading out the voltage signal, and compared with the traditional independent and separated design of the related double sampling circuit and the programmable gain amplifying circuit, the related double sampling circuit and the holding and amplifying circuit can reduce at least two capacitors, thereby simplifying the area of a column reading circuit;
6. the external input reference voltage signal VREF in the invention can be adjusted, and the capacitance values of the adjustable capacitors C3, C4, C5 and C6 are matched and adjusted, so that the adjustment range of the output voltage of the column readout circuit is further increased.
Drawings
FIG. 1 is a schematic diagram of a high-speed column readout circuit for a CMOS image sensor according to the present invention;
FIG. 2 is a schematic diagram of the operation timing of a high-speed column readout circuit for a CMOS image sensor according to the present invention.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a high speed column readout circuit for a CMOS image sensor according to the present invention will be described in further detail with reference to the drawings and detailed description.
A high-speed column readout circuit for a CMOS image sensor, as shown in FIG. 1, includes m branches for buffering samples, a hold and amplify circuit, and a multiplexer, m being an integer greater than or equal to 1, the branches including a column buffer circuit and an associated double sampling circuit. The value of m can be adjusted according to the frame frequency requirement of the CMOS image sensor and the dimension parameter of the analog-to-digital converter.
The input ends of the m column buffer circuits are connected with the output ends of the pixel circuits, and are used for buffering and amplifying photo-generated signals and reset signals of the pixel circuits and improving the reading speed of the pixel signals, and the m column buffer circuits comprise a single-ended amplifier AMP, three switches S1-S3 and two fixed capacitors C1 and C2; one ends of the m switches S1 are connected with the output end of the pixel circuit, and the other ends of the switches S1 are respectively connected with the left polar plate of the fixed capacitor C1 and one end of the switch S2; the right polar plate of the fixed capacitor C1 is connected with the input end of the single-ended amplifier AMP, the left polar plate of the fixed capacitor C2 and one end of the switch S3; the other end of the switch S2, the output end of the single-ended amplifier AMP, and the right plate of the fixed capacitor C2 are connected to the other end of the switch S3. The column buffer circuit has two working states, S2 and S3 are closed, the circuit is in a reset state under the condition that S1 is closed, S2 and S3 are closed, and the circuit is in an amplifying state under the condition that S1 is closed.
The m correlated double sampling circuits sample the photo-generated signals and the reset signals output by the m column buffer circuits respectively, and the photo-generated signals and the reset signals are subtracted by charge sharing to eliminate the fixed mode noise of the pixel circuit, and the pixel circuit comprises seven switches S4-S10 and two programmable capacitors C3 and C4. The output ends of the m single-ended amplifiers AMP are connected with one ends of m switches S4 and one ends of m switches S5; the other end of the switch S4 is connected with the left polar plate of the adjustable capacitor C3 at one end of the switch S8; the right polar plate of the adjustable capacitor C3 is connected with one end of a switch S6 and one end of a switch S9, and the other end of the switch S6 is connected with an external input reference voltage signal VREF; the other end of the switch S5 is connected with the left polar plate of the adjustable capacitor C4; the right polar plate of the adjustable capacitor C4 is connected with one end of the switch S7 and one end of the switch S10, and the other end of the switch S7 is grounded.
The multiplexer comprises 3 multiplexers with m outputs, and the m outputs of the 3 multiplexers are respectively connected with the switches S8, S9 and S10 of the relevant double sampling circuits in the m branches, and are used for respectively controlling the on and off of the switches S8, S9 and S10 in the m relevant double sampling circuits to read out the signals of the relevant double sampling circuits in the m branches to the holding and amplifying circuits in a time sharing mode.
The holding and amplifying circuit is used for holding and amplifying signals output by m correlated double circuit sampling, adopts an amplifier with adjustable gain, converts a single-ended unipolar voltage signal into a double-ended bipolar voltage signal and outputs the double-ended bipolar voltage signal, and comprises a fully differential operational amplifier OP-AMP, seven switches S11-S17 and two programmable capacitors C5 and C6. The positive input end of the fully differential operational amplifier OP-AMP is connected with one end of a switch S11, the other ends of m switches S9 in the related double sampling circuits and the left polar plate of a programmable capacitor C5, the negative input end is connected with one end of a switch S12 and the other ends of m switches S10 in the related double sampling circuits and the left polar plate of a programmable capacitor C6, the negative output end VOUTN is connected with one end of a switch S15 and one end of a switch S17, the positive output end VOUTP is connected with one end of a switch S16 and the other end of a switch S17, an input common-mode voltage signal VCMI is connected with the other ends of the switch S11 and the switch S12, and an output common-mode voltage signal VCMO is connected with one end of a switch S13 and one end of a switch S14; the right pole plate of the programmable capacitor C5 is connected with the other end of the switch S15 and the other end of the switch S13, and the right pole plate of the programmable capacitor C6 is connected with the other end of the switch S16 and the other end of the switch S14.
The high-speed column readout circuit provided by the invention has a two-stage amplification function, wherein one stage is the amplification function of the column buffer circuit, different amplification factors can be obtained by changing the proportional relation between the fixed capacitor C2 and the fixed capacitor C1, and the amplification factors cannot be changed externally once the amplification factors are designed; the related double sampling circuit and the holding and amplifying circuit form a programmable gain amplifier, the second-stage amplification of the column readout circuit is realized, the proportional relation between the programmable capacitor C5 and the programmable capacitor C6 and the proportional relation between the programmable capacitor C3 and the programmable capacitor C4 can be changed through external control, and therefore the amplification factor of the column readout circuit can be changed accordingly. The external input reference voltage VREF can change the output range of the column readout circuit, and can flexibly adjust the output range of the column readout circuit according to the input signal range requirement of the analog-to-digital converter in cooperation with the programmable gain amplification functions of the related double sampling circuit and the holding and amplifying circuit.
As shown in fig. 2, when the high-speed column read circuit has a plurality of column buffer circuits and a correlated double sampling circuit, the operation timings of the switches S1 to S17 are as follows:
time t 0: closing the switches S2 and S3 of all branches, turning off the other switches, and resetting the column buffer circuit;
time t 1: closing the switches S1, S4 and S6 of all branches, and turning off the other switches to sample the pixel photogenerated signals;
time t 2: closing the switches S2 and S3 of all branches, turning off the other switches, and resetting the column buffer circuit;
time t 3: closing the switches S1, S5 and S7 of all branches, turning off the other switches, and sampling pixel reset signals;
time t 4-1: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-1: the switch S8, the switch S9, the switch S10, the switch S15 and the switch S16 of the branch circuit 1 are closed, and the rest switches are turned off to read sampling signals;
time t 4-2: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-2: the switch S8, the switch S9, the switch S10, the switch S15 and the switch S16 of the branch circuit 2 are closed, and the rest switches are turned off to read sampling signals;
…
time t 4-m: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-m: the switches S8, S9, S10, S15 and S16 of the branch m are closed, and the rest switches are turned off to read the sampling signals.
The working principle is as follows:
after exposure, the pixel circuit transfers photo-generated charges to a floating diffusion point capacitor CFD, and before the CFD voltage signal is read, the column buffer circuit is reset, namely, switches S2 and S3 are simultaneously closed at a time t0, the rest switches are turned off, the column buffer circuit is in a reset state, at the moment, the input end and the output end of the single-ended amplifier AMP are short-circuited, and the input voltage and the output voltage of the single-ended amplifier AMP are equal to the common-mode voltage Vo of the single-ended amplifier AMP.
At time t1, a ROW selection transistor row_sel in the pixel circuit is turned on, meanwhile, switches S1, S4 and S6 are turned on, switches S2 and S3 are turned off, a right plate of a capacitor C3 is connected with an external input reference voltage VREF, a pixel signal Vsig is sampled onto a left plate of the capacitor C3, and a left plate voltage VC3L of the capacitor C3 is calculated by the following formula:
VC3L＝Vo-(Vsig-Vo)*C2/C1
vsig is a pixel signal, C1 is a capacitance value of the capacitor C1, and C2 is a capacitance value of the capacitor C2.
At time t2, the floating diffusion capacitor CFD of the pixel circuit is reset, meanwhile, the switches S2 and S3 are closed, the rest of the switches are turned off, the column buffer circuit is reset again, and the voltages of the input end and the output end of the single-ended amplifier AMP are Vo.
After the reset of the floating diffusion point capacitor CFD and the column buffer circuit is completed, at the time t3, the switches S1, S5 and S7 are closed, the switches S2 and S3 are turned off, the right plate of the capacitor C4 is grounded, the reset signal Vrst of the floating diffusion point capacitor is sampled onto the left plate of the capacitor C4, and the left plate voltage VC4L of the capacitor C4 is calculated by the following formula:
VC4L＝Vo-(Vrst-Vo)*C2/C1。
the sampling of the pixel signal and the reset signal is completed through the above operations. And then, the pixel signals obtained by sampling and the reset signals are subjected to difference, amplified and converted into double-end differential signals to be output.
For the case that the number proportion relation of the column buffer circuit, the related double sampling circuit and the holding and amplifying circuit is m:m:1, the sampling signals of m branches are respectively output to the holding and amplifying circuit through a multiplexer.
For the 1 st branch, at time t4_1, the switches S11, S12, S13, S14 and S17 of the holding and amplifying circuit are closed, and the rest switches are turned off, so that the left electrode plates of the capacitors C5 and C6 are connected with an input common-mode voltage signal VCMI of the fully differential operational amplifier OP-AMP, and the right electrode plates of the capacitors C5 and C6 are connected with an output common-mode voltage signal VCMO of the fully differential operational amplifier OP-AMP;
at time t5_1, switches S8, S9 and S10 of branch 1 and S15 and S16 of the hold and amplification circuit are closed, the remaining switches are turned off, the left plates of capacitors C3 and C4 are in charge sharing due to short circuit, the right plates of capacitors C3 and C4 are respectively connected to the positive input terminal and the negative input terminal of the fully differential operational amplifier OP-AMP, and ideally the voltages of the right plates of capacitors C3 and C4 are equal to the voltages of the input common mode voltage signal VCMI of the fully differential operational amplifier OP-AMP, so that the voltage signal changes on the left plates of capacitors C3 and C4 are transferred to the right plates of capacitors C5 and C6, and the negative output terminal and the positive output terminal of the fully differential operational amplifier OP-AMP. In general, the capacitance values c3=c4 and c5=c6 are set, and at this time, the differential relationship of the output voltages is:
wherein, VOUTP is the positive phase output voltage, VOUTN is the negative phase output voltage, VC4L is the left plate voltage of the capacitor C4, VC3L is the left plate voltage of the capacitor C3, VREF is the external input reference voltage, vsig is the pixel signal, vrst is the floating diffusion point capacitor reset signal, and C1, C2, C3, C5 are the capacitance values of the capacitors C1, C2, C3, C5, respectively.
As can be seen from the above equation, the read range of the column read circuit can be controlled by VREF, C3/C5, C2/C1, wherein VREF and C3/C5 can be adjusted by external inputs, so that the output range of the high-speed column read circuit of the invention can be flexibly adjusted.
After the reading of the sampling signals of the branch 1 is completed, and so on, the reading of the sampling signals of m branches is completed one by one.
The present embodiment also provides a high-speed column readout method for a CMOS image sensor, based on the high-speed column readout circuit for a CMOS image sensor, including the steps of:
step 1, simultaneously closing switches S2 and S3, turning off the other switches, enabling the input end and the output end of the single-ended amplifier AMP to be short-circuited, enabling the input voltage and the output voltage to be equal to the common mode voltage Vo of the single-ended amplifier AMP, and resetting the column buffer circuit;
step 3, resetting the floating diffusion point capacitor CFD of the pixel circuit, closing the switches S2 and S3, turning off the rest switches, and resetting the column buffer circuit again;
step 4, the switches S1, S5 and S7 are closed, the switches S2 and S3 are turned off, and the right electrode plate of the capacitor C4 is grounded, so that the column buffer circuit is in an amplifying state, and a reset signal Vrst of the pixel circuit is sampled to the left electrode plate of the adjustable capacitor C4;
step 5, the switches S11, S12, S13, S14 and S17 of the holding and amplifying circuit are closed, the other switches are turned off, the left electrode plate of the adjustable capacitor C5 and the left electrode plate of the adjustable capacitor C6 are connected with an input common-mode voltage signal VCMI of the fully differential operational amplifier OP-AMP, the right electrode plate of the adjustable capacitor C5 and the right electrode plate of the adjustable capacitor C6 are connected with an output common-mode voltage signal VCMO of the fully differential operational amplifier OP-AMP, and the holding and amplifying circuit is reset;
step 6, selecting a branch 1 through a multiplexer, closing switches S8, S9 and S10 of the branch 1 and switches S15 and S16 of a holding and amplifying circuit, turning off the other switches, realizing charge sharing due to short circuit of a left pole plate of an adjustable capacitor C3 and a left pole plate of an adjustable capacitor C4, respectively connecting a positive input end VOUTP and an opposite input end VOUTN of a fully differential operational amplifier OP-AMP with a right pole plate of the adjustable capacitor C3 and a right pole plate of the adjustable capacitor C4, and transferring a photo-generated signal Vsig and a reset signal Vrst on the left pole plate of the adjustable capacitor C3 to the right pole plate of the adjustable capacitor C5 and the right pole plate of the adjustable capacitor C6 as well as an opposite output end VOUTN and a positive output end VOUTP of the fully differential operational amplifier OP-AMP to finish reading photo-generated signals and reset signals of the branch 1;
and 7, resetting the holding and amplifying circuit, selecting the next branch through the multiplexer, and returning to the step 6 until the reading of the photo-generated signals and the reset signals of the m branches is completed, thereby realizing one-time column reading of the sampling signals of the CMOS image sensor.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (9)
1. A high speed column readout circuit for a CMOS image sensor, characterized by: the sampling circuit comprises m branches used for buffering sampling, a holding and amplifying circuit and a multiplexer, wherein m is an integer greater than or equal to 1;
the branch circuit comprises a column buffer circuit and a related double sampling circuit;
the input ends of the m column buffer circuits are connected with the output ends of the pixel circuits and are used for buffering and amplifying photogenerated signals and reset signals of the pixel circuits, so that the reading speed of the pixel signals is improved; the output ends of the m column buffer circuits are respectively connected with the data input ends of m related double sampling circuits;
the m correlated double sampling circuits sample the photo-generated signals and the reset signals output by the m column buffer circuits respectively, and the subtraction of the photo-generated signals and the reset signals is realized through charge sharing so as to eliminate the fixed mode noise of the pixel circuit; the m correlated double sampling circuits adopt gain-adjustable amplifiers, and the output ends of the amplifiers are connected with the input ends of the holding and amplifying circuits;
the output end of the multiplexer is respectively connected with the control input ends of the m correlated double sampling circuits and is used for controlling the correlated double sampling circuits in the m branches and reading out sampled signals to the holding and amplifying circuits in a time-sharing way;
the holding and amplifying circuit is used for holding and amplifying signals sampled and output by m relevant double circuits, and adopts an amplifier with adjustable gain to convert single-ended unipolar voltage signals into double-ended bipolar voltage signals and output the double-ended bipolar voltage signals.
2. The high-speed column readout circuit for a CMOS image sensor according to claim 1, wherein:
the column buffer circuit comprises a single-ended amplifier AMP, three switches S1-S3 and two capacitors C1 and C2;
one ends of the m switches S1 are connected with the output end of the pixel circuit, and the other ends of the switches S1 are respectively connected with the left polar plate of the capacitor C1 and one end of the switch S2;
the right polar plate of the capacitor C1 is connected with the input end of the single-ended amplifier AMP, the left polar plate of the capacitor C2 and one end of the switch S3;
the output end of the single-ended amplifier AMP is connected with the right polar plate of the capacitor C2, the other end of the switch S3 and the other end of the switch S2; the output of the single-ended amplifier AMP is connected to the input of the associated double sampling circuit of the corresponding branch.
3. The high-speed column readout circuit for a CMOS image sensor according to claim 2, wherein:
the correlated double sampling circuit comprises seven switches S4-S10 and two adjustable capacitors C3 and C4;
one end of the switch S4 and one end of the switch S5 are connected with the output end of the single-ended amplifier AMP of the column buffer circuit in the corresponding branch;
the other end of the switch S4 is connected with the left polar plate of the adjustable capacitor C3 at one end of the switch S8; the right polar plate of the adjustable capacitor C3 is connected with one end of a switch S6 and one end of a switch S9, and the other end of the switch S6 is connected with an external input reference voltage signal VREF;
the other end of the switch S5 is connected with the left polar plate of the adjustable capacitor C4; the right polar plate of the adjustable capacitor C4 is connected with one end of the switch S7 and one end of the switch S10, and the other end of the switch S7 is grounded;
the other ends of the m switches S9 are connected with one input end of the holding and amplifying circuit, and the other ends of the m switches S10 are connected with the other input end of the holding and amplifying circuit;
the multiplexer includes 3 selectors having m outputs;
the m outputs of the 3 selectors are respectively connected with the switches S8, S9 and S10 of the relevant double sampling circuits in the m branches, and are used for respectively controlling the on and off of the switches S8, S9 and S10 in the m relevant double sampling circuits, and the signals of the relevant double sampling circuits in the m branches are read out to the holding and amplifying circuit in a time sharing mode.
4. A high-speed column readout circuit for a CMOS image sensor according to claim 3, wherein:
the holding and amplifying circuit comprises a fully differential operational amplifier OP-AMP, seven switches S11-S17 and two adjustable capacitors C5 and C6;
one end of the switch S11 is connected with the other ends of the m switches S9 and is simultaneously connected with the positive input end of the fully differential operational amplifier OP-AMP and the left polar plate of the adjustable capacitor C5;
one end of the switch S12 is connected with the other ends of the m switches S10 and is simultaneously connected with the inverting input end of the fully differential operational amplifier OP-AMP and the left polar plate of the adjustable capacitor C6;
the reverse phase output end VOUTN of the fully differential operational amplifier OP-AMP is connected with one end of a switch S15 and one end of a switch S17, the normal phase output end VOUTP is connected with one end of a switch S16 and the other end of the switch S17, an input common-mode voltage signal VCMI is connected with the other end of a switch S11 and the other end of a switch S12, and an output common-mode voltage signal VCMO is connected with one end of a switch S13 and one end of a switch S14;
the right polar plate of the adjustable capacitor C5 is connected with the other end of the switch S15 and the other end of the switch S13, and the right polar plate of the adjustable capacitor C6 is connected with the other end of the switch S16 and the other end of the switch S14;
the fully differential operational amplifier OP-AMP has a non-inverting output VOUTP and an inverting output VOUTN for outputting bipolar voltage signals.
5. The high-speed column readout circuit for a CMOS image sensor according to claim 4, wherein:
the capacitor C3, the capacitor C4, the capacitor C5 and the capacitor C6 are programmable capacitors.
6. The high-speed column readout circuit for a CMOS image sensor according to claim 5, wherein:
the capacitance value of the capacitor C3 is equal to the capacitance value of the capacitor C4;
the capacitance value of the capacitor C5 is equal to the capacitance value of the capacitor C6.
7. The high-speed column readout circuit for a CMOS image sensor according to claim 6, wherein:
the external input reference voltage signal VREF is adjustable.
8. The high-speed column readout circuit for a CMOS image sensor according to claim 7, wherein the operation timings of the switches S1 to S17 are as follows:
time t 0: closing the switches S2 and S3 of all branches, turning off the other switches, and resetting the column buffer circuit;
time t 1: closing the switches S1, S4 and S6 of all branches, and turning off the other switches to sample the pixel photogenerated signals;
time t 2: closing the switches S2 and S3 of all branches, turning off the other switches, and resetting the column buffer circuit;
time t 3: closing the switches S1, S5 and S7 of all branches, turning off the other switches, and sampling pixel reset signals;
time t 4-1: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-1: the switch S8, the switch S9, the switch S10, the switch S15 and the switch S16 of the branch circuit 1 are closed, and the rest switches are turned off to read sampling signals;
time t 4-2: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-2: the switch S8, the switch S9, the switch S10, the switch S15 and the switch S16 of the branch circuit 2 are closed, and the rest switches are turned off to read sampling signals;
…
time t 4-m: closing the switch S11, the switch S12, the switch S13, the switch S14 and the switch S17, and turning off the rest switches to reset the holding and amplifying circuit;
time t 5-m: the switches S8, S9, S10, S15 and S16 of the branch m are closed, and the rest switches are turned off to read the sampling signals.
9. A high-speed column readout method for a CMOS image sensor based on the high-speed column readout circuit for a CMOS image sensor according to any one of claims 1 to 8, characterized by comprising the steps of:
step 1, adjusting the states of m column buffer circuits, and resetting the states;
step 2, turning on a ROW selection transistor ROW_SEL in a pixel circuit, and simultaneously adjusting the states of m column buffer circuits to enable the m column buffer circuits to be in an amplified state, so as to sample a photo-generated signal Vsig of the pixel circuit;
step 3, resetting floating diffusion point capacitors CFD of the pixel circuits, adjusting states of m column buffer circuits, and resetting the m column buffer circuits again;
step 4, adjusting the states of m column buffer circuits to be in an amplified state, and sampling a reset signal Vrst of a pixel circuit;
step 5, adjusting the state of the holding and amplifying circuit, and resetting the state;
step 6, selecting the branch 1 through a multiplexer, adjusting the state of the related double sampling circuit of the branch, and adjusting the state of the holding and amplifying circuit to finish the reading of the photogenerated signal and the reset signal of the branch 1;
and 7, resetting the holding and amplifying circuit, selecting the next branch through the multiplexer, and returning to the step 6 until the reading of the photo-generated signals and the reset signals of the m branches is completed, thereby realizing one-time column reading of the sampling signals of the CMOS image sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211597226.5A CN116320806A (en) | 2022-12-12 | 2022-12-12 | High-speed column readout circuit and method for CMOS image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211597226.5A CN116320806A (en) | 2022-12-12 | 2022-12-12 | High-speed column readout circuit and method for CMOS image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116320806A true CN116320806A (en) | 2023-06-23 |
Family
ID=86793035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211597226.5A Pending CN116320806A (en) | 2022-12-12 | 2022-12-12 | High-speed column readout circuit and method for CMOS image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116320806A (en) |
-
2022
- 2022-12-12 CN CN202211597226.5A patent/CN116320806A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5893573B2 (en) | Solid-state imaging device | |
| US5710563A (en) | Pipeline analog to digital converter architecture with reduced mismatch error | |
| EP2220764B1 (en) | Switched-capacitor amplifier with improved reset phase | |
| US20070030262A1 (en) | Semiconductor integrated circuit device | |
| US9716510B2 (en) | Comparator circuits with constant input capacitance for a column-parallel single-slope ADC | |
| US9979364B2 (en) | Semiconductor device with improved variable gain amplification | |
| US9525837B1 (en) | Dual sample-and-hold circuit with resistive gain | |
| US10128859B1 (en) | Correlated double sampling analog-to-digital converter | |
| CN1747526A (en) | Read-out circuit of image sensor | |
| CN111491118B (en) | Programmable gain amplifier circuit for image sensor | |
| CN105306845A (en) | Correlated double-sampling circuit capable of cancelling offset | |
| US20230254606A1 (en) | Methods and apparatus for a track and hold amplifier | |
| CN102818637B (en) | CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray) | |
| US20060197693A1 (en) | Analog-to-digital converter | |
| CN116320806A (en) | High-speed column readout circuit and method for CMOS image sensor | |
| US7042383B2 (en) | High speed gain amplifier and method in ADCs | |
| US11239856B1 (en) | Metal-oxide-semiconductor capacitor based charge sharing successive approximation register data converter | |
| CN115150572A (en) | Readout circuit and image sensor | |
| KR101322411B1 (en) | Apparatus and method for cancelling memory effect in amplifier-sharing circuit | |
| CN112436840A (en) | Sample-and-hold circuit and analog-to-digital converter comprising same | |
| CN114629497B (en) | Comparator offset voltage eliminating circuit for column parallel single-slope analog-to-digital converter | |
| US20230147629A1 (en) | Column sharing adc for image sensors and method of operation | |
| JP2007288400A (en) | Amplifier circuit and application circuit thereof | |
| Boonsobhak et al. | A pixel-level ADC with improved performance trade-off for high-speed CMOS imagers | |
| JP2005244343A (en) | Analog-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |