CN116319213A - OOK receiving device and OOK transmitting device - Google Patents

Abstract

An OOK receiving apparatus and an OOK transmitting apparatus, the OOK receiving apparatus comprising: a low noise amplifier, an automatic bias tracking demodulator, a single to differential conversion circuit, and a continuous time linear equalizer, wherein: a low noise amplifier configured to receive the OOK modulated signal through the receiving antenna; an automatic bias tracking demodulator configured to automatically track a bias voltage and demodulate the OOK modulated signal into a baseband signal; a single-to-differential conversion circuit configured to convert a baseband signal output from the auto-bias tracking demodulator into a differential signal; and the continuous time linear equalizer is configured to perform an equalizing operation on the differential signals output by the single-to-differential conversion circuit.

Description

OOK receiving device and OOK transmitting device

Technical Field

Embodiments of the present disclosure relate to, but are not limited to, the field of communications, and more particularly, to an OOK receiving apparatus and an OOK transmitting apparatus.

Background

Modern wireless communications have increasingly high requirements for data rates, and in frequency bands below 10GHz, such as bluetooth, wireless local area network (WIFI), 5G frequency 1 (FR 1), etc., due to limited spectrum resources, high-order digital modulation is often required to improve the communication rate, such as 1024-QAM (Quadrature Amplitude Modulation) modulation is adopted by WIFI 6. These higher order digital modulations can effectively improve spectral efficiency and achieve high communication rates within a narrower bandwidth. However, higher order digital modulation requires a loaded modem circuit to process the signal. In the analog domain, a quadrature local oscillator generating circuit, a quadrature mixer, local oscillator leakage calibration, image suppression and the like are required; in the digital domain, circuits such as carrier recovery and phase recovery are also needed, so that the implementation difficulty is high, and the development cost of a system chip and the system power consumption are increased.

And in millimeter wave frequency band, the available bandwidth is up to tens of gigahertz (GHz), and high communication rate can be obtained without high-order digital modulation. In communication scenes such as point-to-point interconnection, the communication circuit can use the whole bandwidth, and compared with the communication circuit which uses high-order modulation, the communication circuit uses a simpler modulation format to reduce the chip design difficulty and the system power consumption, and obtains high communication data rate by using large bandwidth, so that more balanced performance is realized.

Disclosure of Invention

The embodiment of the disclosure provides an OOK receiving apparatus, which includes: a low noise amplifier, an automatic bias tracking demodulator, a single to differential conversion circuit, and a continuous time linear equalizer, wherein:

the low noise amplifier is configured to receive the OOK modulated signal through the receiving antenna;

the automatic bias tracking demodulator is configured to automatically track bias voltage and demodulate the OOK modulation signal into a baseband signal;

the single-to-difference conversion circuit is configured to convert a baseband signal output by the automatic bias tracking demodulator into a differential signal;

the continuous time linear equalizer is configured to perform an equalizing operation on the differential signal output from the single-to-differential conversion circuit.

Optionally, the automatic bias tracking demodulator includes: a fourth resistor, a fifth resistor, a first demodulator, a replica demodulator, an operational amplifier, and a reference voltage generating circuit, wherein: the fourth resistor and the fifth resistor are connected in series and then connected between two differential input ends of the first demodulator, the series point of the fourth resistor and the fifth resistor is connected with two differential input ends of the replica demodulator and the output end of the operational amplifier, the output end of the replica demodulator is connected with one input end of the operational amplifier, and the reference voltage generating circuit is connected with the other input end of the operational amplifier; the circuit and layout of the first demodulator and the duplicate demodulator are the same.

Optionally, the first demodulator includes a fifth transistor, a sixth transistor and a sixth resistor, and the replica demodulator includes a seventh transistor, an eighth transistor and a seventh resistor, wherein: the control end of the fifth transistor is connected with one differential input end of the first demodulator, the control end of the sixth transistor is connected with the other differential input end of the first demodulator, the first stage of the fifth transistor and the first stage of the sixth transistor are grounded, the second stage of the fifth transistor and the second stage of the sixth transistor are connected with the output end and one end of the sixth resistor after being connected, and the other end of the sixth resistor is connected with the power supply voltage;

the control end of the seventh transistor is connected with the control end of the eighth transistor and then connected with the series point of the fourth resistor and the fifth resistor, the first stage of the seventh transistor and the first stage of the eighth transistor are grounded, the second stage of the seventh transistor and the second stage of the eighth transistor are connected and then connected with one input end of the operational amplifier and one end of the seventh resistor, and the other end of the seventh resistor is connected with a power supply voltage.

Optionally, the low noise amplifier includes an on-chip transformer balun and one or more cascaded amplifying networks, each of the amplifying networks includes a pseudo-differential common source amplifier and a bandwidth matching network connected in sequence, wherein: one input end of the on-chip transformer balun is a signal input end of the low-noise amplifier, the other input end of the on-chip transformer balun is grounded, and two output ends of the on-chip transformer balun are connected with two input ends of the first-stage pseudo-differential common source amplifier;

each stage of the pseudo-differential common source amplifier comprises a second capacitor, a third capacitor, a ninth transistor and a tenth transistor, one end of the second capacitor is connected with the control end of the tenth transistor and one input end of the pseudo-differential common source amplifier, and the other end of the second capacitor is connected with the second pole of the ninth transistor and one output end of the pseudo-differential common source amplifier; one end of the third capacitor is connected with the control end of the ninth transistor and the other input end of the pseudo-differential common source amplifier, and the other end of the third capacitor is connected with the second pole of the tenth transistor and the other output end of the pseudo-differential common source amplifier; the first pole of the ninth transistor and the first pole of the tenth transistor are both grounded.

Optionally, the single-to-differential conversion circuit includes: a low pass filter and one or more cascaded differential amplifier circuits, wherein: in the first n-1 stages of differential amplifier circuits, the positive input end of the first stage of differential amplifier circuits is connected with the signal input end of the single-to-differential conversion circuit, the negative input end of the first stage of differential amplifier circuits is connected with the signal input end of the single-to-differential conversion circuit through the low-pass filter, the positive output end of each stage of differential amplifier circuits is connected with the positive input end of the next stage of differential amplifier circuits, the negative output end of each stage of differential amplifier circuits is connected with the negative input end of the next stage of differential amplifier circuits, and n is the number of stages of the differential amplifier circuits.

Optionally, the low pass filter includes a first resistor and a first capacitor connected in series, wherein: the first end of the first resistor is connected with the signal input end of the single-to-differential conversion circuit, the second end of the first resistor is connected with the first end of the first capacitor and the negative input end of the differential amplifier circuit of the first stage, and the second end of the first capacitor is grounded.

Optionally, the differential amplifier circuit comprises a differential pair and an active load, wherein: the differential pair comprises a first transistor and a second transistor, wherein the control end of the first transistor is a positive input end, the control end of the second transistor is a negative input end, the first pole of the first transistor and the first pole of the second transistor are both connected with a bias current source, and the second pole of the first transistor and the second pole of the second transistor are respectively connected with two ends of the active load.

Optionally, the active load includes a second resistor, a third transistor, and a fourth transistor, wherein: the first pole of the third transistor and the first pole of the fourth transistor are both connected with a power supply voltage, the second pole of the third transistor is connected with the first end of the second resistor, the second pole of the fourth transistor is connected with the first end of the third resistor, and the control end of the third transistor and the control end of the fourth transistor are connected together and are connected with the second end of the second resistor and the second end of the third resistor.

Optionally, the active load of at least one stage further includes a differential inductor, the control terminal of the third transistor and the control terminal of the fourth transistor are connected together and connected to the second terminal of the second resistor and the second terminal of the third resistor, including: the second end of the second resistor is connected with the first end of the differential inductor, the second end of the third resistor is connected with the second end of the differential inductor, and the control end of the third transistor and the control end of the fourth transistor are connected together and are connected with a center tap of the differential inductor.

The embodiment of the disclosure also provides an OOK transmitting device, which includes: a continuous time linear equalizer, a CML to CMOS conversion circuit, a modulator, an oscillator, and a power amplifier, wherein:

the continuous time linear equalizer is configured to receive signals from the PCB channel and perform equalization operation on the received signals;

the CML-to-CMOS conversion circuitry is configured to receive the signal output by the continuous-time linear equalizer, convert the CML level to a CMOS level, and output to the modulator;

the oscillator is configured to generate an intrinsic signal and output the intrinsic signal to the modulator;

the modulator is configured to generate an OOK modulation signal according to the CMOS level output by the CML-to-CMOS conversion circuit and the intrinsic signal;

the power amplifier is configured to amplify and output an OOK modulated signal output from the modulator.

According to the millimeter wave OOK wireless receiving and transmitting device provided by the embodiment of the disclosure, the power amplifier/the low-noise amplifier are integrated on the chip, so that the transmitting power is improved, the noise coefficient is reduced, and the communication distance is further improved; compensating for the transmit-receive baseband signal loss and the bandwidth limitations of the demodulator by integrating a continuous time linear equalizer on the chip; by integrating the automatic bias tracking demodulator on the chip, the robustness of the OOK demodulator is improved.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

Fig. 1 is a schematic structural diagram of an OOK receiving apparatus according to an embodiment of the disclosure;

FIG. 2 is a block diagram of an implementation of a single slip circuit provided by an embodiment of the present disclosure;

FIGS. 3A and 3B are circuit diagrams of implementations of two single slip circuits provided in embodiments of the present disclosure;

FIG. 4 is a schematic diagram of an implementation of an automatic bias tracking demodulator provided by an embodiment of the present disclosure;

FIG. 5 is a diagram of an exemplary circuit for implementing a low noise amplifier according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an OOK transmitting device according to an embodiment of the disclosure.

Detailed Description

The present disclosure describes several embodiments, but the description is illustrative and not limiting, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure that have been disclosed may also be combined with any conventional features or elements to form a unique inventive arrangement as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

Binary amplitude Keying (OOK) modulation is a simple modulation format that represents data by the On and Off of a local oscillator signal, which when turned On represents data 1; when the local oscillation signal is off, data 0 is indicated. OOK modulation has two advantages. Firstly, OOK modulation has no requirement on the phase noise of the local oscillation signal, so that the local oscillation signal can be generated by adopting an open-loop oscillator, a complex phase-locked loop is not needed, and the design complexity and the power consumption are reduced. And secondly, at a receiving end, the OOK signal can be directly subjected to envelope detection, so that the baseband signal can be extracted without coherent demodulation, and complex carrier recovery, phase recovery loops and the like are not needed. In short, OOK modulation is paid attention to low power consumption communication and millimeter wave high-speed interconnection due to the characteristics of simple circuit structure, low implementation cost, low power consumption, no need of coherent local oscillation demodulation, and the like.

The inventor researches that the application of the traditional OOK transmitter and receiver in the millimeter wave frequency band has the following design difficulties: firstly, in the millimeter wave frequency band exceeding 100GHz, the output power of the OOK modulator is small, the noise coefficient of the OOK demodulator is large, the communication distance is limited, and because the signal carrier frequency is high and the bandwidth is wide, the signal amplification is difficult to be carried out by adopting an off-chip power amplifier and a low-noise amplifier. Second, after the OOK modulation data rate exceeds 20Gbps, the communication data rate may be limited by the transmit and receive baseband channel bandwidth and the bandwidth of the OOK demodulator. Again, OOK demodulator performance is related to its bias voltage, which fluctuates with fluctuations in process, temperature and supply voltage, requiring separate calibration for each chip, which is difficult to use.

As shown in fig. 1, an OOK receiving apparatus is provided according to an embodiment of the present disclosure, including a low noise amplifier 101, an automatic bias tracking demodulator 102, a single to differential conversion circuit 103, and a continuous time linear equalizer 104, which are connected in sequence, wherein:

a low noise amplifier 101 configured to receive an OOK modulated signal through a receiving antenna;

an auto-bias tracking demodulator 102 configured to automatically track a bias voltage and demodulate the OOK modulated signal into a baseband signal;

a single-to-difference conversion circuit 103 configured to convert the baseband signal output from the automatic bias tracking demodulator 102 into a differential signal;

the continuous-time linear equalizer 104 is configured to perform an equalizing operation on the differential signal output from the single-to-differential conversion circuit 103.

In the OOK receiving apparatus provided in the embodiment of the present disclosure, the low noise amplifier 101 receives the millimeter wave OOK modulated signal through the receiving antenna. The automatic bias tracking demodulator 102 demodulates the OOK modulated signal into a baseband signal, which is provided with a bias voltage tracking loop, which can automatically track the bias voltage, and reduce the disturbance caused by the process corner, the supply voltage and the temperature change. The single-to-differential conversion circuit 103 converts the single-ended signal output from the auto-bias tracking demodulator 102 into a differential signal. The continuous-time linear equalizer 104 compensates for the limited bandwidth of the demodulator and the insertion loss of the originating continuous-time linear equalizer in the high frequency band to improve the baseband data rate.

The OOK receiving apparatus of the embodiment of the present disclosure may be integrated as a single chip, and by integrating the low noise amplifier 101 on the single chip, noise coefficients are reduced, and communication distance is increased; compensating for the transmit-receive baseband signal loss and the bandwidth limitation of the demodulator by integrating the continuous-time linear equalizer 104 on a single chip; by integrating the automatic offset tracking demodulator 102 on a single chip, an offset automatic tracking loop is arranged in the automatic offset tracking demodulator 102, so that the robustness of the OOK demodulator is improved, and the communication distance and the data rate of the millimeter wave OOK circuit are further improved.

In some exemplary embodiments, as shown in fig. 2, the single-to-differential conversion circuit 103 includes: a low pass filter 1031 and one or more cascaded differential amplifier circuits 1032, wherein:

in the first n-1 stage differential amplifier circuit 1032, the positive input terminal of the first stage differential amplifier circuit 1032 is connected to the signal input terminal of the single-to-differential conversion circuit, the negative input terminal of the first stage differential amplifier circuit 1032 is connected to the signal input terminal of the single-to-differential conversion circuit through the low-pass filter 1031, the positive output terminal of each stage differential amplifier circuit 1032 is connected to the positive input terminal of the next stage differential amplifier circuit 1032, the negative output terminal of each stage differential amplifier circuit 1032 is connected to the negative input terminal of the next stage differential amplifier circuit 1032, and n is the number of cascade stages of the differential amplifier circuits 1032.

In some exemplary embodiments, as shown in fig. 3A or 3B, the low pass filter 1031 includes a first resistor R1 and a first capacitor C1 connected in series, wherein:

the first end of the first resistor R1 is connected to the signal input end of the single-to-differential conversion circuit, the second end of the first resistor R1 is connected to the first end of the first capacitor C1 and the negative input end of the first stage differential amplifier circuit 1032, and the second end of the first capacitor C1 is grounded.

In some exemplary embodiments, as shown in fig. 3A or 3B, the differential amplifier circuit includes a differential pair and an active load, wherein:

the differential pair comprises a first transistor T1 and a second transistor T2, wherein the control end of the first transistor T1 is a positive input end, the control end of the second transistor T2 is a negative input end, the first pole of the first transistor T1 and the first pole of the second transistor T2 are both connected with a bias current source A, and the second pole of the first transistor T1 and the second pole of the second transistor T2 are respectively connected with two ends of an active load.

In some exemplary embodiments, the active load includes a second resistor R2, a third resistor R3, a third transistor T3, and a fourth transistor T4, wherein:

the first pole of the third transistor T3 and the first pole of the fourth transistor T4 are both connected to the power supply voltage, the second pole of the third transistor T3 is connected to the first end of the second resistor R2, the second pole of the fourth transistor T4 is connected to the first end of the third resistor R3, and the control end of the third transistor T3 and the control end of the fourth transistor T4 are connected together and to the second end of the second resistor R2 and the second end of the third resistor R3.

In some exemplary embodiments, the at least one stage active load further includes a differential inductance L, and the control terminal of the third transistor T3 and the control terminal of the fourth transistor T4 are connected together and to the second terminal of the second resistor R2 and the second terminal of the third resistor R3, specifically:

the second end of the second resistor R2 is connected with the first end of the differential inductor L, the second end of the third resistor R3 is connected with the second end of the differential inductor L, and the control end of the third transistor T3 and the control end of the fourth transistor T4 are connected together and are connected with a center tap of the differential inductor L.

Fig. 2 is a block diagram of an implementation of a single slip circuit provided in an embodiment of the present disclosure. As shown in fig. 2, the single slip circuit may be formed by cascade connection of one or more differential amplifier circuits, an input signal is input to the positive input end of the first differential amplifier circuit, and a direct current component in the input signal is extracted through a low-pass filter and is input to the negative input end of the first differential amplifier circuit, so that an effect of automatically tracking the direct current component is achieved. In actual use, one or more stages of differential amplifier circuit cascade connection is determined according to the actual requirements on gain and bandwidth and the limitation on power consumption and area.

Fig. 3A and 3B are circuit diagrams of two implementations of a single slip circuit (where fig. 3A includes two stages and fig. 3B includes three stages, however, embodiments of the present disclosure are not limited thereto), and as shown in fig. 3A and 3B, the differential amplifier circuit uses a differential pair circuit with an active resistor and a PMOS transistor as a load. In the active load, the center of the resistor can be connected to the differential inductor, and then the center tap of the differential inductor is connected to the control end of the PMOS transistor, so that the effect of expanding the bandwidth is achieved. One or more stages of access differential inductors can be selected according to the requirements on speed and bandwidth and the limitation on chip area in actual use.

In some exemplary embodiments, as shown in fig. 4, the auto-bias tracking demodulator includes: a fourth resistor R4, a fifth resistor R5, a first demodulator, a replica demodulator, an operational amplifier, and a reference voltage generating circuit, wherein:

the fourth resistor R4 and the fifth resistor R5 are connected in series and then connected between two differential input ends of the first demodulator, the series point of the fourth resistor R4 and the fifth resistor R5 is connected with two differential input ends of the replica demodulator and the output end of the operational amplifier, the output end of the replica demodulator is connected with one input end (positive input end) of the operational amplifier, and the reference voltage generating circuit is connected with the other input end (negative input end) of the operational amplifier;

the first demodulator and the replica demodulator are identical in circuit and layout.

In some exemplary embodiments, the first demodulator includes a fifth transistor T5, a sixth transistor T6, and a sixth resistor R6, and the replica demodulator includes a seventh transistor T7, an eighth transistor T8, and a seventh resistor R7, wherein:

the control end of the fifth transistor T5 is connected with one differential input end (positive input end) of the first demodulator, the control end of the sixth transistor T6 is connected with the other differential input end (negative input end) of the first demodulator, the first stage of the fifth transistor T5 and the first stage of the sixth transistor T6 are grounded, the second stage of the fifth transistor T5 and the second stage of the sixth transistor T6 are connected with the output end and one end of a sixth resistor R6 after being connected, and the other end of the sixth resistor R6 is connected with a power supply voltage;

the control terminal of the seventh transistor T7 is connected to the control terminal of the eighth transistor T8 and then to the series connection point of the fourth resistor R4 and the fifth resistor R5, the first stage of the seventh transistor T7 and the first stage of the eighth transistor T8 are both grounded, the second stage of the seventh transistor T7 and the second stage of the eighth transistor T8 are connected to one input terminal (positive input terminal) of the operational amplifier and one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the power supply voltage.

Fig. 4 is a schematic diagram of an implementation of an auto-bias tracking demodulator according to an embodiment of the present disclosure. As shown in fig. 4, the drains of the two NMOS transistors (i.e., T5 and T6) are connected to a load resistor (i.e., R6), and the control terminal is connected to the differential input signal to perform an envelope detection function. In order to automatically track the bias voltage, the circuit and layout of the first demodulator are duplicated to form a duplicated demodulator, and the output end of the duplicated demodulator is connected to the positive input end of the operational amplifier. The negative input end of the operational amplifier is connected with the reference voltage generating circuit, and the output end of the operational amplifier is simultaneously connected with the control ends of the two transistors of the replica demodulator and the bias voltage input end of the first demodulator. Due to the operational amplifier feedback loop, the loop controls the output dc voltage of the replica demodulator to the output voltage of the reference voltage generating circuit, regardless of process, supply voltage and temperature fluctuations. At this time, since the first demodulator and the replica demodulator have the same parameters, circuits and layouts, the output voltage of the first demodulator is also the output voltage of the reference voltage generating circuit, thereby playing the role of automatic bias tracking.

In some exemplary embodiments, as shown in fig. 5, the low noise amplifier comprises an on-chip transformer balun and one or more cascaded amplification networks, each comprising a pseudo-differential common source amplifier and a bandwidth matching network connected in sequence, wherein:

one input end of the on-chip transformer balun is a signal input end of the low-noise amplifier, the other input end of the on-chip transformer balun is grounded, and two output ends of the on-chip transformer balun are connected with two input ends of the first-stage pseudo-differential common-source amplifier;

each stage of pseudo-differential common source amplifier comprises a second capacitor C2, a third capacitor C3, a ninth transistor T9 and a tenth transistor T10, one end of the second capacitor C2 is connected with the control end of the tenth transistor T10 and one input end of the pseudo-differential common source amplifier, and the other end of the second capacitor C2 is connected with the second pole of the ninth transistor T9 and one output end of the pseudo-differential common source amplifier; one end of the third capacitor C3 is connected with the control end of the ninth transistor T9 and the other input end of the pseudo-differential common source amplifier, and the other end of the third capacitor C3 is connected with the second pole of the tenth transistor T10 and the other output end of the pseudo-differential common source amplifier; the first electrode of the ninth transistor T9 and the first electrode of the tenth transistor T10 are both grounded.

Fig. 5 shows an exemplary circuit diagram of an implementation of a millimeter wave low noise amplifier. As shown in fig. 5, the input terminal converts the single-ended signal from the antenna into a differential signal by using an on-chip transformer balun, and then amplified by a multi-stage pseudo-differential common source amplifier (4 stages in fig. 5). Each stage of pseudo-differential common source amplifier has a neutralization capacitance to improve gain and stability. The inter-stage uses on-chip transformers for broadband matching to improve overall data rate.

As shown in fig. 6, an embodiment of the present disclosure further provides an OOK transmitting apparatus, including: a continuous time linear equalizer 601, a CML to CMOS conversion circuit 602, a modulator 603, an oscillator 604, and a power amplifier 605, wherein:

a continuous time linear equalizer 601 configured to receive a signal from a PCB channel and perform an equalization operation on the received signal;

a CML-to-CMOS conversion circuit 602 configured to receive a signal output from the continuous-time linear equalizer 601, convert the CML level into a CMOS level, and output to the modulator 603;

an oscillator 604 configured to generate an intrinsic signal, and output to the modulator 603;

a modulator 603 configured to generate an OOK modulated signal based on the CMOS level output from the CML-to-CMOS conversion circuit 602 and the intrinsic signal generated by the oscillator 604;

the power amplifier 605 is configured to amplify the OOK modulated signal output from the modulator 603.

In the OOK transmitting apparatus of the embodiment of the present disclosure, the continuous time linear equalizer 601 compensates for the loss of the PCB channel at high frequencies, and improves the baseband data rate. The CML-to-CMOS conversion circuit 602 converts the CML output level of the continuous-time linear equalizer 601 into a CMOS level, and acts on the modulator 603. The oscillator 604 generates a local oscillator signal. The OOK modulated signal generated by the modulator 603 is amplified and output via a power amplifier 605.

The OOK transmitting device of the embodiment of the disclosure may be integrated as a single chip, and by integrating the power amplifier 605 on the single chip, the transmitting power is improved, the noise factor is reduced, and thus the communication distance is improved; by integrating the continuous time linear equalizer 601 on a single chip, the signal loss of the receiving and transmitting baseband and the bandwidth limitation of the demodulator are compensated, and the communication distance and the data rate of the millimeter wave OOK circuit are further improved.

In summary, in the millimeter wave OOK wireless transceiver provided by the embodiments of the present disclosure, by integrating the power amplifier/the low noise amplifier on the chip, the transmitting power is improved, the noise factor is reduced, and thus the communication distance is increased; compensating for the transmit-receive baseband signal loss and the bandwidth limitations of the demodulator by integrating a continuous time linear equalizer on the chip; by integrating the automatic bias tracking demodulator on the chip, the robustness of the OOK demodulator is improved.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (10)

1. An OOK receiving apparatus, comprising, in order: a low noise amplifier, an automatic bias tracking demodulator, a single to differential conversion circuit, and a continuous time linear equalizer, wherein:

the low noise amplifier is configured to receive the OOK modulated signal through the receiving antenna;

the automatic bias tracking demodulator is configured to automatically track bias voltage and demodulate the OOK modulation signal into a baseband signal;

the single-to-difference conversion circuit is configured to convert a baseband signal output by the automatic bias tracking demodulator into a differential signal;

the continuous time linear equalizer is configured to perform an equalizing operation on the differential signal output from the single-to-differential conversion circuit.

2. The OOK receiving apparatus of claim 1, wherein the automatic bias tracking demodulator comprises: a fourth resistor, a fifth resistor, a first demodulator, a replica demodulator, an operational amplifier, and a reference voltage generating circuit, wherein:

the fourth resistor and the fifth resistor are connected in series and then connected between two differential input ends of the first demodulator, the series point of the fourth resistor and the fifth resistor is connected with two differential input ends of the replica demodulator and the output end of the operational amplifier, the output end of the replica demodulator is connected with one input end of the operational amplifier, and the reference voltage generating circuit is connected with the other input end of the operational amplifier;

the circuit and layout of the first demodulator and the duplicate demodulator are the same.

3. The OOK receiving apparatus of claim 2, wherein the first demodulator includes a fifth transistor, a sixth transistor and a sixth resistor, the replica demodulator includes a seventh transistor, an eighth transistor and a seventh resistor, wherein:

the control end of the fifth transistor is connected with one differential input end of the first demodulator, the control end of the sixth transistor is connected with the other differential input end of the first demodulator, the first stage of the fifth transistor and the first stage of the sixth transistor are grounded, the second stage of the fifth transistor and the second stage of the sixth transistor are connected with the output end and one end of the sixth resistor after being connected, and the other end of the sixth resistor is connected with the power supply voltage;

the control end of the seventh transistor is connected with the control end of the eighth transistor and then connected with the series point of the fourth resistor and the fifth resistor, the first stage of the seventh transistor and the first stage of the eighth transistor are grounded, the second stage of the seventh transistor and the second stage of the eighth transistor are connected and then connected with one input end of the operational amplifier and one end of the seventh resistor, and the other end of the seventh resistor is connected with a power supply voltage.

4. The OOK receiving apparatus of claim 1, wherein the low noise amplifier includes an on-chip transformer balun and one or more cascaded amplification networks, each stage of amplification network including a pseudo-differential common source amplifier and a bandwidth matching network connected in sequence, wherein:

one input end of the on-chip transformer balun is a signal input end of the low-noise amplifier, the other input end of the on-chip transformer balun is grounded, and two output ends of the on-chip transformer balun are connected with two input ends of the first-stage pseudo-differential common source amplifier;

each stage of the pseudo-differential common source amplifier comprises a second capacitor, a third capacitor, a ninth transistor and a tenth transistor, one end of the second capacitor is connected with the control end of the tenth transistor and one input end of the pseudo-differential common source amplifier, and the other end of the second capacitor is connected with the second pole of the ninth transistor and one output end of the pseudo-differential common source amplifier; one end of the third capacitor is connected with the control end of the ninth transistor and the other input end of the pseudo-differential common source amplifier, and the other end of the third capacitor is connected with the second pole of the tenth transistor and the other output end of the pseudo-differential common source amplifier; the first pole of the ninth transistor and the first pole of the tenth transistor are both grounded.

5. The OOK receiving apparatus of claim 1, wherein the single-to-differential converting circuit includes: a low pass filter and one or more cascaded differential amplifier circuits, wherein:

in the first n-1 stages of differential amplifier circuits, the positive input end of the first stage of differential amplifier circuits is connected with the signal input end of the single-to-differential conversion circuit, the negative input end of the first stage of differential amplifier circuits is connected with the signal input end of the single-to-differential conversion circuit through the low-pass filter, the positive output end of each stage of differential amplifier circuits is connected with the positive input end of the next stage of differential amplifier circuits, the negative output end of each stage of differential amplifier circuits is connected with the negative input end of the next stage of differential amplifier circuits, and n is the number of stages of the differential amplifier circuits.

6. The OOK receiving apparatus of claim 5, wherein the low pass filter includes a first resistor and a first capacitor in series, wherein:

the first end of the first resistor is connected with the signal input end of the single-to-differential conversion circuit, the second end of the first resistor is connected with the first end of the first capacitor and the negative input end of the differential amplifier circuit of the first stage, and the second end of the first capacitor is grounded.

7. The OOK receiving apparatus of claim 5, wherein the differential amplifier circuit comprises a differential pair and an active load, wherein:

the differential pair comprises a first transistor and a second transistor, wherein the control end of the first transistor is a positive input end, the control end of the second transistor is a negative input end, the first pole of the first transistor and the first pole of the second transistor are both connected with a bias current source, and the second pole of the first transistor and the second pole of the second transistor are respectively connected with two ends of the active load.

8. The OOK receiving apparatus of claim 7, wherein the active load comprises a second resistor, a third transistor, and a fourth transistor, wherein:

the first pole of the third transistor and the first pole of the fourth transistor are both connected with a power supply voltage, the second pole of the third transistor is connected with the first end of the second resistor, the second pole of the fourth transistor is connected with the first end of the third resistor, and the control end of the third transistor and the control end of the fourth transistor are connected together and are connected with the second end of the second resistor and the second end of the third resistor.

9. The OOK receiving apparatus of claim 8, wherein the at least one stage of the active load further comprises a differential inductor, the control terminal of the third transistor and the control terminal of the fourth transistor being coupled together and to the second terminal of the second resistor and the second terminal of the third resistor, comprising:

the second end of the second resistor is connected with the first end of the differential inductor, the second end of the third resistor is connected with the second end of the differential inductor, and the control end of the third transistor and the control end of the fourth transistor are connected together and are connected with a center tap of the differential inductor.

10. An OOK transmitting apparatus, comprising: a continuous time linear equalizer, a CML to CMOS conversion circuit, a modulator, an oscillator, and a power amplifier, wherein:

the continuous time linear equalizer is configured to receive signals from the PCB channel and perform equalization operation on the received signals;

the CML-to-CMOS conversion circuitry is configured to receive the signal output by the continuous-time linear equalizer, convert the CML level to a CMOS level, and output to the modulator;

the oscillator is configured to generate an intrinsic signal and output the intrinsic signal to the modulator;

the modulator is configured to generate an OOK modulation signal according to the CMOS level output by the CML-to-CMOS conversion circuit and the intrinsic signal;

the power amplifier is configured to amplify and output an OOK modulated signal output from the modulator.

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