CN116318125A - Reference sampling phase-locked loop applied to low-voltage mode - Google Patents
Reference sampling phase-locked loop applied to low-voltage mode Download PDFInfo
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Abstract
The invention discloses a reference sampling phase-locked loop applied to a low-voltage mode, which comprises a reference sampling phase discriminator, a low-pass filter, a voltage-controlled oscillator, a frequency divider module, a clock generator and a high-level boosting inverter which are connected in sequence. The invention adds the high-level boost inverter based on the existing reference sampling phase-locked loop, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the time constant of sampling under low pressure, ensures the normal sampling and holding function of the sampler under low pressure, simultaneously allows the use of a larger sampling capacitor to improve noise, and realizes the normal sampling work and superior clock jitter performance of the phase-locked loop under low pressure; and a low-pass filter is added at the output end of the reference sampling phase discriminator, so that a high-frequency pole is introduced, and the reference spurious is improved on the premise of not influencing the phase margin, thereby improving the performance of the circuit.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a reference sampling phase-locked loop applied to a low-voltage mode.
Background
To meet the increasing transmission of communication data, phase-locked loops (PLLs) with better spectral purity exhibit new dimensions. Performance metrics such as clock jitter, spurs, phase noise, power consumption, and area are all critical. Conventional Charge Pump Phase Locked Loops (CPPLLs) have difficulty meeting these stringent requirements. To achieve better jitter performance, the dead time must be set smaller to reduce In-band phase noise (IPN). However, it is excessively dependent on advanced processes, and is limited by the need to sacrifice large power consumption and problems of filter area. Furthermore, matching of charge pumps is difficult to achieve at low voltages. Sub-sampling phase-locked loop (ssppll) has better jitter performance, but its fewer frequency dividers and structural stability problems caused by high frequency operation make it difficult to use.
The advent of a Reference Sampling Phase Locked Loop (RSPLL) solves the above-described problems, with high loop gain and simple loop structure making it possible to replace CPPLL. At the same time, the sampling phase of the RSPLL operates around the reference frequency, further enhancing its structural robustness, and it can be locked without additional auxiliary loops. But it is difficult to design a low jitter, low power RSPLL in a 180nm CMOS process.
In terms of power consumption, one effective method is to reduce the power supply voltage. However, it also causes serious degradation of circuit performance, resulting in a decrease in gain factor of the phase detector and a increase in phase noise of the VCO, and on-resistance R of the sampler at low voltage operation ON The sampling time constant tau is increased, even because of V existing in the MOS tube under low pressure TH Causing the tube to enter the sub-saturation region which can greatly reduce the accuracy of the sampling. And on-resistance R ON Can change along with Vin, is inaccurate, and causes that the sampler can not realize normal sampling and holding functions and the reference sampling phase-locked loop can not realize normal phase-locking functions. While only a smaller sampling capacitance can be used to maintain the sampling time constant much smaller than the reference period τ=r×c < T REF Resulting in degradation of the sampling thermal noise. And under low-voltage operation, the power consumption of the digital circuit is reduced at the cost of reducing the operating speed, so that the frequency divider cannot realize the normal frequency division function when operating at high frequency, and the operating frequency of the phase-locked loop is limited.
Disclosure of Invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a reference sampling phase-locked loop applied in a low-voltage mode. The technical problems to be solved by the invention are realized by the following technical scheme:
the reference sampling phase-locked loop comprises a reference sampling phase discriminator, a low-pass filter, a voltage-controlled oscillator, a frequency divider module, a clock generator and a high-level boosting inverter which are connected in sequence;
wherein the reference sampling phase discriminator is used for receiving an input reference signal f ref Sampling, holding and tracking to obtain sampling output voltage V smp ；
The low-pass filter is used for outputting the voltage V to the sample smp Low-pass filtering to obtain voltage signal V with reduced ripple c ；
The voltage-controlled oscillator is used for generating a voltage signal V according to the voltage signal c Generating an output signal f out And serves as an output signal of the whole reference sampling phase-locked loop;
the frequency divider module is used for outputting the output signal f out Frequency division is carried out to obtain a frequency division output signal f div ；
The clock generator is used for dividing the frequency output signal f div Performing timing processing to output a first narrow pulse signal V 1 And a second narrow pulse signal V 2 ；
The high-level boost inverter is used for generating the first narrow pulse signal V 1 And the second narrow pulse signal V 2 Boosting to correspondingly obtain a first feedback clock signal CK 1 And a second feedback clock signal CK 2 And feeds it back to the reference sampling phase detector until the output signal f out And the reference signal f ref To achieve the phase locking function of the phase locked loop.
In one embodiment of the present invention, the reference sampling phase detector includes a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor; wherein,,
the first sampling switch and the second sampling switch are connected in series, and the first end of the first sampling switch is used as the reference signal f ref The second end of the second sampling switch is used as the output end of the reference sampling phase discriminator;
the first sampling capacitor is connected between the second end of the first sampling switch and the grounding end, and the second sampling capacitor is connected between the second end of the second sampling switch and the grounding end;
the first sampling switch is used for sampling the first feedback clock signal CK 1 Realize on or off, the second sampling switch is controlled according to the second feedback clock signal CK 2 Realize on or off.
In one embodiment of the invention, the low pass filter is a passive filter, a switched capacitor filter, or an active filter.
In one embodiment of the invention, the frequency divider module comprises a first frequency divider and a second frequency divider; the input end of the first frequency divider is connected with the output end of the voltage-controlled oscillator, and the output end of the second frequency divider is connected with the input end of the clock generator; wherein,,
the first frequency divider is an injection locking frequency divider, a current mode logic frequency divider, a true single-phase clock trigger frequency divider or a miller frequency divider.
In one embodiment of the present invention, the first frequency divider is a current mode logic four frequency divider for outputting the output signal f out Performing frequency division by fourObtaining a four-frequency division output signal f 1 ；
The second frequency divider is a multimode programmable frequency divider for dividing the four frequency output signal f 1 Frequency division is carried out to obtain a frequency division output signal f which is used as a feedback signal of the phase-locked loop div 。
In one embodiment of the present invention, the clock generator is a two-phase non-overlapping clock generator for dividing the frequency-divided output signal f div Performing time sequence processing to generate a two-phase non-overlapping first narrow pulse signal V operating at a frequency division frequency 1 And a second narrow pulse signal V 2 。
In one embodiment of the present invention, the high-level boost inverter includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first capacitor, a second capacitor, and an inverter, wherein,
the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are both connected with a power supply end;
the grid electrode of the first MOS tube is respectively connected with the source electrode of the second MOS tube, the source electrode of the third MOS tube and the first polar plate of the second capacitor;
the source electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and the first polar plate of the first capacitor;
the drain electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube; the grid electrode of the third MOS tube is respectively connected with the grid electrode of the fourth MOS tube, the second polar plate of the first capacitor and the input end of the inverter;
the source electrode of the fourth MOS tube is connected with the grounding end;
the second plate of the second capacitor is connected with the output end of the inverter;
the grid electrode of the third MOS tube is used as the input end of the high-level boost inverter, and the drain electrode of the third MOS tube is used as the output end of the high-level boost inverter.
The invention has the beneficial effects that:
1. the invention adds the high-level boost inverter based on the existing reference sampling phase-locked loop, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the time constant of sampling under low pressure, ensures the normal sampling and holding function of the sampler under low pressure, simultaneously allows the use of a larger sampling capacitor to improve noise, and realizes the normal sampling work and superior clock jitter performance of the phase-locked loop under low pressure;
2. according to the reference sampling phase-locked loop, the low-pass filter is added at the output end of the reference sampling phase discriminator, the high-frequency pole is introduced, and the reference spurious is improved on the premise of not influencing the phase margin, so that the performance of the circuit is improved;
3. the invention adopts the current mode logic four frequency divider to reduce the working frequency required by the multimode programmable frequency divider, solves the problem of the reduction of the working speed of the frequency divider caused by low-voltage operation, and realizes the normal operation of the reference sampling phase-locked loop under low voltage and superior spurious and clock jitter performance.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a block diagram of a reference sampling phase-locked loop applied in a low-voltage mode according to an embodiment of the present invention;
FIG. 2 is a detailed block diagram of a reference sampling phase-locked loop applied in a low-voltage mode according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a reference sampling phase detector provided by an embodiment of the present invention;
fig. 4 is a graph comparing on-resistance of a conventional RSPD and an RSPD of the present invention;
FIG. 5 is a PVT simulation result diagram of the on-resistance of the sampling switch driven by HBINV provided by the embodiment of the invention;
fig. 6 is a circuit diagram and a tuning curve of a voltage controlled oscillator according to an embodiment of the present invention;
fig. 7 is a circuit diagram of a frequency divider module according to an embodiment of the present invention;
FIG. 8 is a circuit diagram of a high level boost inverter provided by an embodiment of the present invention;
fig. 9 is an input-output waveform diagram of a high-level boost inverter according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a block diagram of a reference sampling phase-locked loop applied in a Low-voltage mode according to an embodiment of the present invention, which includes a reference sampling phase discriminator (Reference sampling phase detector, RSPD), a Low Pass Filter (LPF), a voltage controlled oscillator (Voltage controlled oscillator, VCO), a frequency divider module (DIV), a Clock generator (Clock generator), and a High-level boost inverter (High-level boost inverter, HBINV) connected in sequence;
wherein the reference sampling phase discriminator is used for receiving an input reference signal f ref Sampling, holding and tracking to obtain sampling output voltage V smp ；
The low-pass filter is used for sampling the output voltage V smp Low-pass filtering to obtain voltage signal V with reduced ripple c ；
The voltage-controlled oscillator is used for controlling the voltage signal V c Generating an output signal f out And serves as an output signal of the whole reference sampling phase-locked loop;
the frequency divider module is used for outputting a signal f out Frequency division is carried out to obtain a frequency division output signal f div ；
The clock generator is used for dividing the frequency of the output signal f div Performing timing processing to output a first narrow pulse signal V 1 And a second narrow pulse signal V 2 ；
The high-level boost inverter is used for generating a first narrow pulse signal V 1 And a second narrow pulse signal V 2 Boosting to correspondingly obtain a first feedback clock signal CK 1 And a second feedback clock signal CK 2 And feeds it back to the reference sampling phase detector until the output signal f out And reference signal f ref To achieve phase lock of the phase-locked loopFunction.
Specifically, referring to fig. 2, fig. 2 is a detailed structure diagram of a reference sampling phase-locked loop applied in a low-voltage mode according to an embodiment of the present invention, in which a sampling input terminal of RSPD is connected to an input reference signal f ref The two clock signal input ends are connected with the output ends of the two Nonoverlap Clock Generation, and the sampling output end is connected with the input end of the LPF. The input end of LPF is connected with the sampling output end of RSPD, and the output end is connected with the control voltage input end of VCO. The control voltage input end of the VCO is connected with the output end of the LPF, the output end is connected with the input end of the DIV, and the output signal f of the VCO out As the clock signal output by the phase locked loop. The output end of the DIV is connected with the input end of the clock generator, and the two-phase non-overlapping output ends are respectively connected with the input ends of two identical HBINVs. The input ends of the two identical HBINVs are respectively connected with two-phase non-overlapping output ends of the clock generator, and the output ends are respectively connected with two feedback clock signal input ends of the RSPD.
The invention adds the high-level boost inverter based on the existing reference sampling phase-locked loop, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the time constant of sampling under low pressure, ensures the normal sampling and holding function of the sampler under low pressure, simultaneously allows the use of a larger sampling capacitor to improve noise, and realizes the normal sampling work and superior clock jitter performance of the phase-locked loop under low pressure.
Further, referring to fig. 3, fig. 3 is a circuit diagram of a reference sampling phase detector according to an embodiment of the present invention. In this embodiment, the reference sampling phase detector comprises a first sampling switch S 1 Second sampling switch S 2 First sampling capacitor C S And a second sampling capacitor C H The method comprises the steps of carrying out a first treatment on the surface of the Wherein,,
first sampling switch S 1 And a second sampling switch S 2 In series with a first sampling switch S 1 As a reference signal f ref Is a second sampling switch S 2 The second end of the phase detector is used as the output end of the reference sampling phase detector;
first sampling capacitor C S Is connected to a first sampling switch S 1 A second sampling capacitor C between the second terminal and the ground terminal H Connected to a second sampling switch S 2 Between the second end of (c) and the ground end;
first sampling switch S 1 According to the first feedback clock signal CK 1 Realize on or off, a second sampling switch S 2 According to the second feedback clock signal CK 2 Realize on or off.
Specifically, the embodiment adopts a MOS tube NM 1 And MOS tube NM 2 Respectively as first sampling switches S 1 And a second sampling switch S 2 。
The working principle of RSPD provided in this embodiment is as follows:
first feedback clock signal CK operating at MMDIV output frequency 1 And a second feedback clock signal CK 2 As a sampling signal, f ref To input a reference signal, a first sampling switch S 1 And a second sampling switch S 2 Sampling switches respectively for master-slave two-stage sampling and a first sampling capacitor C S And a second sampling capacitor C H Sampling capacitors respectively used for master-slave two-stage sampling and sampling output signal V S And sampling the output signal V H The sampling output signals of the master-slave two-stage sampling are respectively obtained. Feedback clock signal CK 1 ，CK 2 And reference signal f ref The phase difference between the two signals represents the phase difference between the feedback signal of the reference sampling phase-locked loop and the reference signal, and the phase difference is converted into a voltage signal through a track-and-hold sampler, and the reference sampling refers to that the sampling frequency is the reference frequency.
When the first feedback clock signal CK 1 Zero crossing at the rising edge of (2) and reference signal f ref The second feedback clock signal CK is aligned with the rising edge of the first clock signal CK, and the phase difference is 0 2 Sampling output signal V of main sampler S Further sampling to obtain a sampled output signal V H . At this time, the output signal V is sampled H The voltage value of (2) is equal to the control voltage required by the voltage-controlled oscillator after being locked after passing through the LPF.
When the first feedback clock signal CK 1 And a second feedback clock signal CK 2 Lag behind reference signal f ref The phase difference at this time is not 0, and the obtained sampling output signal V H The voltage value of the voltage-controlled oscillator is smaller than the control voltage required by the voltage-controlled oscillator after the voltage value passes through the LPF.
When the first feedback clock signal CK 1 And a second feedback clock signal CK 2 Leading the reference signal f ref The phase difference at this time is not 0, and the obtained sampling output signal V H The voltage value of (2) is larger than the control voltage required by the voltage-controlled oscillator after the voltage value is locked after passing through the LPF.
Further, as shown in FIG. 2, an LPF is connected to the output of the RSPD for outputting a signal V for sampling smp Performing low-pass filtering to obtain voltage signal V c 。
Alternatively, the LPF of the present embodiment may be a passive filter, a switched capacitor filter, or an active filter, without limitation. Alternatively, the low-pass filter may be a first-order low-pass filter, or may be a low-pass filter of another order, where the specific order is not limited herein.
In this embodiment, as shown in FIG. 2, the LDF includes a filter resistor R 3 And a filter capacitor C 3 Wherein the resistance R 3 One end of the capacitor is connected with the output end of the RSPD, and the other end is connected with the output end of the RSPD through the capacitor C 3 Ground, resistance R 3 And capacitor C 3 Is used as the output end of LDF for outputting the voltage signal V with reduced ripple c 。
In the embodiment, the LPF is added at the output end of the RSPD, the high-frequency pole is introduced, the reference spurious is improved on the premise of not influencing the phase margin, and the performance of the reference sampling phase-locked loop is improved. The specific principle is as follows: let LPF be a first order filter with transfer function of
Then introduce a high frequency pole->
Wherein s is complex frequency, R 3 For filtering resistance, C 3 Is a filter capacitorTo realize the function of low-pass filtering. Then at the high frequency pole omega p At the frequency, the slope of the amplitude curve is additionally changed by-20 dB/dec, so that the suppression capability of high-frequency noise can be enhanced. A loop is provided to contain a zero point omega z And two poles omega p1 ，ω p2 Then the phase margin:
as can be seen from the phase margin PM formula, when the high frequency pole ω p Far greater than the phase-locked loop bandwidth omega c Then the high frequency pole omega p The phase margin of the phase locked loop is not affected.
In order to verify the beneficial effects of the circuit of the present invention, the on-resistance of the conventional RSPD is compared with that of the RSPD designed by the embodiment of the present invention, and the PVT of the on-resistance of the sampling switch driven by HBINV is simulated, and the results are shown in fig. 4 and fig. 5, wherein fig. 4 is a comparison diagram of the on-resistance of the conventional RSPD and that of the RSPD provided by the embodiment of the present invention, and it can be seen that the on-resistance of the RSPD provided by the present invention is much smaller than that of the conventional RSPD. Fig. 5 shows PVT simulation results of the on-resistance of the sampling switch driven by HBINV. It can be seen that at 0.1-0.9V, the on-resistance of the sampling switch can be maintained in a low resistance state.
Further, referring to fig. 6, fig. 6 is a circuit diagram and a tuning chart of a voltage controlled oscillator according to an embodiment of the invention. To obtain oscillation stability, this embodiment employs NMOS and PMOS complementary cross-coupled VCOs, as shown in the left diagram of fig. 6. At the same time, the tail current source is removed to obtain a larger amplitude, thereby reducing phase noise. The tuning curve of the VCO is shown in the right hand graph of fig. 6, and it can be seen that the VCO used has good frequency continuity and linearity in the range of 4.02 to 5.09 GHz.
In this embodiment, the frequency divider module includes a first frequency divider and a second frequency divider; the input end of the first frequency divider is connected with the output end of the voltage-controlled oscillator, and the output end of the second frequency divider is connected with the input end of the clock generator; wherein,,
the first frequency divider is an injection locked frequency divider, a current mode logic frequency divider, a true single phase clock trigger frequency divider, or a miller frequency divider.
Alternatively, as an implementation, as shown in fig. 7, the first frequency divider in the present embodiment adopts a Current-mode logic four-divider (cml_div4) for outputting the signal f out Four-frequency division is carried out to obtain a four-frequency division output signal f 1 The method comprises the steps of carrying out a first treatment on the surface of the The second frequency divider employs a multimode programmable divider (Multimode programmable frequency divider, MMDIV) for dividing the output signal f by four 1 Frequency division is carried out to obtain a frequency division output signal f which is used as a feedback signal of the phase-locked loop div 。
The invention adopts the current mode logic four frequency divider to reduce the working frequency required by the multimode programmable frequency divider, solves the problem of the reduction of the working speed of the frequency divider caused by low-voltage operation, and realizes the normal operation of the reference sampling phase-locked loop under low voltage and superior spurious and clock jitter performance.
In addition, it should be noted that, the clock generator in this embodiment adopts a two-phase non-overlapping clock generator (Nonoverlap Clock Generation), the input end of which is connected to the output end of the MMDIV, and the output end is correspondingly connected to the two HBINVs.
Specifically, nonoverlap Clock Generation performs time sequence processing on the frequency-divided output signal to obtain a first two-phase non-overlapping narrow pulse signal V 1 And a second two-phase non-overlapping narrow pulse signal V 2 The method comprises the steps of carrying out a first treatment on the surface of the First two-phase non-overlapping narrow pulse signal V 1 The first feedback clock signal CK is obtained through corresponding HBINV boosting processing 1 The method comprises the steps of carrying out a first treatment on the surface of the Second two-phase non-overlapping narrow pulse signal V 2 The second feedback clock signal CK is obtained through corresponding HBINV boosting processing 2 The method comprises the steps of carrying out a first treatment on the surface of the First feedback clock signal CK 1 And a second feedback clock signal CK 2 Two feedback clock signal inputs of RSPD are respectively inputted.
In the present embodiment, the first two-phase non-overlapping narrow pulse signal V 1 And a second two-phase non-overlapping narrow pulse signal V 2 Operating at a divided frequency, a first feedback clock signal CK 1 And a second feedback clock signal CK 2 To obtain a high swing two-phase non-overlapping narrow pulse signal at low voltage.
Further, referring to fig. 8, fig. 8 is a circuit diagram of a high-level boost inverter according to an embodiment of the present invention, which includes a first MOS transistor M 1 Second MOS tube M 2 Third MOS tube M 3 Fourth MOS tube M 4 First capacitor C 1 A second capacitor C 2 And an inverter, wherein,
first MOS tube M 1 Drain electrode of (d) and second MOS transistor M 2 The drains of the two are connected with a power supply end;
first MOS tube M 1 The grid electrodes of the MOS transistors are respectively connected with a second MOS transistor M 2 Source electrode of (C), third MOS transistor M 3 Source of (C) and second capacitance C 2 Is a first plate of (a);
first MOS tube M 1 The source electrode of (C) is connected with the second MOS tube M 2 Gate of (C) and first capacitance C 1 Is a first plate of (a);
third MOS tube M 3 The drain electrode of the transistor is connected with a fourth MOS tube M 4 A drain electrode of (2); third MOS tube M 3 The grid electrodes of the MOS transistors are respectively connected with a fourth MOS transistor M 4 Gate of (C), first capacitor C 1 And an input of an inverter;
fourth MOS tube M 4 The source electrode of the capacitor is connected with the grounding end;
second capacitor C 2 The second plate of the (B) is connected with the output end of the inverter;
third MOS tube M 3 The grid electrode of the third MOS tube M is used as the input end of the high-level boosting inverter 3 The drain of which serves as the output of the high-level boost inverter.
The working principle of the HBINV of this embodiment is as follows:
under the condition of lower power supply voltage, HBINV boosts the high level of the feedback clock signal, and remarkably reduces a sampling switch S in the reference sampling phase discriminator RSPD 1 And SS (all-over-all) 2 On-resistance R of (2) ON So that the time constant τ=r of the sampling switch and the sampling capacitor ON *C S Far smaller thanReference clock period T REF Thereby realizing the normal sampling function. The same sampling switch size achieves a smaller R ON Allowing the use of a larger capacitor to reduce sampling noise from the sampling capacitor and achieve more excellent in-band noise performance at low voltages.
As shown IN the input/output waveform diagram of HBINV IN FIG. 9, first, the potentials at the a and b points are determined, and first, the a and b points are assumed to be 0, and after the rising edge of the IN signal arrives, the voltage at both ends of the capacitor will not be suddenly changed, the voltage at the a point will be raised, M 2 Tube is conducted to C 2 Charging, the voltage at point b starts to rise, M 1 Tube is conducted to C 1 And (5) charging. This process is a positive feedback process. The final charge brings the voltages at points a and b to VDD. At this time, the charging preparation process ends. When the rising edge of the IN signal comes again, the voltage at point a will rise to 2 x VDD, although the potential at point b is reduced at a moment, but M 2 The tube is always conducted and gives C 2 And charging, namely charging the potential at the point b to VDD. Similarly, when the IN signal falls, the voltage at point b will rise to (1+m) VDD, and at instant a point a will be lowered, M 1 The tube is always conducted and gives C １ And charging to enable the point a to be charged to VDD. Normal operating state V a ，V b One of them is VDD and the other is a voltage higher than VDD, and the input/output waveforms thereof are shown in fig. 9.
Wherein the magnitude of the voltage boost multiple m is approximately:
(1) when the input IN of HBINV changes from "0" to "VDD", M 4 From off to on, M 3 From on to off. The output OUT is discharged, eventually 0. At the same time V a Through capacitor C 1 The voltage bootstrap effect of (2) is achieved by VDD, V b Reset to VDD.
(2) When the input IN of HBINV changes from "VDD" to "0", M 4 From on to off, M 3 From off to on. At the same time V a The voltage is reset to VDD. Due to M 3 The tube is opened and the tube is closed,and the output OUT has no bleed-off path, and finally V b Through capacitor C 2 The voltage bootstrap effect of (1+m) is achieved to the high level voltage of VDD, and the output OUT is charged to the high level voltage of (1+m) VDD, so that the high level boosting function of the HBINV is achieved.
In the present embodiment, the on-resistance R of the sampling switch is reduced by using HBINV ON The normal sampling and holding function of the sampler under low pressure is realized. The specific principle is as follows:
the on-resistance of the sampling switch is:
wherein mu n For electron mobility, C ox Is the capacitance of the gate oxide layer per unit area,
for the aspect ratio of the sampling switch, V GS For sampling the gate-source voltage of the MOS tube in the switch, namely the sampling voltage of the sampler, V TH Is the threshold voltage of the MOS tube in the sampling switch. HBINV increases V in the formula by boosting the sampled voltage GS Thereby reducing the on-resistance R ON 。
When the sampling switch is turned on, the time required for the output voltage to rise from zero to the maximum input level is a speed measure, and the time constant τ=r can be used ON *C S To describe, C S The size of the sampling capacitance. If the sampling rate is not fast enough, i.e. the time constant τ is not much smaller than the sampling time, the input signal cannot be completely sampled in the sampling time, which may result in distortion of the sampled output. As can be seen from the formula of the time constant τ, the sampling capacitance C is not changed S At the time, the on-resistance R is reduced ON The sampling speed can be increased, and the normal sampling function is realized. In RSPLL, the sampling time is typically the reference period or the high level pulse width of the sampled signal.
On-resistance R of sampling switch ON Introducing resistive thermal noise
Wherein K is Boltzmann constant, T is temperature, C S The size of the sampling capacitance. In order to reduce noise, the sampling capacitance must be large enough, but this results in a time constant τ=r ON *C S Is increased to decrease the sampling rate. While reducing the resistance R ON The sampling capacitance can be increased to reduce noise without increasing the time constant τ.
The working principle of the overall architecture of the low-jitter RSPLL applied in the low-voltage mode provided in this embodiment is as follows:
first, a high swing two-phase non-overlapping narrow pulse signal CK boosted by HBINV 1 ，CK 2 Input reference signal f by RSPD ref Sampling, holding and tracking to obtain sampling output voltage V smp . LPF pair sampling output signal V smp Low-pass filtering to obtain voltage signal V with reduced ripple c . Output voltage V of filter c Controlling the output frequency of the VCO as the control voltage of the VCO to obtain an output signal f out . Output signal f of oscillator out Performing four frequency division through CML_DIV4 to obtain a four frequency division output signal f 1 . Four frequency division output signal f 1 Frequency division by a multimode programmable divider MMDIV to obtain a frequency-divided output signal f as a feedback signal of the phase-locked loop div . The frequency-divided output signal FDIV is subjected to a time sequence process of Nonoverlap Clock Generation to generate a two-phase non-overlapping narrow pulse signal V operating at a frequency division frequency 1 And V 2 . Two-phase non-overlapping narrow pulse signal V 1 And V 2 The boost function of HBINV is adopted to obtain a high-swing two-phase non-overlapping narrow pulse signal CK at low voltage 1 ，CK 2 . The phase-locked loop circularly works according to the above process by negative feedback until the output voltage f of the VCO is realized out And input reference signal f ref The phase of the phase lock loop is equal, and the phase locking function of the phase lock loop is completed.
The invention adds the high-level boost inverter based on the existing reference sampling phase-locked loop, optimizes the sampling and holding switch, greatly reduces the on-resistance of the sampling switch, reduces the time constant of sampling under low pressure, ensures the normal sampling and holding function of the sampler under low pressure, simultaneously allows the use of a larger sampling capacitor to improve noise, and realizes the normal sampling work and superior clock jitter performance of the phase-locked loop under low pressure.
The invention utilizes the CMOS technology of 0.18 mu m to manufacture the reference sampling phase-locked loop with the working frequency of 4.02GHz-5.09GHz, the working voltage of 1V-1.8V, the clock jitter of 168fs and the reference spurious of-76 dBc, thereby realizing the superior performance of low voltage and low spurious low jitter.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. The reference sampling phase-locked loop is characterized by comprising a reference sampling phase discriminator, a low-pass filter, a voltage-controlled oscillator, a frequency divider module, a clock generator and a high-level boosting inverter which are connected in sequence;
wherein the reference sampling phase discriminator is used for receiving an input reference signal f ref Sampling, holding and tracking to obtain sampling output voltage V smp ；
The low-pass filter is used for outputting the voltage V to the sample smp Low-pass filtering to obtain voltage signal V with reduced ripple c ；
The voltage-controlled oscillator is used for generating a voltage signal V according to the voltage signal c Generating an output signal f out And serves as an output signal of the whole reference sampling phase-locked loop;
the frequency divider module is used for outputting the output signal f out Frequency division is carried out to obtain a frequency division output signal f div ；
The clock generator is used for matchingThe frequency-divided output signal f div Performing timing processing to output a first narrow pulse signal V 1 And a second narrow pulse signal V 2 ；
The high-level boost inverter is used for generating the first narrow pulse signal V 1 And the second narrow pulse signal V 2 Boosting to correspondingly obtain a first feedback clock signal CK 1 And a second feedback clock signal CK 2 And feeds it back to the reference sampling phase detector until the output signal f out And the reference signal f ref To achieve the phase locking function of the phase locked loop.
2. A reference sampling phase-locked loop for use in a low voltage mode according to claim 1, wherein the reference sampling phase detector comprises a first sampling switch (S 1 ) Second sampling switch (S) 2 ) A first sampling capacitor (C S ) And a second sampling capacitor (C H ) The method comprises the steps of carrying out a first treatment on the surface of the Wherein,,
the first sampling switch (S 1 ) And the second sampling switch (S 2 ) Is connected in series, and the first sampling switch (S 1 ) As the first end of the reference signal f ref Is connected to the input of the second sampling switch (S 2 ) Is used as the output end of the reference sampling phase discriminator;
the first sampling capacitor (C S ) Is connected to the first sampling switch (S 1 ) Between the second terminal of the second sampling capacitor (C H ) Is connected to a second sampling switch (S 2 ) Between the second end of (c) and the ground end;
the first sampling switch (S 1 ) According to the first feedback clock signal CK 1 Realize on or off, the second sampling switch (S 2 ) According to the second feedback clock signal CK 2 Realize on or off.
3. The reference sampling phase-locked loop of claim 1 applied in a low-voltage mode, wherein the low-pass filter is a passive filter, a switched capacitor filter, or an active filter.
4. The reference sampling phase-locked loop for use in a low voltage mode of claim 1, wherein the frequency divider module comprises a first frequency divider and a second frequency divider; the input end of the first frequency divider is connected with the output end of the voltage-controlled oscillator, and the output end of the second frequency divider is connected with the input end of the clock generator; wherein,,
the first frequency divider is an injection locking frequency divider, a current mode logic frequency divider, a true single-phase clock trigger frequency divider or a miller frequency divider.
5. The reference sampling phase-locked loop for low-voltage mode as claimed in claim 4, wherein said first frequency divider is a current-mode logic four-divider for outputting said output signal f out Four-frequency division is carried out to obtain a four-frequency division output signal f 1 ；
The second frequency divider is a multimode programmable frequency divider for dividing the four frequency output signal f 1 Frequency division is carried out to obtain a frequency division output signal f which is used as a feedback signal of the phase-locked loop div 。
6. The reference sampling phase-locked loop for use in a low voltage mode as claimed in claim 1, wherein the clock generator is a two-phase non-overlapping clock generator for dividing the frequency-divided output signal f div Performing time sequence processing to generate a two-phase non-overlapping first narrow pulse signal V operating at a frequency division frequency 1 And a second narrow pulse signal V 2 。
7. The reference sampling phase-locked loop applied in a low-voltage mode according to claim 1, wherein the high-level boost inverter comprises a first MOS transistor (M 1 ) Second MOS transistor (M) 2 ) Third MOS transistor (M) 3 ) Fourth MOS tube (M) 4 ) A first capacitor (C 1 ) A second capacitor (C 2 ) And an inverter, wherein,
the first MOS transistor (M) 1 ) And the second MOS transistor (M 2 ) The drains of the two are connected with a power supply end;
the first MOS transistor (M) 1 ) The grid electrodes of the MOS transistors are respectively connected with the second MOS transistor (M 2 ) Source electrode of (M) and third MOS transistor (M) 3 ) And the source of said second capacitance (C 2 ) Is a first plate of (a);
the first MOS transistor (M) 1 ) Is connected with the source electrode of the second MOS tube (M) 2 ) And the gate of the first capacitor (C 1 ) Is a first plate of (a);
the third MOS transistor (M) 3 ) Is connected with the drain electrode of the fourth MOS tube (M) 4 ) A drain electrode of (2); the third MOS transistor (M) 3 ) The grid electrodes of the MOS transistors are respectively connected with the fourth MOS transistor (M 4 ) Is arranged in the first capacitor (C) 1 ) And an input of the inverter;
the fourth MOS tube (M) 4 ) The source electrode of the capacitor is connected with the grounding end;
the second capacitor (C 2 ) The second plate of the (a) is connected with the output end of the inverter;
the third MOS transistor (M) 3 ) Is used as the input end of the high-level boost inverter, the third MOS transistor (M 3 ) Is used as the output end of the high-level boost inverter.
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