CN116298831A - Built-in self-test method and system for internal delay parameters of FPGA (field programmable gate array) - Google Patents

Built-in self-test method and system for internal delay parameters of FPGA (field programmable gate array) Download PDF

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Publication number
CN116298831A
CN116298831A CN202310399263.3A CN202310399263A CN116298831A CN 116298831 A CN116298831 A CN 116298831A CN 202310399263 A CN202310399263 A CN 202310399263A CN 116298831 A CN116298831 A CN 116298831A
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clock
signal
phase shift
trigger
delay
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徐元银
丛伟林
刘云搏
耿林
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Chengdu Hua Microelectronics Technology Co ltd
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Chengdu Hua Microelectronics Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31707—Test strategies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a built-in self-test method and a built-in self-test system for internal delay parameters of an FPGA, which relate to the integrated circuit technology, and the test method comprises the following steps: (1) Inputting a reference signal to the module to be tested, wherein the reference signal generates a delay signal through the module to be tested; (2) Converting the time delay between the reference signal and the delay signal into a pulse width; (3) And detecting pulse width by adopting a dynamic phase shift clock, wherein the phase difference between any two adjacent detection edges output by the dynamic phase shift clock is a fixed value. The invention solves the problem of testing precision, taking 50Mhz input clock as an example, the testing precision can reach 78.125ps, and the precision requirement is satisfied; meanwhile, a built-in self-test mode is adopted, so that a test signal is not required to be led to a test point, and extra delay is not introduced; and the built-in self-test mode is adopted, so that the test is more convenient.

Description

Built-in self-test method and system for internal delay parameters of FPGA (field programmable gate array)
Technical Field
The present invention relates to integrated circuit technology.
Background
Because the internal circuit of the FPGA is complex, the delay of the internal circuit is not fixed, if an internal signal is required to be led to an external test point, the delay value is measured through an instrument, and the external instrument cannot accurately test the delay parameter of the internal resource because the signal is led to the external test point and the additional delay is also led in; and the internal delay is in ns level, even ps level, if the delay is measured by a clock sampling method, the frequency of the internal clock must be Ghz, and at present, the system clock of the FPGA cannot reach the frequency yet, and cannot be realized.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for testing the internal delay parameters of the FPGA, which can not introduce excessive extra delay while meeting the test precision.
The technical scheme adopted by the invention for solving the technical problems is that the built-in self-test method for the internal delay parameters of the FPGA is characterized by comprising the following steps:
(1) Inputting a reference signal to the module to be tested, wherein the reference signal generates a delay signal through the module to be tested;
(2) Converting the time delay between the reference signal and the delay signal into a pulse width;
(3) And detecting pulse width by adopting a dynamic phase shift clock, wherein the phase difference between any two adjacent detection edges output by the dynamic phase shift clock is a fixed value.
In the step (3), a D trigger is adopted for detection, a pulse signal is input into a D end of the D trigger, a dynamic phase shift clock is input into a clock end of the D trigger, the output of the D trigger is detected, and meanwhile, the trigger signal of the dynamic phase shift clock is counted, so that the detection of the pulse width is realized.
The step (3) comprises:
(3.1) inputting a pulse signal into a D end of the D trigger, and inputting a dynamic phase shift clock into a clock end of the D trigger;
(3.2) detecting the output signal of the D flip-flop while counting the trigger signals of the dynamic phase-shifted clock;
(3.3) calculating a time delay: d=t/s, D is a delay value, T is an effective width of the D flip-flop output signal, and s is a phase shift number of the dynamic phase shift clock.
The invention also provides a built-in self-test system of the internal delay parameter of the FPGA, which is characterized by comprising the following parts:
the clock controller is used for generating a phase shift clock, and the phase difference of any two adjacent signal edges of the phase shift clock is equal and is a fixed value;
the signal generator is used for generating pulses with the width equal to the time delay of two paths of input signals;
the D end of the D trigger is connected with the output end of the signal generator, and the clock end of the D trigger is connected with the output end of the clock controller;
and one input end of the dynamic sampler is connected with the output end of the D trigger, and the other input end of the dynamic sampler is connected with the clock controller and is used for counting the phase shift times of the phase shift clock output signal corresponding to the effective width of the output signal of the D trigger.
The invention solves the problem of testing precision, taking 50Mhz input clock as an example, the testing precision can reach 78.125ps, and the precision requirement is satisfied; meanwhile, a built-in self-test mode is adopted, so that a test signal is not required to be led to a test point, and extra delay is not introduced; and the built-in self-test mode is adopted, so that the test is more convenient.
The invention can be used in the field of engineering application, and through delay test, the understanding of chip characteristics is deepened, more reasonable and reliable engineering is designed, and in the debugging process, the analysis is assisted to solve the problems encountered in the engineering; the method can also be used in the field of chip testing, and the delay testing efficiency and the testing precision are improved.
Drawings
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is a schematic diagram of pulse width expressing time delay.
Fig. 3 is a schematic test diagram of the present invention.
Fig. 4 is a schematic diagram of a verification environment of the present invention.
Fig. 5 is a simulated waveform diagram (software interface screenshot) of the verification of fig. 4.
Fig. 6 is a dynamic phase shift verification waveform diagram (software interface screenshot).
Fig. 7 is a sampling schematic.
Fig. 8 is a graph of measured effects (software interface screen shots).
Detailed Description
The invention provides a built-in self-test method of internal delay parameters based on dynamic phase shift of a clock manager.
DCM: digital clock management module
BUFG: global clock buffer
The built-in self-test method of the internal delay parameter of the FPGA comprises the following steps:
(1) Inputting a reference signal to the module to be tested, wherein the reference signal generates a delay signal through the module to be tested;
(2) Converting the time delay between the reference signal and the delay signal into a pulse width;
(3) And detecting pulse width by adopting a dynamic phase shift clock, wherein the phase difference between any two adjacent detection edges output by the dynamic phase shift clock is a fixed value.
The step (3) comprises:
(3.1) inputting a pulse signal into a D end of the D trigger, and inputting a dynamic phase shift clock into a clock end of the D trigger;
(3.2) detecting the output signal of the D flip-flop while counting the trigger signals of the dynamic phase-shifted clock;
(3.3) calculating a time delay: d=t/s, D is a delay value, T is an effective width of the D flip-flop output signal, and s is a phase shift number of the dynamic phase shift clock. The effective width is the width of the signal area output by the D flip-flop and corresponding to the pulse width in the step (2), for example, the step (2) expresses the time delay with a high level, and the width of the high level part of the Q end output signal of the D flip-flop is the effective width after passing through the D flip-flop.
As shown in fig. 1. The system of the invention comprises:
the clock control module generates a working clock required by the signal generator module and a dynamic phase shift clock required by the delay detection module; the step length of each phase shift of the dynamic phase shift clock is a fixed value, which is called a phase shift step length, or the phase difference between any two adjacent detection edges of the dynamic phase shift clock output is a fixed value. The detection edge refers to a signal trigger edge, for example, for a D flip-flop, the rising edge is the detection edge.
The signal generator module is used for accessing the module to be tested, generating a delay signal, comparing the delay signal Dly _s with a reference signal Ref_s, and converting the delay value of the module into a pulse signal Dly _pulse. The pulse width of Dly _pulse is the amount of delay;
and the delay detection module is used for detecting the pulse width of the Dly _pulse by using a dynamic phase shift clock, and counting the number of ps_en (phase shift times) when Dly _pulse is 1, so that the delay value of the module to be detected is obtained.
As shown in fig. 2, the dynamically phase-shifted clock signal sys_clk samples Dly _pulse are used, and since both the clock signal sys_clk and the signal under test Dly _pulse are periodic, the Dly _pulse obtained for the sys_clk sample at a certain phase must be constant, but can be either 0 or 1. The clock signal sys_clk is dynamically phase shifted to continuously change the phase of the clock, and if the phase shift range is wide enough (greater than or equal to the period of the Dly _pulse signal), the value obtained by sampling Dly _pulse will change, so that the duration of the high level Dly _pulse, that is, the delay of Dly _s relative to ref_s, can be obtained. The measurement accuracy depends on the sys_clk phase shift accuracy, which is 78.125ps for a 50Mhz clock.
As shown in FIG. 3, the vertical lines with arrows represent the sampling edges of the clock manager for each TAP delay, the numbers above the arrows range from 0 to n, the number of TAPs phase shifted by the clock manager (the number of phase shifts), 0 represents no initial phase, and n represents n TAPs phase shifts. Without loss of generality, assuming that at the initial phase, the output clock of the clock manager is sampled to Dly _pulse to be low level, after phase shifting j+1 TAPs, the output clock of the clock manager is sampled to Dly _pulse to be high level, after phase shifting k+1 TAPs, the output clock of the clock manager is sampled to Dly _pulse to be low level again, and then the duration of high level of Dly _pulse signal is k-j phase shift step values, namely delay_t= (k-j) phase shift step length of Dly _s relative to Ref_s.
Phase shift step size of 1/256 x period CLKIN
PERIOD CLKIN The clock cycles are input to the clock manager.
Examples
Building a simulation model, wherein a logic structure frame is shown in fig. 4, a global clock input pin inputs 100Mhz, three DCMs are driven after BUFG, and control logic, DCM0 and DCM1 output 2x clocks, and DCM2 outputs 1x clock clk0; wherein the 2x clock (dcm0_clk2x, equivalent to ref_s) phase of the DCM0 output is fixed to 0, i.e. phase aligned with the input clock clk_in; the 2x clock (dcm1_clk2x, corresponding to Dly _s) output by DCM1 has a phase shift of 46, i.e. a fixed phase shift of 46 phase shift steps, and Dly _s has a fixed delay of 46 phase shift steps with respect to ref_s. After dcm0_clk2x and dcm2_clk2x are subjected to logic operation (ref_s=1 and dly_s=0), a signal Dly _pulse to be detected is output; the 1x clock clk0 output by the DCM2 is dynamically phase-adjusted under the action of control logic.
Simulation analysis is performed on the logic function shown in fig. 4, and a simulation waveform is shown in fig. 5. As can be seen from the figure, after the dcm0_clk2x (ref_s) and dcm2_clk2x (Dly _s) are logically operated (ref_s=1 and dly_s=0), a square wave signal Dly _pulse, dly _pulse high-level duration, that is, a delay of Dly _s relative to ref_s, is output.
The dynamic phase shift function of DCM2 is used for continuously adjusting the phase of an output clock sys_clk, each time one tap is adjusted, the signal Dly _pulse to be tested is continuously sampled 256 times, enough sample is ensured, after 256 times of sampling are completed, the next phase adjustment is performed, and the cycle is repeated until the phase shift is adjusted to the whole adjustable range. The sampled signal is denoted as sync_data as shown in fig. 6.
After sampling the sys_clk, a very low frequency signal sync_data is obtained, which corresponds to a signal obtained by amplifying the signal to be measured Dly _pulse by a plurality of times. The phase shift amount adjusted by DCM when sync_data is high can obtain the delay of Dly _s relative to Ref_s, the simulation test result is 45 TAPs, and the delay is compared with the preset 46 TAPs, and one TAP error exists, because the phase change of sys_clk is not continuous, but can be adjusted by taking one TAP as a gradient (for 100Mhz clock, the TAP is equal to 39.0625 ps), and the situation that a certain period of high level cannot be acquired is necessarily existed on the rising edge or the falling edge of Dly _pulse, as shown in fig. 7, and the period of time t_x cannot be sampled.
The simulation result differs from the theoretical delay value by one TAP, and the error value is 39.0625ps.
The upper plate of the scheme is actually measured, and the verification test effect is shown in fig. 8.
In practical engineering application, because the sampling clock and the signal to be tested are not in the same clock domain, and because the phase of the output clock of the DCM is continuously adjusted, the situation necessarily exists, and under certain phases, the output clock of the DCM is sampled at the jump edge of the signal, and the sampling to high or low level is possible, so that burrs exist in the sampled signal. The burr signals are originally positioned at the jump edges of the signals, can be processed as 1 or 0, can be used for measuring errors, and can be used for measuring delay values without special processing, so that the test results are not affected.
The actual test delay value is 45 phase shift step sizes, which is 1 phase shift step size smaller than the theoretical value, belongs to measurement errors, and the actual measurement value accords with theoretical analysis.

Claims (4)

  1. The built-in self-test method for the internal delay parameters of the FPGA is characterized by comprising the following steps of:
    (1) Inputting a reference signal to the module to be tested, wherein the reference signal generates a delay signal through the module to be tested;
    (2) Converting the time delay between the reference signal and the delay signal into a pulse width;
    (3) And detecting pulse width by adopting a dynamic phase shift clock, wherein the phase difference between any two adjacent detection edges output by the dynamic phase shift clock is a fixed value.
  2. 2. The method for built-in self-test of internal delay parameters of an FPGA of claim 1, wherein in the step (3), a D trigger is used for detection, a pulse signal is input to a D end of the D trigger, a dynamic phase shift clock is input to a clock end of the D trigger, an output of the D trigger is detected, and at the same time, the trigger signal of the dynamic phase shift clock is counted to realize detection of pulse width.
  3. 3. The method for built-in self-test of internal delay parameters of FPGA of claim 1, wherein step (3) comprises:
    (3.1) inputting a pulse signal into a D end of the D trigger, and inputting a dynamic phase shift clock into a clock end of the D trigger;
    (3.2) detecting the output signal of the D flip-flop while counting the trigger signals of the dynamic phase-shifted clock;
    (3.3) calculating a time delay: d=t/s, D is a delay value, T is an effective width of the D flip-flop output signal, and s is a phase shift number of the dynamic phase shift clock.
  4. The built-in self-test system of the internal delay parameter of the FPGA is characterized by comprising the following parts:
    the clock controller is used for generating a phase shift clock, and the phase difference of any two adjacent signal edges of the phase shift clock is equal and is a fixed value;
    the signal generator is used for generating pulses with the width equal to the time delay of two paths of input signals;
    the D end of the D trigger is connected with the output end of the signal generator, and the clock end of the D trigger is connected with the output end of the clock controller;
    and one input end of the dynamic sampler is connected with the output end of the D trigger, and the other input end of the dynamic sampler is connected with the clock controller and is used for counting the phase shift times of the phase shift clock output signal corresponding to the effective width of the output signal of the D trigger.
CN202310399263.3A 2023-04-14 2023-04-14 Built-in self-test method and system for internal delay parameters of FPGA (field programmable gate array) Pending CN116298831A (en)

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