CN116263616A

CN116263616A - Adaptive power conditioning circuit, computing system and electronic device

Info

Publication number: CN116263616A
Application number: CN202111535426.3A
Authority: CN
Inventors: 王悬
Original assignee: Nvidia Corp
Current assignee: Nvidia Corp
Priority date: 2021-12-15
Filing date: 2021-12-15
Publication date: 2023-06-16

Abstract

Provided are an adaptive power conditioning circuit, a computing system, and an electronic device, the circuit comprising: a plurality of power sensing units for sensing power consumed by respective input power rails on a processor system board; a summer for summing the power to obtain a total power; a plurality of first conversion units each for converting power into a first bit sequence and a second conversion unit for converting total power into a second bit sequence; and a logic operation unit for performing logical OR operation on the first and second bit sequences to generate a final bit sequence, the final bit sequence being transmitted to the processor, the processor adaptively performing power adjustment based on the final bit sequence. The invention uses the hardware circuit to adaptively adjust the clock frequency, can quickly react to the power change, has better performance, saves the cost and the PCB area, is beneficial to optimizing the input power distribution network, and can be simultaneously used for the multi-processing unit circuit board.

Description

Adaptive power conditioning circuit, computing system and electronic device

Technical Field

The present invention relates to the field of computers, and more particularly, to an adaptive power conditioning circuit, computing system, and electronic device.

Background

For the individual processing units such as CPU, GPU and the like in the computing system, the consumed power is obviously different when the same or different applications are run due to the different running speed, leakage current, load and other parameters. In order for different processing units to achieve as high performance as possible under various conditions, one solution is to use dynamic over-clocking (GPU boost) and power capping (power capping) methods in the computing system to ensure that the processing units can run at higher clock frequencies while not exceeding their power or thermal limits, thereby making the processing units run more secure.

The existing schemes for realizing the dynamic over-frequency and power capping method are as follows: one is to first sense the power of each power rail on the processing system board and pass the power through I ² The C bus is fed back to the processing unit, and the processing unit further processes the power; the other is to sense the voltage and current of each power rail on the processing system board card, and feed back analog signals such as the voltage and current to the processing unit, and further process the voltage and current signals by an analog-to-digital converter (ADC) in the processing unit.

The two solutions described above have at least the following drawbacks:

1. the sensing devices used in both the above schemes cannot be shared between different processing units, and thus each processing unit needs to be provided with one sensing device, which increases the cost and causes waste of PCB (printed circuit board) area.

2. Both schemes require the use of underlying software to calculate the clock frequency, which is dependent on the core power real time value, and therefore both schemes require additional current detection circuitry to sense the power real time value, which can result in increased cost and waste of PCB area. Also, some power rails need to be monitored separately, and the power topology always divides a single power rail into two or more power rails for power sensing, so the input power distribution network is not optimal.

3. Both schemes described above are based on software calculations, which require that during calculation it is assumed that the workload at the current point in time is the same as the workload at the previous point in time, whereas in reality the two are often different. In this case, the computation will require several iterations, which makes the power capping not quickly responsive.

Accordingly, there is a need for a new type of adaptive power conditioning circuit, computing system, and electronic device that addresses the above-described and other problems.

Disclosure of Invention

The present invention has been made to solve the above-described problems. According to an aspect of the present invention, there is provided an adaptive power conditioning circuit, the circuit comprising: a plurality of power sensing units, each for sensing power consumed by a respective input power rail of a plurality of input power rails on a processor system board; a summer for summing the sensed power consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails; a plurality of first conversion units each for converting the sensed power consumed by a respective input power rail into a first bit sequence and a second conversion unit for converting the total power consumed by the plurality of input power rails into a second bit sequence; and the logic operation unit is used for carrying out logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, wherein the final bit sequence is transmitted to a processor on the processor system board card, and the processor adaptively carries out power adjustment based on the final bit sequence.

In one embodiment, the power sensing unit includes a voltage-current monitor for sensing voltage and current on a respective input power rail of the plurality of input power rails and a multiplier for converting the sensed voltage and current into power consumed by the respective input power rail.

In one embodiment, each first conversion unit converts the power consumed by a respective input power rail into the first bit sequence by stepwise comparing the power consumed by the respective input power rail with a respective target power for the input power rail.

In an embodiment, wherein the second conversion unit converts the total power consumed by the plurality of input power rails into the second bit sequence by stepwise comparing the total power with a total target power.

In one embodiment, the circuit further comprises: a clock control unit for generating a bit sequence clock signal for controlling the transmission of the final bit sequence to the processor.

In one embodiment, the circuit further comprises: and a parallel-to-serial conversion unit for parallel-to-serial converting the final bit sequence before the final bit sequence is transmitted to the processor, the converted final bit sequence being transmitted to the processor, the processor adaptively performing power adjustment based on the converted final bit sequence.

In one embodiment, the clock control unit is further configured to generate a packet clock signal, where the packet clock signal is configured to control the packet of the converted final bit sequence into a plurality of data packets, such that the converted final bit sequence is transmitted to the processor in the form of data packets.

In one embodiment, the first conversion unit and the second conversion unit each comprise a multi-stage comparator.

In one embodiment, the first conversion unit and the second conversion unit each comprise an analog-to-digital converter.

In one embodiment, the processor includes a graphics processing unit.

According to another aspect of the present invention, there is provided a computing system comprising: a processor; and an adaptive power conditioning circuit, comprising: a plurality of power sensing units, each for sensing power consumed by a respective input power rail of a plurality of input power rails on a processor system board; a summer for summing the sensed power consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails; a plurality of first conversion units each for converting the sensed power consumed by a respective input power rail into a first bit sequence and a second conversion unit for converting the total power consumed by the plurality of input power rails into a second bit sequence; and the logic operation unit is used for carrying out logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, wherein the final bit sequence is transmitted to a processor on the processor system board card, and the processor adaptively carries out power adjustment based on the final bit sequence.

In one embodiment, the adaptive power conditioning circuit further comprises: a clock control unit for generating a bit sequence clock signal for controlling the transmission of the final bit sequence to the processor.

In one embodiment, the adaptive power conditioning circuit further comprises: and a parallel-to-serial conversion unit for parallel-to-serial converting the final bit sequence before the final bit sequence is transmitted to the processor, the converted final bit sequence being transmitted to the processor, the processor adaptively performing power adjustment based on the converted final bit sequence.

In one embodiment, the processor includes a graphics processing unit.

According to yet another aspect of the present invention, there is provided an electronic device comprising an adaptive power regulating circuit as described above.

The self-adaptive power regulating circuit, the computing system and the electronic equipment of the embodiment of the invention use the hardware circuit to self-adaptively regulate the clock frequency, do not need an additional current sensing device or split a single power rail, can quickly respond to power change, so that the clock lifting and power capping performances are better, the cost and the PCB area are saved, the input power distribution network is beneficial to optimization, and the self-adaptive power regulating circuit can be simultaneously used for a multi-processing-unit circuit board.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following more particular description of embodiments of the present invention, as illustrated in the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and not constitute a limitation to the invention. In the drawings, like reference numerals generally refer to like parts or steps.

Fig. 1 shows a schematic block diagram of an exemplary adaptive power conditioning circuit according to one embodiment of the present invention.

FIG. 2 shows a table of the final bit sequence obtained by an OR operation according to one embodiment of the invention.

Fig. 3 shows a schematic diagram of the output signals of three pins of an adaptive power regulating circuit according to one embodiment of the invention.

Fig. 4 shows a bit sequence received by a processor according to one embodiment of the invention.

Fig. 5 shows a bit sequence received by a processor according to another embodiment of the invention.

FIG. 6 shows a schematic block diagram of a computing system in accordance with one embodiment of the invention.

Fig. 7 illustrates a block diagram of an example electronic device suitable for implementing at least some embodiments of the disclosure.

FIG. 8 illustrates an example operating environment in which an electronic device can operate.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present invention and not all embodiments of the present invention, and it should be understood that the present invention is not limited by the example embodiments described herein. Based on the embodiments of the invention described in the present application, all other embodiments that a person skilled in the art would have without inventive effort shall fall within the scope of the invention.

The existing scheme for realizing the dynamic over-frequency and power capping method is based on software iterative computation and has the defects. To solve the above-described problems, an embodiment of the present invention provides an adaptive power adjustment circuit including: a plurality of power sensing units, each for sensing power consumed by a respective input power rail of a plurality of input power rails in the processor; a summer for summing the sensed power consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails; a plurality of first conversion units each for converting the sensed power consumed by a respective input power rail into a first bit sequence and a second conversion unit for converting the total power consumed by the plurality of input power rails into a second bit sequence; and a logic operation unit for performing a logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, wherein the final bit sequence is transmitted to the processor, and the processor adaptively performs power adjustment based on the final bit sequence.

The self-adaptive power regulating circuit of the embodiment of the invention uses a hardware circuit to self-adaptively regulate the clock frequency, does not need an additional current sensing device or split a single power rail, and can quickly respond to power variation, thereby ensuring better clock lifting and power capping performances, saving cost and PCB area, being beneficial to optimizing an input power distribution network and being simultaneously used for a multi-processing unit circuit board.

The following describes the aspects of the invention in detail in connection with specific embodiments.

In one embodiment of the present invention, an adaptive power conditioning circuit is provided. Referring to fig. 1, fig. 1 illustrates a schematic block diagram of an exemplary adaptive power conditioning circuit 10, according to one embodiment. As shown in fig. 1, the adaptive power conditioning circuit 10 may include a plurality of power sensing units 20, a summer 30, a plurality of first and second conversion units 40 and 50, and a logic operation unit (not shown).

Wherein each power-sensing unit 20 is configured to sense power consumed by a corresponding input power rail of a plurality of input power rails on a processor system board. A plurality of power sensing units corresponding to the number of input power rails may thus be provided, each sensing the power consumed by a respective input power rail.

Illustratively, the processor system board herein is used to refer to various system boards that consume power, such as a Central Processing Unit (CPU) system board, a Graphics Processing Unit (GPU) system board, and the like, as the invention is not limited in this regard.

Wherein the power consumed by the input power rail can be obtained by measuring the voltage and current. Illustratively, the power sensing unit 20 may include a voltage-current monitor 22 and a multiplier 24. Wherein the voltage current monitor 22 is for sensing voltages and currents on respective ones of the plurality of input power rails and the multiplier 24 is for converting the sensed voltages and currents into power consumed by the respective input power rails.

In one embodiment, the voltage and current monitor 22 may be any device, apparatus, chip, etc. known in the art capable of performing voltage and current monitoring, such as a power detector, a voltage and current sampling device, etc., as the invention is not limited in this regard.

The summer 30 is configured to sum the sensed power consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails.

Each of the plurality of first conversion units 40 is for converting the sensed power consumed by the corresponding input power rail into a first bit sequence. Wherein a number of first conversion units corresponding to the number of input power rails may be provided, each of which is connected to a corresponding power sensing unit 20, respectively, to convert the power consumed by the corresponding input power rail into a first bit sequence.

In one embodiment, the first conversion unit 40 may convert the power of the respective input power rail into the first bit sequence by stepwise comparing the power consumed by the respective input power rail with the respective target power for the input power rail. In one embodiment, the first bit sequence may be a binary bit sequence consisting of 0 and 1.

In one embodiment, the first conversion unit 40 may include a multi-stage comparator (comparator ladder), as shown in fig. 1. In another embodiment, the first conversion unit 40 may include an analog-to-digital converter (ADC).

In one embodiment, the corresponding target power for the input power rail may be determined by I ² The C port is set and stored in a register.

The second conversion unit 50 may be connected to the summer 30 for converting the total power consumed by the plurality of input power rails into a second bit sequence. In one embodiment, the second bit sequence may be a binary bit sequence consisting of 0 and 1.

In one embodiment, the second conversion unit 50 converts the total power to the second bit sequence by stepwise comparing the total power consumed by the plurality of input power rails with the total target power.

In one embodiment, the second conversion unit 50 may include a multi-stage comparator, as shown in fig. 1. In another embodiment, the second conversion unit 50 may include an analog-to-digital converter (ADC).

In one embodiment, the total target power may be determined by I ² The C port is set and stored in a register.

Referring to the example of fig. 1, in the multi-stage comparator, resistors having the same number of bits as bits in a bit sequence may be connected in series to form resistor ladders (resistors), the sensed power is divided into a plurality of steps by the respective resistors, compared with a target power, and corresponding bits are output according to the comparison result, and the bits output by the respective comparators constitute the bit sequence. Wherein the target power may be set at an intermediate position of the resistor ladder.

Wherein the first bit sequence and the second bit sequence may be represented by [ dm, …, d1, d0, u0, u1, …, un ], wherein dx represents the upper bits and ux represents the lower bits. When all dx bits in the bit sequence are 0 and all ux bits are 1, it is indicated that their corresponding power is at their target power. If any lower bit ux in the bit sequence is 0, indicating that the corresponding power is lower than the target power, and increasing the clock frequency to increase the power so as to make the real-time power equal to the target power; if any of the upper bits dx in the bit sequence is 1, it indicates that its corresponding power is higher than the target power, at which time the clock frequency should be reduced to reduce the power so that the real-time power is equal to the target power.

The logic operation unit is used for carrying out logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence. Wherein the final bit sequence may be transmitted directly to the processor, which adaptively performs power adjustment based on the final bit sequence. In this way, any input power rail consuming power or the total power consumed by all power rails exceeding its own target power will trigger power throttling, thereby improving the performance of the processor.

Referring to fig. 2, fig. 2 shows a table of a final bit sequence obtained by an or operation according to an embodiment of the present invention. Taking three power rails as an example, as shown in fig. 2, dm bits of three powers of the three power rails are ored with dm bits of total power to obtain dm bits of a final bit sequence, and other bits of the final bit sequence are obtained in the same way. The resulting final bit sequence shown in fig. 2 is [0,0,0,0,1,1,1,1,1,1], i.e., bit d0 is 1, indicating that the real-time power is above the target power, at which time the clock frequency should be reduced to reduce the real-time power so that the real-time power is equal to the target power.

In one embodiment, the adaptive power regulating circuit 10 may further comprise a clock control unit 60 for generating a bit sequence clock signal for controlling the transmission of the final bit sequence to the processor.

In order to reduce the number of pins of the processor receiving the final bit sequence, in one embodiment, the adaptive power adjustment circuit 10 may further comprise a parallel-to-serial conversion unit 70 for parallel-to-serial converting the final bit sequence, converting the generated parallel bit sequence into a serial bit sequence, and then transmitting the converted final bit sequence to the processor, which adaptively performs power adjustment based on the converted final bit sequence.

In one embodiment, the logic operation unit may be included in the parallel-serial conversion unit 70 or may be a separate device, which is not limited in the present invention.

In one embodiment, the clock control unit 60 is further configured to generate a packet clock signal, where the packet clock signal is configured to control the packet of the converted final bit sequence into a plurality of data packets, and then transmit the converted final bit sequence to the processor in the form of data packets, and the processor adaptively adjusts the power based on the converted final bit sequence in the form of data packets. Wherein the processor will use the bit sequence clock signal and the packet clock signal to ensure that the bit sequence is received correctly. Therefore, the connection of the adaptive power adjustment circuit 10 to the processor only requires 3 pins, namely a power bit sequence Pin1, a bit sequence clock Pin2 and a packet clock Pin3, wherein the power bit sequence Pin1 is used for outputting the final bit sequence to the processor, the bit sequence clock Pin2 is used for outputting the bit sequence clock signal to the processor, and the packet clock Pin3 is used for outputting the packet clock signal to the processor. Referring to fig. 3, fig. 3 shows a schematic diagram of the output signals of 3 pins of an adaptive power conditioning circuit according to one embodiment of the present invention.

Wherein the amount of adjustment of the clock frequency is determined according to the pattern of the bit sequence, since the bit sequence is generated by stepwise comparison of the power with the target power. Referring to fig. 4, fig. 4 shows a bit sequence received by a processor according to one embodiment of the invention. As shown in fig. 4, the lower ux contains 0, indicating that the power is lower than the target power, the clock frequency should be increased to increase the power, and both lower u0 and u1 are 0, so the clock frequency should be increased by 2 steps (step). Referring to fig. 5, fig. 5 shows a bit sequence received by a processor according to another embodiment of the present invention. As shown in fig. 5, the high order dx contains 1, indicating that the power is higher than the target power, at which time the clock frequency should be reduced to reduce the power, and only one low order d0 is 1, so the clock frequency should be reduced by one step (step). That is, the more the power differs from the target power, the more steps the clock frequency is adjusted.

In another embodiment of the present invention, a computing system is provided. Referring to FIG. 6, FIG. 6 shows a schematic block diagram of a computing system 600 according to one embodiment of the invention. As shown in fig. 6, computing system 600 may include a processor 610 and an adaptive power adjustment circuit 620.

The processor 610 may be various elements that consume power, such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), etc., and may also be used to refer to a circuit board that includes the processor, such as a graphics card, etc.

The adaptive power conditioning circuit 620 may be the adaptive power conditioning circuit 10 described above. Only the main structure of the adaptive power adjustment circuit 620 is shown below, and specific details are not described here for brevity.

The adaptive power conditioning circuit 620 may include a plurality of power sensing units, a summer, a plurality of first and second conversion units, and a logic operation unit.

Wherein each power-sensing unit is configured to sense power consumed by a respective input power rail of a plurality of input power rails on a processor system board. A plurality of power sensing units corresponding to the number of input power rails may thus be provided, each sensing the power consumed by a respective input power rail.

Wherein the power consumed by the input power rail can be obtained by measuring the voltage and current. The power sensing unit may include a voltage current monitor and a multiplier, for example. Wherein the voltage current monitor is for sensing voltage and current on a respective input power rail of the plurality of input power rails, and the multiplier is for converting the sensed voltage and current into power consumed by the respective input power rail.

In one embodiment, the voltage and current monitor may be any device, apparatus, chip, etc. known in the art capable of performing voltage and current monitoring, such as a power detector, a voltage and current sampling device, etc., which the present invention is not limited to.

The summer is configured to sum the sensed power consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails.

Each first conversion unit of the plurality of first conversion units is for converting the sensed power consumed by the respective input power rail into a first bit sequence. Wherein a plurality of first conversion units corresponding to the number of input power rails may be provided, each first conversion unit being connected to a corresponding power sensing unit, respectively, to convert the power consumed by the corresponding input power rail into a first bit sequence.

In one embodiment, the first conversion unit may convert the power of the respective input power rail into the first bit sequence by stepwise comparing the power consumed by the respective input power rail with the respective target power for the input power rail. In one embodiment, the first bit sequence may be a binary bit sequence consisting of 0 and 1.

The second conversion unit may be connected to the summer for converting the total power consumed by the plurality of input power rails into a second bit sequence. In one embodiment, the second bit sequence may be a binary bit sequence consisting of 0 and 1.

In one embodiment, the second conversion unit converts the total power consumed by the plurality of input power rails into the second bit sequence by stepwise comparing the total power with the total target power.

In one embodiment, the adaptive power adjustment circuit 620 may further include a clock control unit for generating a bit sequence clock signal for controlling the transmission of the final bit sequence to the processor.

In order to reduce the number of pins of the processor receiving the final bit sequence, in one embodiment, the adaptive power adjustment circuit may further comprise a parallel-to-serial conversion unit for parallel-to-serial converting the final bit sequence before the final bit sequence is transmitted to the processor, converting the generated parallel bit sequence into a serial bit sequence, and then transmitting the converted final bit sequence to the processor, which adaptively performs power adjustment based on the converted final bit sequence.

In one embodiment, the logic operation unit may be included in the parallel-serial conversion unit or may be a separate device, which is not limited in the present invention.

In one embodiment, the clock control unit is further configured to generate a packet clock signal, where the packet clock signal is configured to control the packet of the converted final bit sequence into a plurality of data packets, and then transmit the converted final bit sequence in the form of data packets to the processor, and the processor adaptively adjusts the power based on the converted final bit sequence in the form of data packets.

Wherein the amount of adjustment of the clock frequency is determined according to the pattern of the bit sequence, since the bit sequence is generated by stepwise comparison of the power with the target power.

The computing system of the embodiment of the invention comprises the self-adaptive power regulating circuit, the clock frequency is regulated in a self-adaptive way by using the hardware circuit, an additional current sensing device is not required, a single power rail is not required to be split, and the power change can be responded quickly, so that the clock lifting and power capping performances are better, the cost and the PCB area are saved, the input power distribution network is facilitated to be optimized, and the computing system can be simultaneously used for a multi-processing-unit circuit board.

The embodiment provides an electronic device. By way of example, the electronic device may include any electronic device known in the art having more than one circuit board, such as a desktop computer, laptop computer, tablet computer, smart home device, cell phone, robot, etc., as the invention is not limited in this regard. The electronic device of the present embodiment may include the circuit board according to the embodiment of the present invention described above.

Referring now to fig. 7, fig. 7 is a block diagram of one example electronic device 700 suitable for use in implementing at least some embodiments of the present disclosure. Electronic device 700 may include bus 702 that directly or indirectly couples the following devices: memory 704, one or more Central Processing Units (CPUs) 706, one or more Graphics Processing Units (GPUs) 708, a communication interface 710, input/output (I/O) ports 712, input/output (I/O) components 714, a power supply 716, and one or more presentation components 718 (e.g., one or more displays).

Although the various blocks of fig. 7 are shown as being connected to wires via bus 702, this is not intended to be limiting and is for clarity only. For example, in some embodiments, the presentation component 718 (e.g., a display device) can be considered the I/O component 714 (e.g., if the display is a touch screen). As another example, CPU 706 and/or GPU 708 may include memory (e.g., memory 704 may represent a storage device in addition to memory of GPU 708, CPU 706, and/or other components). In other words, the electronic device of fig. 7 is merely illustrative. Categories such as "workstation," "server," "notebook," "desktop," "tablet," "client device," "mobile device," "handheld device," "gaming machine," "Electronic Control Unit (ECU)", "virtual reality system," "robotic device," and/or other device or system types are not distinguished because all categories are considered within the scope of the electronic device of fig. 7.

Bus 702 may represent one or more buses, such as an address bus, a data bus, a control bus, or a combination thereof. Bus 702 may include one or more bus types, such as an Industry Standard Architecture (ISA) bus, an Extended ISA (EISA) bus, a Video Electronics Standards Association (VESA) bus, a Peripheral Component Interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and/or other types of bus.

Memory 704 may include any of a variety of computer-readable media. Computer readable media can be any available media that can be accessed by electronic device 700. Computer-readable media may include both volatile and nonvolatile media, and removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media.

Computer storage media may include volatile and nonvolatile media and/or removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules, and/or other data types. For example, memory 704 may store computer readable instructions (e.g., instructions representing one or more programs and/or one or more program elements, such as an operating system). Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by electronic device 700. As used herein, a computer storage medium does not itself contain a signal.

Communication media may embody computer readable instructions, data structures, program modules, and/or other data types in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" may mean a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Combinations of any of the above should also be included within the scope of computer readable media.

The one or more CPUs 706 can be configured to execute computer-readable instructions to control one or more components of the electronic device 700 to perform one or more of the methods and/or processes described herein. Each of the one or more CPUs 706 can include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) that are capable of processing multiple software threads simultaneously. The one or more CPUs 706 can include any type of processor and can include different types of processors depending on the type of electronic device 700 implemented (e.g., fewer processors for the mobile device and more processors for the server). For example, depending on the type of electronic device 700, the processor may be an ARM processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). In addition to one or more microprocessors or auxiliary coprocessors, such as a data coprocessor, the electronic device 700 may include one or more CPUs 706.

The electronic device 700 may render graphics (e.g., 3D graphics) using one or more GPUs 708. One or more GPUs 708 may include hundreds or thousands of cores that are capable of processing hundreds or thousands of software threads simultaneously. The one or more GPUs 708 may generate pixel data of an output image in response to rendering commands (e.g., rendering commands received from the one or more CPUs 706 via a host interface). One or more GPUs 708 may include a graphics memory, such as a display memory, to store pixel data. Display memory may be included as part of memory 704. The one or more GPUs 708 may include two or more GPUs that run in parallel (e.g., via a link). When combined together, each GPU 708 may generate pixel data for different portions of the output image or different output images (e.g., a first GPU for the first image and a second GPU for the second image). Each GPU may include its own memory or may share memory with other GPUs.

In examples where the electronic device 700 does not include one or more GPUs 708, the one or more CPUs 706 can be used to render graphics.

The communication interface 710 may include one or more receivers, transmitters, and/or transceivers that enable the electronic device 700 to communicate with other electronic devices via an electronic communication network, including wired and/or wireless communication. The communication interface 710 may include components and functionality to enable communication over any number of different networks, such as a wireless network (e.g., wi-Fi, Z-wave, bluetooth LE, zigBee, etc.), a wired network (e.g., communication over ethernet), a low power wide area network (e.g., loRaWAN, sigFox, etc.), and/or the internet, among others.

The I/O ports 712 can enable the electronic device 700 to be logically coupled to other devices, including an I/O component 714, one or more presentation components 718, and/or other components, some of which can be built into (e.g., integrated into) the electronic device 700. Illustrative I/O components 714 include microphones, mice, keyboards, joysticks, game pads, game controllers, satellite disks, scanners, printers, wireless devices, and the like. The I/O component 714 can provide a Natural User Interface (NUI) that processes user-generated air gestures, voice, or other physiological input. In some cases, the input may be transmitted to an appropriate network element for further processing. NUI may enable speech recognition, handwriting recognition, facial recognition, biometric recognition, on-screen and near-screen gesture recognition, air gestures, head and eye tracking, and touch recognition (described in more detail below) associated with a display of electronic device 700. The electronic device 700 may include a depth camera (e.g., a stereoscopic camera system), an infrared camera system, an RGB camera system, touch screen technology, and combinations of these for gesture detection and recognition. Furthermore, the electronic device 700 may include an accelerometer or gyroscope (e.g., as part of an Inertial Measurement Unit (IMU)) for detecting motion. In some examples, the output of the accelerometer or gyroscope may be used by the electronic device 700 to present immersive augmented reality or virtual reality.

The power supply 716 may include a hard-wired power supply, a battery power supply, or a combination thereof. The power supply 716 may provide power to the electronic device 700 to enable components of the electronic device 700 to operate.

The one or more presentation components 718 may include a display (e.g., monitor, touch screen, television screen, heads-up display (HUD), other display types, or combinations thereof), speakers, and/or other presentation components. One or more rendering components 718 may receive data from other components (e.g., one or more GPUs 708, one or more CPUs 706, etc.) and output data (e.g., images, video, sound, etc.).

Example operating Environment

According to some embodiments of the present disclosure, the electronic device 700 may be implemented in the example operating environment 800 of fig. 8.

Operating environment 800 includes, among other components not shown, one or more client devices 820, one or more networks 840, one or more server devices 860, and one or more data stores 850. It is to be appreciated that the operating environment 800 illustrated in fig. 8 is an example of one suitable operating environment. Each of the components shown in fig. 8 may be implemented via any type of computing device, such as, for example, one or more of the electronic devices 700 described in connection with fig. 5. These components may communicate with each other via a network 840, which may be wired, wireless, or both. Network 840 may include multiple networks or one of the networks, but is shown in simplified form so as not to obscure aspects of the present disclosure. For example, network 840 may include one or more Wide Area Networks (WANs), one or more Local Area Networks (LANs), one or more public networks such as the internet, and/or one or more private networks. Where network 840 comprises a wireless telecommunications network, components such as base stations, communication towers, or even access points (among other components) may provide wireless connectivity.

It should be appreciated that any number of client devices 820, server devices 860, and data stores 850 may be employed within the operating environment 800 within the scope of the present disclosure. Each may be configured as a single device or as multiple devices that cooperate in a distributed environment.

The one or more client devices 820 may include at least some of the components, features, and functions of the example electronic device 700 described herein with respect to fig. 5. By way of example and not limitation, client device 820 may be embodied as a Personal Computer (PC), laptop computer, mobile device, smart phone, tablet computer, smart watch, wearable computer, personal Digital Assistant (PDA), MP3 player, global Positioning System (GPS) or device, video player, handheld communication device, gaming device or system, entertainment system, vehicle mounted computer system, embedded system controller, remote control, appliance, consumer electronics device, workstation, any combination of these delineated devices, or any other suitable device.

The one or more client devices 820 may include one or more processors and one or more computer-readable media. The computer-readable medium may include computer-readable instructions executable by one or more processors. The instructions, when executed by one or more processors, may cause the one or more processors to perform desired functions.

The one or more server devices 860 may also include one or more processors and one or more computer-readable media. The computer-readable medium includes computer-readable instructions executable by one or more processors. The instructions, when executed by one or more processors, may cause the one or more processors to perform desired functions.

The one or more data stores 850 can include one or more computer-readable media. The computer-readable medium may include computer-readable instructions executable by one or more processors. The instructions, when executed by one or more processors, may cause the one or more processors to perform desired functions. One or more data stores 850 (or computer data stores) are depicted as a single component, but may be embodied as one or more data stores (e.g., databases) and may be at least partially in the cloud.

Although depicted as being external to one or more server devices 860 and one or more client devices 820, one or more data stores 850 may be implemented, at least in part, on any combination of one or more server devices 860 and/or one or more client devices 820 (e.g., as memory 504 of fig. 5). For example, some information may be stored on one or more client devices 820 and other and/or replica information may be stored externally (e.g., on one or more server devices 860). Thus, it should be appreciated that information in one or more data stores 850 may be distributed (which may be hosted externally) in any suitable manner across one or more data stores for storage. For example, the one or more data stores 850 can include at least some of one or more computer-readable media of the one or more server devices 860 and/or at least some of one or more computer-readable media of the one or more client devices 820.

Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above illustrative embodiments are merely illustrative and are not intended to limit the scope of the present invention thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in order to streamline the invention and aid in understanding one or more of the various inventive aspects, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the invention. However, the method of the present invention should not be construed as reflecting the following intent: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be combined in any combination, except combinations where the features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

The foregoing description is merely illustrative of specific embodiments of the present invention and the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the scope of the present invention. The protection scope of the invention is subject to the protection scope of the claims.

Claims

1. An adaptive power conditioning circuit, the circuit comprising:

a plurality of power sensing units, each for sensing power consumed by a respective input power rail of a plurality of input power rails on a processor system board;

a summer for summing the sensed power consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails;

a plurality of first conversion units each for converting the sensed power consumed by a respective input power rail into a first bit sequence and a second conversion unit for converting the total power consumed by the plurality of input power rails into a second bit sequence;

a logic operation unit for performing a logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence,

Wherein the final bit sequence is transmitted to a processor on the processor system board, the processor adaptively performing power adjustment based on the final bit sequence.

2. The circuit of claim 1, wherein the power sensing unit comprises a voltage-current monitor for sensing voltage and current on a respective input power rail of the plurality of input power rails and a multiplier for converting the sensed voltage and current into power consumed by the respective input power rail.

3. The circuit of claim 1, wherein each first conversion unit converts power consumed by a respective input power rail into the first bit sequence by stepwise comparing the power consumed by the respective input power rail with a respective target power for the input power rail.

4. The circuit of claim 1, wherein the second conversion unit converts the total power consumed by the plurality of input power rails to the second bit sequence by stepwise comparing the total power with a total target power.

5. The circuit of claim 1, wherein the circuit further comprises: a clock control unit for generating a bit sequence clock signal for controlling the transmission of the final bit sequence to the processor.

6. The circuit of claim 5, wherein the circuit further comprises: and a parallel-to-serial conversion unit for parallel-to-serial converting the final bit sequence before the final bit sequence is transmitted to the processor, the converted final bit sequence being transmitted to the processor, the processor adaptively performing power adjustment based on the converted final bit sequence.

7. The circuit of claim 6, wherein the clock control unit is further configured to generate a packet clock signal that is configured to control the encapsulation of the converted final bit sequence into a plurality of data packets such that the converted final bit sequence is transmitted to the processor in the form of data packets.

8. The circuit of claim 1, wherein the first conversion unit and the second conversion unit each comprise a multi-stage comparator.

9. The circuit of claim 1, wherein the first conversion unit and the second conversion unit each comprise an analog-to-digital converter.

10. The circuit of claim 1, wherein the processor comprises a graphics processing unit.

11. A computing system, the computing system comprising:

a processor; and

an adaptive power conditioning circuit, comprising:

12. The computing system of claim 11, wherein the power sensing unit includes a voltage-current monitor to sense voltage and current on a respective input power rail of the plurality of input power rails and a multiplier to convert the sensed voltage and current to power consumed by the respective input power rail.

13. The computing system of claim 11, wherein each first conversion unit converts power consumed by a respective input power rail into the first bit sequence by stepwise comparing the power consumed by the respective input power rail with a respective target power for the input power rail.

14. The computing system of claim 11, wherein the second conversion unit converts the total power consumed by the plurality of input power rails to the second bit sequence by stepwise comparing the total power to a total target power.

15. The computing system of claim 11, wherein the adaptive power conditioning circuit further comprises: a clock control unit for generating a bit sequence clock signal for controlling the transmission of the final bit sequence to the processor.

16. The computing system of claim 15, wherein the adaptive power conditioning circuit further comprises: and a parallel-to-serial conversion unit for parallel-to-serial converting the final bit sequence before the final bit sequence is transmitted to the processor, the converted final bit sequence being transmitted to the processor, the processor adaptively performing power adjustment based on the converted final bit sequence.

17. The computing system of claim 16, wherein the clock control unit is further configured to generate a packet clock signal that is configured to control the encapsulation of the converted final bit sequence into a plurality of data packets such that the converted final bit sequence is transmitted to the processor in the form of data packets.

18. The computing system of claim 11, wherein the first conversion unit and the second conversion unit each comprise a multi-stage comparator.

19. The computing system of claim 11, wherein the first conversion unit and the second conversion unit each comprise an analog-to-digital converter.

20. The computing system of claim 11, wherein the processor comprises a graphics processing unit.

21. An electronic device comprising the adaptive power conditioning circuit of any of claims 1-10.