CN116208151A

CN116208151A - ADC channel delay calibration method, system and equipment based on weak signals

Info

Publication number: CN116208151A
Application number: CN202310222720.1A
Authority: CN
Inventors: 胡佳栋; 赵习儒; 董晶晶; 夏海云
Original assignee: Nanjing University of Information Science and Technology
Current assignee: Nanjing University of Information Science and Technology
Priority date: 2023-03-09
Filing date: 2023-03-09
Publication date: 2023-06-02

Abstract

The invention discloses an ADC channel delay calibration method, system and equipment based on weak signals, which relate to the technical field of ADC channel delay and comprise the following steps: firstly, inputting a weak signal with known frequency and phase and an analog signal to be detected into an ADC at the same time; extracting weak signals through a weak signal detection module; and then calculating the delay of the ADC channel by using the weak signals extracted from the ADC sampling data. Since the input and extraction of the weak signal can be performed in real time, the delay of the ADC channel can be calibrated in real time, which allows the correction of the delay of the ADC channel to be performed in real time. By the method, delay alignment of sampling data can be carried out on a plurality of ADC channels, so that strict relative delay relation of each ADC channel is not required to be ensured during hardware circuit design.

Description

ADC channel delay calibration method, system and equipment based on weak signals

Technical Field

The invention relates to the technical field of ADC channel delay, in particular to an ADC channel delay calibration method, an ADC channel delay calibration system and ADC channel delay calibration equipment based on weak signals.

Background

An ADC (Analog-to-digital converter) is capable of converting an electrical signal of Analog quantity into a digital electrical signal. The delay of the ADC channel, i.e. the time required for a signal to pass from the input to become a binary data in the digital circuit, is important in certain applications, especially in applications where the ADC is continuously operated in a variable environment. For example, the time-interleaved sampling ADC realizes a higher sampling rate by alternately and parallelly sampling a plurality of sub-ADCs, the accuracy of the delay of each sub-ADC channel determines the uniformity of the sampling interval of the time-interleaved sampling ADC system, and the small deviation of the channel delay also causes the rapid deterioration of key indexes such as the effective bits of the time-interleaved sampling ADC. For another example, an acquisition system for a wind lidar may result in reduced range resolution of the lidar if the ADC does not have deterministic channel delays.

Therefore, high-precision calibration of the delay of the ADC channel is an important technique, and the calibration is divided into two steps of calibration and correction. In order to realize accurate ADC channel delay, accurate calibration is needed to be carried out on the delay of the ADC channel, so that accurate basis is provided for subsequent delay correction.

The traditional ADC channel delay calibration method is to input a sine signal with larger amplitude, and then to perform sine fitting analysis on the sampled data, so as to accurately calculate the delay of the ADC channel. However, this method requires calibration to be completed before the ADC collects the signal to be measured, and calibration cannot be performed during the collection. In addition, the delay of the ADC channel varies with the operating time and operating environment of the ADC, and typically, when the operating voltage or operating temperature of the ADC varies, the original calibration result will fail to some extent or even fail completely. Although the conventional delay correction method can generally implement real-time delay correction, when the delayed calibration result fails, the correction will also fail, so that the failure to implement real-time delay calibration also means that the real-time delay calibration cannot be implemented. Therefore, the conventional delay calibration method has a certain limitation, and is difficult to cope with the situation that the ADC needs to work continuously and for a long time under a variable environment.

Disclosure of Invention

In order to solve the defects in the background art, the invention aims to provide a method, a system and equipment for calibrating the channel delay of an ADC (analog to digital converter) based on a weak signal, so that the ADC can continuously and continuously work in a variable environment for a long time, and can also calibrate the channel delay in real time during the working, thereby enhancing the applicability of the ADC.

The aim of the invention can be achieved by the following technical scheme: a method for calibrating ADC channel delay based on weak signals comprises the following steps:

inputting a weak signal with known frequency and phase and an analog signal to be detected into an ADC at the same time;

the digital processing chip receives the ADC sampling data and extracts weak signals from the ADC sampling data;

and calculating the delay of the ADC channel by using the extracted weak signals.

Optionally, when the calibration accuracy of the delay of the ADC channel is high, the weak signal input into the ADC together with the analog signal to be tested is a sine signal.

The weak signal amplitude is small, and the weak signal amplitude is in the same amplitude level as the noise component, or the weak signal amplitude is smaller than the noise amplitude.

Optionally, the ADC channel receives ADC sample data using a weak signal detection module in the digital processing chip.

Optionally, the method for extracting the weak signal comprises the following steps:

setting the sampling rate of the ADC to be M/N times of the repetition frequency of the weak signal, then sampling M points of the weak signal in every N periods, forming the sampling points into a weak signal in one period, wherein each K sampling points are a group, sampling group A data, K is integer multiple of M, A is a positive integer, the sampling point serial numbers of each group are i=1, 2, and the number K, accumulating the sampling points with the same serial numbers in each group, and finally obtaining an accumulated sum waveform containing K data.

Wherein optionally, M and N are integers of mutually prime.

Optionally, when a is sufficiently large, a component corresponding to the weak signal becomes obvious in the accumulated sum waveform, and the phase of the accumulated sum waveform has a deterministic relationship with the phase of the weak signal.

Wherein optionally, the process of calculating the delay of the ADC channel is as follows: fitting the accumulated sum waveform to obtain the position of a certain characteristic edge of the waveform in the accumulated sum waveform, setting the sampling period of the ADC as Ts, setting the characteristic edge obtained by fitting at the X-th point of the accumulated sum waveform, and obtaining the delay of an ADC channel as (XTs/N+C) if the sampling rate of the ADC is M/N times of the weak signal repetition frequency, wherein C is a constant and is obtained by calibration.

Optionally, by using the method, delay calibration can be performed on 2 or more ADC channels, so that when delay values of the channels are different, delay alignment can be performed on sampling data according to the calibrated delay values, and thus, when designing a hardware circuit, it is unnecessary to strictly ensure that the relative delay of each ADC channel is completely equal to a target value, thereby reducing design requirements of the hardware circuit.

An ADC channel delay calibration system based on weak signals, comprising:

the signal input module: the analog signal processing circuit is used for inputting a weak signal with known frequency and phase and an analog signal to be detected into the ADC at the same time;

weak signal detection module: for extracting and receiving weak signals;

ADC channel delay calculation module: and calculating the delay of the ADC channel by using the extracted weak signals.

An apparatus, comprising:

one or more processors;

a memory for storing one or more programs;

when one or more of the programs are executed by one or more of the processors, the one or more of the processors implement an ADC channel delay calibration method based on weak signals as described above.

The invention has the beneficial effects that:

the ADC channel delay calibration technology based on the weak signals can calibrate the delay of the ADC channel in real time without affecting the normal operation and performance of the ADC, and provides delay adjustment information for the realization of the deterministic delay of the ADC channel. By the method, delay alignment of sampling data can be carried out on a plurality of ADC channels, so that strict relative delay relation of each ADC channel is not required to be ensured during hardware circuit design.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to those skilled in the art that other drawings can be obtained according to these drawings without inventive effort;

FIG. 1 is a schematic diagram of the present invention;

FIG. 2 is a schematic diagram of the principle structure of an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 1, the method for calibrating the ADC channel delay based on the weak signal comprises the following steps:

It should be further noted that, in the implementation process, when the calibration accuracy requirement of the ADC channel delay is high, the weak signal input into the ADC together with the analog signal to be tested is a sinusoidal signal.

It should be further noted that, in the implementation process, when the calibration accuracy requirement of the ADC channel delay is low, the weak signal input into the ADC together with the analog signal to be tested is a square wave signal and a peak pulse signal.

It should be further noted that, in the implementation process, the weak signal amplitude is small, and the weak signal amplitude is in the same amplitude level as the noise component, or is smaller than the noise amplitude.

It should be further noted that, in the implementation process, the ADC channel receives ADC sampling data by using a weak signal detection module in the digital processing chip.

It should be further noted that, in the implementation process, the method for extracting the weak signal is as follows:

It should be further noted that, in the implementation process, M and N are integers of mutually equal quality.

It should be further noted that, in the implementation process, when a is sufficiently large, the component corresponding to the weak signal becomes obvious in the accumulated sum waveform, and the phase of the accumulated sum waveform has a deterministic relationship with the phase of the weak signal.

It should be further noted that, in the implementation process, the process of calculating the delay of the ADC channel is as follows: fitting the accumulated sum waveform to obtain the position of a certain characteristic edge of the waveform in the accumulated sum waveform, setting the sampling period of the ADC as Ts, setting the characteristic edge obtained by fitting at the X-th point of the accumulated sum waveform, and obtaining the delay of an ADC channel as (XTs/N+C) if the sampling rate of the ADC is M/N times of the weak signal repetition frequency, wherein C is a constant and is obtained by calibration; by the method, delay calibration can be carried out on 2 or more ADC channels, so that when delay values of all the channels are different, sampling data can be aligned according to the calibrated delay values, and when a hardware circuit is designed, the relative delay of all the ADC channels can be not required to be strictly ensured to be completely equal to a target value, thereby reducing the design requirement of the hardware circuit.

An ADC channel delay calibration system based on weak signals, comprising:

weak signal detection module: for extracting and receiving weak signals;

Based on the same inventive concept, the present invention also provides a computer apparatus comprising: one or more processors, and memory for storing one or more computer programs; the program includes program instructions and the processor is configured to execute the program instructions stored in the memory. The processor may be a central processing unit (CentralProcessingUnit, CPU), but may also be other general purpose processors, digital signal processors (DigitalSignalProcessor, DSP), application specific integrated circuits (Application SpecificIntegratedCircuit, ASIC), field-Programmable gate arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., which are the computational cores and control cores of the terminal for implementing one or more instructions, in particular for loading and executing one or more instructions in a computer storage medium to implement the above methods.

It should be further noted that, in this embodiment, the 25MHz clock signal provided by the crystal oscillator is multiplied by a Phase Locked Loop (PLL) chip to become three clocks with deterministic delay relationships, and the three clocks are output to the FPGA chip, the ADC chip and a resistor network respectively by means of ac coupling. One 200MHz clock is output to the FPGA chip; one path of 1GHz clock is used as a sampling clock to be transmitted to the ADC chip; in addition, because the signal amplitude of the other 200MHz clock output by the PLL chip is larger and does not meet the low-amplitude characteristic of weak signals, the clock signal is divided by adopting a resistor network, and then is connected to the analog input of the ADC chip through a 100k omega resistor, so that the amplitude of the clock signal is reduced below the noise level. Thus, a weak 200MHz sinusoidal signal can be detected by a weak detection module in the FPGA chip in a coherent accumulation mode, and then the channel delay is accurately calculated through a sinusoidal four-parameter fitting algorithm. According to the channel delay, the phase of the sampling clock of the ADC can be adjusted, and the sampling data can be buffered and delayed, so that the delay of the ADC channel is adjusted. Because the input and the extraction of the weak signals can be performed in real time, the delay of the ADC channel can be calibrated in real time, and the correction of the delay of the ADC channel can also be performed in real time. Before the method of the embodiment of the invention is not applied, each time the data transmission channel between the ADC and the FPGA is reestablished, the data transmission delay between the ADC and the FPGA chip has a certain probability to change within hundreds of ns, and the change of the delay of the ADC channel can be controlled within 1ns by the method of the embodiment.

It should be noted that, as shown in fig. 3, at the analog signal input ports of the two channels, the analog signals are respectively overlapped with the same weak signal, and the time difference of the weak signal reaching the two ports is negligible. After a transmission delay of 10ns, the signal of the channel 1 is sent into an ADC for sampling, and the sampled data is sent into a digital processing chip; after a transmission delay of 16.6ns, the signal of the channel 2 is sent to the ADC for sampling, and the sampled data is sent to the digital processing chip. The ADC and the digital processing chip of the two channels are the same, and each digital processing chip calculates the delay value of the channel through weak signals. After comparing the delay values of the two channels, the channel 1 can be used as a reference, and the sampling data of the channel 2 is subjected to corresponding delay buffering processing, so that the time error between the sampling data of the two channels is within one sampling period.

In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing has shown and described the basic principles, principal features, and advantages of the present disclosure. It will be understood by those skilled in the art that the present disclosure is not limited to the embodiments described above, which have been described in the foregoing and description merely illustrates the principles of the disclosure, and that various changes and modifications may be made therein without departing from the spirit and scope of the disclosure, which is defined in the appended claims.

Claims

1. The ADC channel delay calibration method based on the weak signal is characterized by comprising the following steps of:

2. The method for calibrating the ADC channel delay based on the weak signal according to claim 1, wherein when the calibration accuracy of the ADC channel delay is high, the weak signal input into the ADC together with the analog signal to be tested is a sine signal.

3. The method for calibrating ADC channel delay based on weak signals according to claim 1, wherein the weak signals have small amplitude, and can be in the same amplitude level with noise components in analog signals to be tested or have amplitude smaller than the noise components.

4. The method for calibrating the delay of the ADC channel based on the weak signal according to claim 2, wherein the ADC channel receives ADC sampling data by using a weak signal detection module in a digital processing chip.

5. The method for calibrating ADC channel delay based on weak signals according to claim 1, wherein the method for extracting weak signals is as follows:

setting the sampling rate of the ADC to be M/N times of the repetition frequency of the weak signal, sampling M points of the weak signal in every N periods, wherein M and N are integers of mutual quality, forming the sampling points into the weak signal in one period, sampling A group data in every K groups, K being integer times of M, A being a positive integer, and the sampling point serial number of each group being i=1, 2, and accumulating the sampling points with the same serial number in every group to finally obtain an accumulated sum waveform containing K data.

6. The method for calibrating the delay of the ADC channel based on the weak signal according to claim 1, wherein the process of calculating the delay of the ADC channel is as follows:

fitting the accumulated sum waveform to obtain the position of a certain characteristic edge of the waveform in the accumulated sum waveform, setting the sampling period of the ADC as Ts, setting the characteristic edge obtained by fitting at the X-th point of the accumulated sum waveform, and setting the sampling rate of the ADC as M/N times of the weak signal repetition frequency, wherein the delay of an ADC channel is (XTs/N+C), wherein C is a constant and can be obtained by calibration in advance.

7. The method for calibrating ADC channel delay based on weak signals according to claim 5, wherein when A is large enough, the components corresponding to the weak signals in the accumulated sum waveform become obvious, and the phase of the accumulated sum waveform has a deterministic relationship with the phase of the weak signals.

8. The method for calibrating ADC channel delay based on weak signals according to claim 1, wherein two or more ADC channels are delay calibrated, and when the delay values of the channels are different, the sampled data can be delay aligned according to the calibrated delay values.

9. An ADC channel delay calibration system based on weak signals, comprising:

weak signal detection module: for extracting and receiving weak signals;

10. An apparatus, comprising:

one or more processors;

a memory for storing one or more programs;

when one or more of the programs are executed by one or more of the processors, the one or more of the processors implement a weak signal based ADC channel delay calibration method according to any one of claims 1-8.