CN116193138B - Data processing system, electronic component and electronic equipment - Google Patents
Data processing system, electronic component and electronic equipment Download PDFInfo
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- CN116193138B CN116193138B CN202310429670.4A CN202310429670A CN116193138B CN 116193138 B CN116193138 B CN 116193138B CN 202310429670 A CN202310429670 A CN 202310429670A CN 116193138 B CN116193138 B CN 116193138B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0105—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level using a storage device with different write and read speed
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
Abstract
The present disclosure provides a data processing system, an electronic component, and an electronic device, which aim to reduce the pressure of decoded data on bandwidth. In this disclosure, a data processing system includes an interface module and a control module, where the interface module is configured to, after receiving decoded data output by a decoder through a first data channel, transmit the decoded data to a memory through a second data channel if the decoded data is not the first data, send the decoded data to a compression module to compress if the decoded data is the first data, set a first indication signal value to a first preset value in a last clock cycle, and not transmit the decoded data through the second data channel in the last clock cycle. And the control module is used for transmitting compressed data to the memory through the second data channel when the first indication signal value is detected to be a first preset value, wherein the compressed data is decoded data compressed by the compression module.
Description
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a data processing system, an electronic component, and an electronic device.
Background
As the display format goes from 1080P to 4K to 8K, the decoded image data puts a great strain on the bandwidth. Taking a video playing scene as an example, after a video decoder in the SoC chip decodes the image data, the decoded data obtained by decoding is stored in a GDDR (graphics double data rate) memory through a bus, and a display controller DC (display controller) in the SoC chip reads the data from the GDDR memory through the bus and displays the data. In the video playing process, the data volume of the decoded data is large, and a large pressure is caused on the bandwidth.
Disclosure of Invention
It is an object of the present disclosure to provide a data processing system, an electronic component and an electronic device, which aim to reduce the bandwidth stress of decoded data.
According to one aspect of the present disclosure, there is provided a data processing system comprising an interface module and a control module;
the interface module is used for judging whether the decoded data is first data or not after receiving the decoded data output by the decoder through the first data channel;
the interface module is further configured to transmit the decoded data to a memory through a second data channel if the decoded data is not the first data;
The interface module is further configured to send the decoded data to the compression module for compression when the decoded data is first data, set a first indication signal value to a first preset value in the last N clock cycles, and not transmit the decoded data through the second data channel in the last M clock cycles;
and the control module is used for transmitting compressed data to the memory through the second data channel when the first indication signal value is detected to be a first preset value, wherein the compressed data is decoded data compressed by the compression module.
In one possible implementation of the present disclosure, the first data is decoded data that is not compressed by the decoder.
In a possible implementation manner of the present disclosure, the interface module is further configured to determine, after receiving address information of the decoded data through the first address channel, whether the address information is address information of the first data;
the interface module is further configured to transmit the address information to the memory through a second address channel if the address information is not the address information of the first data;
the interface module is further configured to send the address information to the control module when the address information is of the first data, set a second indicator signal value to a second preset value in the last P clock cycles, and not transmit the address information through the second address channel in the last Q clock cycles;
And the control module is further used for transmitting the address information to the memory through the second address channel when the second indication signal value is detected to be a second preset value.
In a possible implementation manner of the present disclosure, when the interface module sends the address information to the control module, the interface module is specifically configured to: and when the compression module outputs the compressed data corresponding to the address information to the control module, the compression module outputs the address information to the control module.
In a possible implementation manner of the present disclosure, when the interface module determines whether the address information is the address information of the first data, the interface module is specifically configured to determine, according to a transaction ID carried by the address information, whether the address information is the address information of the first data;
the interface module is specifically configured to determine whether the decoded data is first data according to a transaction ID carried by address information corresponding to the decoded data when determining whether the decoded data is first data.
In a possible implementation manner of the present disclosure, the interface module is further configured to set a first count signal value to a first counter value and update the first counter value when the decoded data is first data;
the interface module is further configured to set a second count signal value to a second counter value and update the second counter value when the address information is address information of the first data;
wherein, the first counter value and the second counter value corresponding to the same pair of decoding data and address information are matched; for the same pair of compressed data and address information, a first count signal value of the control module when transmitting the compressed data through the second data channel is matched with a second count signal value of the control module when transmitting the address information through the second address channel.
In a possible implementation manner of the present disclosure, the control module is specifically configured to, when transmitting compressed data to the memory through the second data channel:
when address information corresponding to the compressed data is transmitted to the memory through the second address channel and the first indication signal value is detected to be a first preset value, judging whether the current first count signal value is equal to a pre-stored second count signal value, if so, transmitting the compressed data to the memory through the second data channel;
Wherein, the pre-stored second count signal value refers to: and a second count signal value when address information corresponding to the compressed data is transmitted through the second address channel.
In a possible implementation manner of the present disclosure, the control module is further specifically configured to, when transmitting compressed data to the memory through the second data channel:
and judging whether the current first count signal value is greater than or equal to the current second count signal value or not under the condition that the address information corresponding to the compressed data is not transmitted to the memory through the second address channel and the first indication signal value is detected to be a first preset value, and if so, transmitting the compressed data to the memory through the second data channel and storing the current first count signal value.
In a possible implementation manner of the present disclosure, when the control module transmits address information to the memory through the second address channel, the control module is specifically configured to:
and judging whether the current second count signal value is greater than or equal to the current first count signal value or not under the condition that the compressed data corresponding to the address information is not transmitted to the memory through the second data channel and the second indication signal value is detected to be a second preset value, if so, transmitting the address information to the memory through the second address channel and storing the current second count signal value.
In a possible implementation manner of the present disclosure, when the control module transmits address information to the memory through the second address channel, the control module is further specifically configured to:
judging whether the current second count signal value is equal to a pre-stored first count signal value or not under the condition that compressed data corresponding to the address information is transmitted to the memory through the second data channel and the second indication signal value is detected to be a second preset value, and if yes, transmitting the address information to the memory through the second address channel; wherein, the pre-stored first count signal value refers to: and a first count signal value when compressed data corresponding to the address information is transmitted through the second data channel.
In one possible implementation manner of the present disclosure, the control module is further configured to store the compressed data output by the compression module and address information corresponding to the compressed data to a first FIFO queue;
the control module is specifically configured to, when transmitting compressed data to the memory through the second data channel:
judging whether the current first count signal value is greater than or equal to the current second count signal value under the condition that the legacy compressed data and the legacy address information are not present and the first indication signal value is detected to be a first preset value, if so, transmitting all the compressed data which are not transmitted yet to the memory through the second data channel, and storing the current first count signal value; wherein, the legacy compressed data refers to: compressed data of which corresponding address information has been transferred to the memory through the second address channel, the legacy address information referring to: address information that the corresponding compressed data has been transferred to the memory via the second data channel.
In one possible implementation manner of the present disclosure, the control module is further configured to store the compressed data output by the compression module and address information corresponding to the compressed data to a first FIFO queue;
the control module is specifically configured to, when transmitting address information to the memory through the second address channel:
judging whether the current second count signal value is greater than or equal to the current first count signal value or not under the condition that the legacy compressed data and the legacy address information are not present and the second instruction signal value is detected to be a second preset value, if yes, transmitting all address information which is not transmitted yet to the memory through the second address channel, and storing the current second count signal value; wherein, the legacy compressed data refers to: compressed data of which corresponding address information has been transferred to the memory through the second address channel, the legacy address information referring to: address information that the corresponding compressed data has been transferred to the memory via the second data channel.
In one possible implementation of the present disclosure, the first data channel and the second data channel are both AXI bus protocol-based data channels; the decoded data further includes second data;
The interface module comprises a second FIFO queue and an ID storage unit; the second FIFO queue is configured to store a transaction ID corresponding to the second data sent by the decoder; the ID storage unit is used for storing the transaction ID carried by the writing response information sent by the memory;
the interface module is further configured to return, when a first transaction ID in the second FIFO queue is equal to any one transaction ID stored in the ID storage unit, the first transaction ID in the second FIFO queue to the decoder, and delete a corresponding transaction ID stored in the ID storage unit.
According to another aspect of the present disclosure, there is also provided an electronic assembly comprising a data processing system as described in any one of the embodiments above. In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.
According to another aspect of the present disclosure, there is also provided an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.
Drawings
FIG. 1 is a schematic diagram of a data processing system provided by an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a compressed data transmission flow provided in an embodiment of the present disclosure;
fig. 3 is a schematic diagram of an address information transmission flow provided in an embodiment of the disclosure;
FIG. 4 is a schematic diagram of the transmission of compressed data and address information provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of the transmission of compressed data and address information provided by an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an interface module provided by an embodiment of the present disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
As the display format goes from 1080P to 4K to 8K, the decoded image data puts a great strain on the system. In order to reduce the pressure of the decoded data on the bandwidth, the inventor of the present disclosure thinks that a compression module is connected to the output end of the decoder, and the data output by the decoder is compressed by using the compression module, so that the size of the decoded data is effectively compressed, and the pressure of the decoded data on the bandwidth is reduced. However, in practical implementation, the inventor has found that the actual situation is relatively complex, and mainly, only a part of the decoded data output by the decoder may need to be compressed. Taking a video decoder as an example, the decoded data output after the video decoder decodes the video file includes data of an image frame and data of a reference frame, wherein the data of the reference frame has been compressed by the video decoder, and the data of the image frame has not been compressed by the video decoder, so that only the data of the image frame needs to be compressed. Therefore, how to reduce the pressure of decoded data on the system bandwidth in such a complex situation is a problem to be solved.
Based on the above situation, the present inventors provide a data processing system, an electronic component, and an electronic device through the following embodiments, with the objective of reducing the pressure of decoded data on the system bandwidth under the above-mentioned complex situation.
With reference to FIG. 1, FIG. 1 is a schematic diagram of a data processing system provided by an embodiment of the present disclosure, as shown in FIG. 1, the data processing system includes an interface module and a control module.
The interface module is used for judging whether the decoded data is the first data after receiving the decoded data output by the decoder through the first data channel.
The interface module is further configured to transmit the decoded data to the memory via the second data channel in the event that the decoded data is not the first data.
The interface module is further configured to send the decoded data to the compression module for compression if the decoded data is the first data, set the first indication signal value to a first preset value in the last N clock cycles, and not transmit the decoded data through the second data channel in the last M clock cycles.
And the control module is used for transmitting compressed data to the memory through the second data channel when the first indication signal value is detected to be a first preset value, wherein the compressed data is the decoded data compressed by the compression module.
In the disclosure, after receiving current decoded data output by a decoder through a first data channel, an interface module determines whether the decoded data is first data that needs to be compressed. If the decoded data is not the first data, the interface module immediately places the decoded data into the second data channel, thereby transferring the decoded data to the memory via the second data channel. If the decoded data is the first data, the interface module will not put the decoded data into the second data channel, but send the decoded data to the compression module for compression processing, in addition, the interface module will not put the decoded data into the second data channel in the next M clock cycles, and set the first indication signal value WV to the first preset value in the next N clock cycles, so that the control module is prompted to idle the current second data channel by the first indication signal value WV. Wherein, M and N are positive integers greater than or equal to 1, M and N can be equal or unequal, and M and N can be configured as 1 for improving the bus utilization.
When the control module detects that the first indication signal value WV is a first preset value, the current second data channel is idle, and then the control module puts the compressed data (namely, the data formed after the first data is compressed) output by the compression module into the second data channel, so that the compressed data is transmitted to the memory through the second data channel.
The data processing system processes the decoded data output by the decoder, so that first data in the decoded data can be sent to the compression module for compression processing, and other decoded data in the decoded data can be normally transmitted to the memory through the second data channel. In addition, when the second data channel is idle, the compressed data formed by compression can be put into the second data channel, so that transmission conflict between the compressed data and other decoding data is avoided, and the compressed data can be transmitted to the memory. In summary, the present disclosure is able to reduce the bandwidth stress of decoded data in the above-described complex situations.
In this disclosure, setting the first indication signal value WV to a first preset value may specifically refer to: and pulling the first indication signal value WV high, wherein the pulled first indication signal value WV indicates that the current second data channel is idle. Alternatively, it may specifically refer to: the first indication signal value WV is pulled down, and the pulled down first indication signal value WV indicates that the current second data channel is idle.
In the present disclosure, the first data channel is a data channel connecting the decoder and the interface module, and the decoder transmits decoded data to the interface module through the first data channel. The decoded data refers to data obtained after the decoder decodes the source file. The second data channel is a data channel connecting the interface module and the memory, the interface module sends decoding data except the first data to the memory through the second data channel, and the control module sends compressed data to the memory through the second data channel when the second data channel is idle.
In some embodiments, the first data channel and the second data channel are two independent data channels, the master device master corresponding to the first data channel is a decoder, the slave device slave corresponding to the first data channel is an interface module, the master device master corresponding to the second data channel is an interface module, and the slave device slave corresponding to the second data channel is a memory.
In other embodiments, the first data channel and the second data channel are two virtual channels defined for the sake of more clear description of the present disclosure, where the first data channel and the second data channel together form an actual data channel, the first data channel is a first segment of the actual data channel, the second data channel is a second segment of the actual data channel, the master of the actual data channel is a decoder, and the slave of the actual data channel is a memory.
In the present disclosure, the first data is decoded data that is not compressed by the decoder. For example, the first data may be image frame data output by a video decoder.
In some embodiments, as shown in fig. 1, the interface module is further configured to determine, after receiving the address information of the decoded data through the first address channel, whether the address information is the address information of the first data.
The interface module is further configured to transmit the address information to the memory through the second address channel if the address information is not the address information of the first data.
The interface module is further configured to send the address information to the control module when the address information is the address information of the first data, set the second indication signal value to a second preset value in the last P clock cycles, and not transmit the address information through the second address channel in the last Q clock cycles.
The control module is further configured to transmit address information to the memory through the second address channel when the second indication signal value is detected to be a second preset value.
In the disclosure, after receiving current address information output by a decoder through a first address channel, an interface module judges whether the address information is address information corresponding to first data. If the address information is not the address information corresponding to the first data, the interface module immediately puts the address information into the second address channel, so that the address information is transmitted to the memory through the second address channel. If the address information is the address information corresponding to the first data, the interface module does not put the address information into the second address channel, but sends the address information to the control module, in addition, the interface module does not put the address information into the second address channel in the next Q clock cycles, and sets the second indication signal value AWV to a second preset value in the next P clock cycles, so that the control module is prompted to be idle in the current second address channel by the second indication signal value AWV. Wherein, P and Q are positive integers greater than or equal to 1, P and Q can be equal or unequal, and P and Q can be configured as 1 for improving bus utilization.
When the control module detects that the second indication signal value AWV is a second preset value, the current second address channel is idle, and then the control module puts the address information into the second address channel, so that the address information is transmitted to the memory through the second address channel.
In the present disclosure, the address information is transmitted to the memory through the above-mentioned data processing system, so that the memory can store corresponding decoded data and compressed data according to the received address information. And according to the second indication signal value AWV, the address information corresponding to the compressed data is transmitted when the second address channel is idle, so that the transmission conflict of the address information can be avoided.
In this disclosure, setting the second indication signal value AWV to a second preset value may specifically refer to: and pulling the second indication signal value AWV high, wherein the pulled second indication signal value AWV indicates that the current second address channel is idle. Alternatively, it may specifically refer to: and pulling down the second indication signal value AWV, wherein the pulled-down second indication signal value AWV indicates that the current second address channel is idle.
In some embodiments, as shown in fig. 1, when the interface module sends address information to the control module, the interface module is specifically configured to: and when the compression module outputs the compressed data corresponding to the address information to the control module, the address information is output to the control module at the same time.
In the disclosure, when an interface module receives first data from a first data channel and receives address information corresponding to the first data from a first address channel, the interface module simultaneously sends the first data and the first information to a compression module. After receiving a pair of first data and address information, the compression module compresses only the first data, thereby obtaining compressed data, and then outputs the compressed data and the address information to the control module at the same time.
The sending of the first data and the address information to the compression module simultaneously may mean that the first data and the address information are sent to the compression module simultaneously in the same clock cycle, or that the first data and the address information are sent to the compression module sequentially in adjacent clock cycles, which is not limited in the disclosure. Likewise, the compression module outputs both compressed data and address information, which is also understood in a similar manner and is not limiting of the present disclosure.
In some embodiments, when determining whether the address information is the address information of the first data, the interface module is specifically configured to determine whether the address information is the address information of the first data according to the transaction ID carried by the address information. The interface module is specifically configured to determine whether the decoded data is the first data according to the transaction ID carried by the address information corresponding to the decoded data when determining whether the decoded data is the first data.
In particular implementations, the decoder may send out the decoded data and the address information in a burst (burst) transmission mechanism based on the AXI4.0 bus protocol, where each burst corresponds to one of the decoded data. The decoder transmits the first address and control information corresponding to burst through the first address channel, wherein the control information includes but is not limited to burst length, burst size and burst transmission type. The decoder transmits data to be transmitted (i.e., decoded data) corresponding to burst through the first data channel. In the AXI4.0 bus protocol, the first address channel also carries a transaction ID (i.e., AWID) when transmitting the head address and control information.
In the present disclosure, the decoder may be configured in advance such that the decoder uses a first preset AWID when transmitting first data, and uses a second preset AWID when transmitting other decoded data (i.e., decoded data other than the first data, such as second data). After receiving the address information (i.e. the first address) through the first address channel, the interface module judges whether the AWID carried by the address information is a first preset AWID, if so, the interface module determines that the address information is the address information corresponding to the first data. When the interface module determines that the currently received address information is address information corresponding to first data, the interface module may determine decoding data corresponding to the address information as the first data.
In the AXI4.0 bus protocol, when the first data channel transmits data, after the first data channel transmits all data corresponding to one burst, a last identifier indicates that all data of the current burst is transmitted. Therefore, in the present disclosure, the interface module may determine what burst is the current burst (i.e., determine what decoding data is the current decoding data) by counting the last identifier, and may determine what address information is the current address information by counting the AWID, and further determine the decoding data corresponding to the address information by comparing the count values. It should be noted that the foregoing manner is merely an example, and the present disclosure may also determine the decoded data corresponding to the address information (or determine the address information corresponding to the decoded data) in a manner, and is not limited to how to determine the decoded data corresponding to the address information (or determine the address information corresponding to the decoded data).
Alternatively, in particular implementations, the decoder may send out the decoded data and address information in a burst (burst) transmission scheme based on the AXI3.0 bus protocol, one for each burst. The decoder transmits the first address and control information corresponding to burst through the first address channel, wherein the control information includes but is not limited to burst length, burst size and burst transmission type. The decoder transmits data to be transmitted (i.e., decoded data) corresponding to burst through the first data channel. In the AXI3.0 bus protocol, the first address channel also carries a transaction ID (i.e., AWID) when transmitting the first address and control information, and the first data channel also carries a transaction ID (i.e., WID) when transmitting data. And in the AXI3.0 bus protocol, the WID carried by the data is equal to the AWID carried by the address information of the data.
In the present disclosure, the decoder may be configured in advance such that the decoder uses a first preset ID when transmitting first data, and uses a second preset ID when transmitting other decoded data (i.e., decoded data other than the first data, such as second data). And after receiving the decoding data through the first data channel, the interface module judges whether the WID carried by the decoding data is a first preset ID, and if so, determines that the decoding data is first data. After receiving the address information (i.e. the first address) through the first address channel, the interface module judges whether the AWID carried by the address information is a first preset ID, if so, determines that the address information is the address information corresponding to the first data. In addition, the interface module may also determine the decoded data corresponding to the address information (or determine the address information corresponding to the decoded data) by comparing the WID and the AWID.
In some embodiments, the interface module is further configured to set the first count signal value to a first counter value and update the first counter value if the decoded data is the first data.
The interface module is further configured to set the second count signal value to a second counter value and update the second counter value if the address information is the address information of the first data.
Wherein the first counter value and the second counter value of the same pair of decoded data and address information are matched. For the same pair of compressed data and address information, a first count signal value of the control module when transmitting the compressed data through the second data channel is matched with a second count signal value of the control module when transmitting the address information through the second address channel.
In this disclosure, the same pair of decoded data and address information can be understood as: if the address information x is the address information of one decoded data y, the decoded data y and the address information x are a pair of decoded data and address information. In the present disclosure, the first counter value and the second counter value are matched, specifically referring to: the first counter value and the second counter value satisfy a certain functional relationship, such as the first counter value being equal to the second counter value, or such as 4 times the first counter value and the second counter value. To simplify the implementation, the first and second counter values that are equal are considered to be matched.
In the present disclosure, after receiving the first data through the first data channel, the interface module sets the first count signal value to the current first counter value, and then updates the first counter value, for example, increases the first counter value by 1. The interface module sets the second count signal value to the current second counter value after receiving the address information of a certain first data through the first address channel, and then updates the second counter value, for example, the second counter value is increased by 1. In the present disclosure, the first counter value and the second counter data may be initialized to 0, and each time the first counter value is updated, the first counter value is incremented by 1, and each time the second counter value is updated, the second counter value is incremented by 1. When the interface module receives the nth first data, the first counter value at the moment is equal to n-1, the interface module sets the first counting signal value to n-1, then adds 1 to the first counter value, and the new first counter value is changed to n. When the interface module receives address information corresponding to the nth first data, the second counter value at the moment is equal to n-1, the interface module sets the second counting signal value to n-1, then adds 1 to the second counter value, and the new second counter value is changed into n. It can be seen that the first counter value and the second counter value corresponding to the nth first data and the address information thereof are equal, and the first data and the address information thereof are matched.
When the control module detects that the current first indication signal value WV is a first preset value, the transmission of the compressed data on the second data channel is controlled according to the current first count signal value Wcounter. Or when the control module detects that the current second indication signal value AWV is a second preset value, controlling the transmission of the address information on the second address channel according to the current second counting signal value AWcounter. For the same pair of compressed data and address information, the first count signal value Wcounter of the control module when transmitting the compressed data through the second data channel is matched with the second count signal value AWcounter of the control module when transmitting the address information through the second address channel. For example, for a certain compressed data and its address information, the first count signal value Wcounter when transmitting the first data through the second data channel is equal to wcounter_n, and the second count signal value awounter when transmitting the address information through the second address channel is equal to awounter_n, which should match awounter_n.
The present disclosure transmits the compressed data and the address information thereof in the above manner, so that the bit times of the compressed data in the second data channel are the same as the corresponding bit times of the address information in the second address channel. For example, for some compressed data and its address information, when the compressed data is transmitted through the second data channel, the compressed data is the p-th data transmitted to the memory by the second data channel, when the address information is transmitted through the second address channel, the address information is the p-th address transmitted to the memory by the second address channel, and when the memory stores the p-th data received by the memory according to the p-th address information received by the memory, the correspondence between the address and the stored data can be ensured.
Referring to fig. 2, fig. 2 is a schematic diagram of a compressed data transmission flow provided in an embodiment of the disclosure. As shown in fig. 2, in some embodiments, the control module, when transmitting compressed data to the memory through the second data channel, is specifically configured to:
when address information corresponding to the compressed data is transmitted to a memory through a second address channel and a first indication signal value is detected to be a first preset value, judging whether the current first count signal value is equal to a pre-stored second count signal value, if so, transmitting the compressed data to the memory through the second data channel, and if not, temporarily not transmitting the compressed data; wherein, the pre-stored second count signal value refers to: a second count signal value when address information corresponding to the compressed data is transmitted through a second address channel;
and judging whether the current first count signal value is greater than or equal to the current second count signal value under the condition that address information corresponding to the compressed data is not transmitted to the memory through the second address channel and the first indication signal value is detected to be the first preset value, if so, transmitting the compressed data to the memory through the second data channel, storing the current first count signal value, and if not, temporarily not transmitting the compressed data.
Referring to fig. 3, fig. 3 is a schematic diagram of an address information transmission flow provided in an embodiment of the disclosure. As shown in fig. 3, the control module is specifically configured to, when transmitting address information to the memory through the second address channel:
when the compressed data corresponding to the address information is not transmitted to the memory through the second data channel and the second indication signal value is detected to be a second preset value, judging whether the current second counting signal value is larger than or equal to the current first counting signal value, if so, transmitting the address information to the memory through the second address channel and storing the current second counting signal value; if not, the address information is not transmitted temporarily;
when the compressed data corresponding to the address information is transmitted to the memory through the second data channel and the second indication signal value is detected to be a second preset value, judging whether the current second counting signal value is equal to the pre-stored first counting signal value, if so, transmitting the address information to the memory through the second address channel, and if not, temporarily not transmitting the address information; the pre-stored first count signal value refers to: a first count signal value when compressed data corresponding to the address information is transmitted through the second data channel.
In particular, referring to fig. 4, fig. 4 is a schematic diagram illustrating transmission of compressed data and address information according to an embodiment of the present disclosure. Illustratively, the control module may have FIFO queues, buffers, and registers disposed therein. Each pair of compressed data and address information output by the compression module is stored in the FIFO queue. The buffer is used for storing legacy compressed data and legacy address information, and the legacy compressed data refers to: the corresponding address information is already transmitted to the compressed data of the memory through the second address channel; legacy address information refers to: the corresponding compressed data has been transferred to the address information of the memory via the second data channel. The register is used for storing a second count signal value AWcounter of address information corresponding to the legacy compressed data when the address information is transmitted and is also used for storing a first count signal value Wcounter of the compressed data corresponding to the legacy address information when the address information is transmitted.
At the first moment, the control module detects that the second indicating signal value AWV is pulled up (i.e. AWV is equal to the second preset value), and reads the current second count signal value AWcounter, where AWcounter is equal to 65. The control module detects that the buffer is currently empty, indicating that no legacy compressed data or legacy address information is currently stored. The control module also detects that the FIFO queue is also currently empty, indicating that both the compressed data and address information previously stored in the FIFO queue have been read out, and that the compression module is compressing the data and has not yet reached the output of the compressed data and address information. At a first time, the control module does not perform a transmission operation.
At the second moment, the control module detects that the first indication signal value WV is pulled high (i.e., WV is equal to the first preset value), and reads the current first count signal value Wcounter, where Wcounter is equal to 58. The control module detects that the buffer is currently empty, indicating that no legacy compressed data or legacy address information is currently stored. The control module detects that the FIFO queue currently has stored a pair of compressed data and address information. The control module also determines that the current first count signal value Wcounter is less than the current second count signal value AWcounter. At a second time, the control module does not perform a transmission operation.
At a third time, the control module detects that the second indication signal value AWV is pulled high, and reads the current second count signal value AWcounter, where AWcounter is equal to 66. The control module detects that the buffer is currently empty, indicating that no legacy compressed data or legacy address information is currently stored. The control module detects that the FIFO queue currently has stored a pair of compressed data and address information. The control module also determines that the current second count signal value AWcounter is greater than the current first count signal value Wcounter. At a third moment, the control module reads the pair of compressed data and the address information from the FIFO queue and puts the address information into a second address channel, so that the address information is transmitted to the memory through the second address channel; the control module also stores the compressed data as legacy compressed data, stores the legacy compressed data to a buffer, and stores the current second count signal value AWcounter (i.e., 66) to a register.
It should be noted that, the states of the FIFO queue, buffer and register at the third time in fig. 4 are the states of the FIFO queue, buffer and register after the control module has performed the transmission operation.
At the fourth moment, the control module detects that the second indicating signal value AWV is pulled high, and reads the current second count signal value AWcounter, and the AWcounter is equal to 67. The control module detects that the buffer currently stores the legacy compressed data, and the control module can continue transmitting the address information after waiting for the legacy compressed data to be transmitted. At the fourth instant, the control module therefore does not perform a transmission operation.
At the fifth moment, the control module detects that the first indication signal value WV is pulled high, and reads the current first count signal value Wcounter, where Wcounter is equal to 59. The control module detects that the buffer currently stores legacy compressed data. The control module reads the second count signal value AWcounter (i.e. 66) stored in the register, determines whether the current first count signal value Wcounter is equal to 66, and at the fifth moment, the control module does not perform the transmission operation because the current first count signal value Wcounter is not equal to 66.
At the nth time, the control module detects that the first indication signal value WV is pulled high, and reads the current first count signal value Wcounter, where Wcounter is equal to 66. The control module detects that the buffer currently stores legacy compressed data. The control module reads the second count signal value AWcounter (i.e. 66) stored in the register, determines whether the current first count signal value Wcounter is equal to 66, and puts the legacy compressed data stored in the buffer into the second data channel at the nth time, so that the legacy compressed data is transferred to the memory through the second data channel, and the buffer is emptied at the moment.
It should be noted that, the states of the FIFO queue, buffer and register at the nth time in fig. 4 are the states of the FIFO queue, buffer and register after the control module has performed the transmission operation.
In the present disclosure, in an initialization stage before a decoder starts decoding, FIFO queues, buffers, and registers in a control module may be emptied in advance.
In some embodiments, the control module, when transferring compressed data to the memory via the second data channel, is specifically configured to: and under the condition that the legacy compressed data and the legacy address information are not present, and the condition that the first indication signal value is a first preset value is detected, judging whether the current first count signal value is greater than or equal to the current second count signal value, if so, transmitting all the compressed data which are not transmitted yet to a memory through a second data channel, storing the current first count signal value, and if not, temporarily not transmitting the compressed data.
The control module is specifically configured to, when transmitting address information to the memory through the second address channel: judging whether the current second counting signal value is larger than or equal to the current first counting signal value or not under the condition that the legacy compressed data and the legacy address information are not existed and the second indicating signal value is detected to be a second preset value, if so, transmitting all address information which is not transmitted yet to a memory through a second address channel and storing the current second counting signal value; if not, the address information is not transmitted temporarily.
Wherein, legacy compressed data refers to: the corresponding address information is compressed data which has been transferred to the memory through the second address channel, and the legacy address information refers to: the corresponding compressed data has been transferred to the address information of the memory via the second data channel.
In specific implementation, referring to fig. 5, fig. 5 is a schematic diagram illustrating transmission of compressed data and address information according to an embodiment of the present disclosure. Illustratively, the control module may have FIFO queues, buffers, and registers disposed therein. Each pair of compressed data and address information output by the compression module is stored in the FIFO queue. The buffer is used for storing the legacy compressed data and the legacy address information. The register is used for storing a second count signal value AWcounter of address information corresponding to the legacy compressed data when the address information is transmitted and is also used for storing a first count signal value Wcounter of the compressed data corresponding to the legacy address information when the address information is transmitted.
At time n+1, the control module detects that the second indication signal value AWV is pulled high, and reads the current second count signal value AWcounter, and the AWcounter is equal to 81. The control module detects that the buffer is currently empty, indicating that no legacy compressed data or legacy address information is currently stored. The control module detects that the FIFO queue currently has stored three pairs of compressed data and address information. The control module also determines that the current second count signal value AWcounter is greater than the current first count signal value Wcounter. At the (n+1) th moment, the control module reads out three pairs of compressed data and address information stored in the FIFO queue, and sequentially puts each address information into the second address channel according to the storage sequence of the three address information in the FIFO queue, so that the three address information is sequentially transmitted through the second address channel; the control module also takes the three compressed data as three legacy compressed data, and stores the three legacy compressed data into the buffer according to the storage sequence of the three compressed data in the FIFO queue; the control module also stores the current second count signal value AWcounter (i.e. 81) to a register.
It should be noted that, the states of the FIFO queue, buffer and register at the n+1 time in fig. 5 are the states of the FIFO queue, buffer and register after the control module has performed the transmission operation.
At time n+2, the control module detects that the second indication signal value WV is pulled high, and reads the current first count signal value Wcounter, where Wcounter is equal to 67. The control module detects that the buffer currently stores legacy compressed data. The control module reads the second count signal value AWcounter (i.e. 81) stored in the register, determines whether the current first count signal value Wcounter is equal to 81, and does not perform the transmission operation at the n+2th time since the current first count signal value Wcounter is not equal to 81.
At time n+3, the control module detects that the second indication signal value AWV is pulled high, and reads the current second count signal value AWcounter, where AWcounter is equal to 82. The control module detects that the buffer currently stores the legacy compressed data, and the control module can continue transmitting the address information after waiting for the legacy compressed data to be transmitted. So at time n+3, the control module does not perform a transfer operation.
At time n+m, the control module detects that the second indication signal value WV is pulled high, and reads the current first count signal value Wcounter, where Wcounter is equal to 81. The control module detects that the buffer currently stores legacy compressed data. The control module reads the second count signal value AWcounter (i.e. 81) stored in the register, judges whether the current first count signal value Wcounter is equal to 81, and at the n+m time, the control module sequentially puts all the legacy compressed data stored in the buffer into the second data channel according to the storage sequence of the legacy compressed data in the buffer, so that the legacy compressed data is sequentially transmitted through the second data channel, and the buffer is emptied at the moment.
It should be noted that, the states of the FIFO queue, buffer and register at the n+m time in fig. 5 are the states of the FIFO queue, buffer and register after the control module has performed the transmission operation.
In the present disclosure, in an initialization stage before a decoder starts decoding, FIFO queues, buffers, and registers in a control module may be emptied in advance.
In some embodiments, the first data channel and the second data channel are both AXI bus protocol based data channels. The decoded data also includes second data, which may be, for example, reference frame data output by the video decoder.
The interface module comprises a second FIFO queue and an ID storage unit; a second FIFO queue for storing transaction IDs corresponding to the second data sent by the decoder; and the ID storage unit is used for storing the transaction ID carried by the writing response information sent by the memory.
The interface module is further configured to return the first transaction ID in the second FIFO queue to the decoder and delete the corresponding transaction ID stored in the ID storage unit, if the first transaction ID in the second FIFO queue is equal to any one of the transaction IDs stored in the ID storage unit.
In the present disclosure, the decoder outputs data based on the AXI bus protocol, and in order to meet the order-preserving requirements in the AXI bus protocol, the interface module needs to return a write response to the decoder in the original order. And when the interface module receives a burst corresponding to the second data, storing the transaction ID corresponding to the burst into a second FIFO queue, so that the sequence of the transaction IDs is recorded by using the second FIFO queue, and meanwhile, the order-preserving requirement of the write response is ensured by using the first-in-first-out principle of the second FIFO queue.
Referring to fig. 6, fig. 6 is a schematic diagram of an interface module provided by an embodiment of the present disclosure. As shown in fig. 6, the interface module includes a second FIFO queue and a plurality of ID storage units. Each ID storage unit comprises a null indication field, an ID field and an ID number field, wherein the null indication field is used for indicating whether the current ID storage unit is null, the ID field is used for indicating the IDs stored in the current ID storage unit, and the ID number field is used for indicating the number of corresponding IDs.
And each time the interface module receives a burst corresponding to the second data, storing the transaction ID (namely AWID) corresponding to the burst into the second FIFO queue.
In addition, after receiving a write response returned by the memory, the interface module acquires a transaction ID (i.e., BID) carried by the write response, and then determines whether the BID is equal to a first AWID (i.e., a first stored AWID) in the second FIFO queue. If the two are equal, the first AWID in the second FIFO queue is fetched, and a write response corresponding to the AWID is sent to a decoder.
If the two are not equal, comparing the BID with the ID field of each non-empty ID storage unit; if the BID is equal to the ID field of a certain ID storage unit, adding 1 to the ID number field of the ID storage unit; if the BID is not equal to the ID fields of all the ID storage units, an empty ID storage unit is allocated to the BID, the ID field of the ID storage unit is set to the BID, the ID number field of the ID storage unit is set to 1, and finally the empty indication field of the ID storage unit is updated to indicate that the ID storage unit is currently not empty.
In addition, after the second FIFO queue fetches the first AWID each time, the remaining AWIDs in the second FIFO queue are shifted forward by one bit, thereby making the original second AWID the new first AWID. The new first AWID is compared with the ID field of each non-empty ID storage unit; if the first AWID is equal to the ID field of a certain ID storage unit, the first AWID in the second FIFO queue is fetched, and a write response corresponding to the AWID is sent to a decoder. The remaining AWIDs in the second FIFO queue are then all shifted forward by one bit, and so on.
Further, each time the second FIFO queue fetches the first AWID, the ID number field of the ID storage unit corresponding to the AWID is decremented by 1. If the number of IDs field after 1 reduction becomes 0, the empty indication field of the ID storage unit is updated to indicate that the ID storage unit is currently empty. Wherein, the AWID corresponds to the ID storage unit, specifically: an AWID corresponds to an ID storage unit if the AWID is equal to the ID field of the ID storage unit.
In some embodiments, the interface module may also perform status detection periodically or aperiodically. When the state detection is carried out, the interface module adds the ID number fields of all the non-empty ID storage units to obtain an addition result, then detects whether the depth of the second FIFO queue is larger than the addition result, if not, sets a corresponding error register, and sends out error interrupt.
The disclosed embodiments also provide an electronic assembly comprising a data processing system as described in any of the embodiments above. In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.
The embodiment of the disclosure also provides electronic equipment, which comprises the electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, game console, workstation, server, etc.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (15)
1. A data processing system, the system comprising an interface module and a control module;
the interface module is used for judging whether the decoded data is first data or not after receiving the decoded data output by the decoder through the first data channel;
the interface module is further configured to transmit the decoded data to a memory through a second data channel if the decoded data is not the first data;
the interface module is further configured to send the decoded data to the compression module for compression when the decoded data is first data, set a first indication signal value to a first preset value in the last N clock cycles, and not transmit the decoded data through the second data channel in the last M clock cycles;
and the control module is used for transmitting compressed data to the memory through the second data channel when the first indication signal value is detected to be a first preset value, wherein the compressed data is decoded data compressed by the compression module.
2. The data processing system of claim 1, the first data being decoded data that has not been compressed by the decoder.
3. The data processing system of claim 1, the interface module further configured to determine, after receiving address information of the decoded data via the first address channel, whether the address information is address information of the first data;
the interface module is further configured to transmit the address information to the memory through a second address channel if the address information is not the address information of the first data;
the interface module is further configured to send the address information to the control module when the address information is of the first data, set a second indicator signal value to a second preset value in the last P clock cycles, and not transmit the address information through the second address channel in the last Q clock cycles;
and the control module is further used for transmitting the address information to the memory through the second address channel when the second indication signal value is detected to be a second preset value.
4. A data processing system according to claim 3, wherein when the interface module sends the address information to the control module, the interface module is specifically configured to: and when the compression module outputs the compressed data corresponding to the address information to the control module, the compression module outputs the address information to the control module.
5. The data processing system according to claim 3, wherein the interface module is specifically configured to determine whether the address information is of the first data according to a transaction ID carried by the address information when determining whether the address information is of the first data;
the interface module is specifically configured to determine whether the decoded data is first data according to a transaction ID carried by address information corresponding to the decoded data when determining whether the decoded data is first data.
6. A data processing system according to claim 3, the interface module further for setting a first count signal value to a first counter value and updating the first counter value if the decoded data is first data;
the interface module is further configured to set a second count signal value to a second counter value and update the second counter value when the address information is address information of the first data;
wherein, the first counter value and the second counter value corresponding to the same pair of decoding data and address information are matched; for the same pair of compressed data and address information, a first count signal value of the control module when transmitting the compressed data through the second data channel is matched with a second count signal value of the control module when transmitting the address information through the second address channel.
7. The data processing system of claim 6, the control module, when transferring compressed data to the memory via the second data channel, is specifically configured to:
when address information corresponding to the compressed data is transmitted to the memory through the second address channel and the first indication signal value is detected to be a first preset value, judging whether the current first count signal value is equal to a pre-stored second count signal value, if so, transmitting the compressed data to the memory through the second data channel;
wherein, the pre-stored second count signal value refers to: and a second count signal value when address information corresponding to the compressed data is transmitted through the second address channel.
8. The data processing system of claim 7, the control module, when transferring compressed data to the memory over the second data channel, is further specifically configured to:
and judging whether the current first count signal value is greater than or equal to the current second count signal value or not under the condition that the address information corresponding to the compressed data is not transmitted to the memory through the second address channel and the first indication signal value is detected to be a first preset value, and if so, transmitting the compressed data to the memory through the second data channel and storing the current first count signal value.
9. The data processing system of claim 6, the control module, when transferring address information to the memory via the second address channel, is specifically configured to:
and judging whether the current second count signal value is greater than or equal to the current first count signal value or not under the condition that the compressed data corresponding to the address information is not transmitted to the memory through the second data channel and the second indication signal value is detected to be a second preset value, if so, transmitting the address information to the memory through the second address channel and storing the current second count signal value.
10. The data processing system of claim 9, the control module, when transferring address information to the memory via the second address channel, is further specifically configured to:
judging whether the current second count signal value is equal to a pre-stored first count signal value or not under the condition that compressed data corresponding to the address information is transmitted to the memory through the second data channel and the second indication signal value is detected to be a second preset value, and if yes, transmitting the address information to the memory through the second address channel; wherein, the pre-stored first count signal value refers to: and a first count signal value when compressed data corresponding to the address information is transmitted through the second data channel.
11. The data processing system of claim 6, wherein the control module is further configured to store the compressed data output by the compression module and address information corresponding to the compressed data to a first FIFO queue;
the control module is specifically configured to, when transmitting compressed data to the memory through the second data channel:
judging whether the current first count signal value is greater than or equal to the current second count signal value under the condition that the legacy compressed data and the legacy address information are not present and the first indication signal value is detected to be a first preset value, if so, transmitting all the compressed data which are not transmitted yet to the memory through the second data channel, and storing the current first count signal value; wherein, the legacy compressed data refers to: compressed data of which corresponding address information has been transferred to the memory through the second address channel, the legacy address information referring to: address information that the corresponding compressed data has been transferred to the memory via the second data channel.
12. The data processing system of claim 6, wherein the control module is further configured to store the compressed data output by the compression module and address information corresponding to the compressed data to a first FIFO queue;
The control module is specifically configured to, when transmitting address information to the memory through the second address channel:
judging whether the current second count signal value is greater than or equal to the current first count signal value or not under the condition that the legacy compressed data and the legacy address information are not present and the second instruction signal value is detected to be a second preset value, if yes, transmitting all address information which is not transmitted yet to the memory through the second address channel, and storing the current second count signal value; wherein, the legacy compressed data refers to: compressed data of which corresponding address information has been transferred to the memory through the second address channel, the legacy address information referring to: address information that the corresponding compressed data has been transferred to the memory via the second data channel.
13. The data processing system of claim 1, the first data channel and the second data channel each being AXI bus protocol based data channels; the decoded data further includes second data;
the interface module comprises a second FIFO queue and an ID storage unit; the second FIFO queue is configured to store a transaction ID corresponding to the second data sent by the decoder; the ID storage unit is used for storing the transaction ID carried by the writing response information sent by the memory;
The interface module is further configured to return, when a first transaction ID in the second FIFO queue is equal to any one transaction ID stored in the ID storage unit, the first transaction ID in the second FIFO queue to the decoder, and delete a corresponding transaction ID stored in the ID storage unit.
14. An electronic assembly comprising the data processing system of any one of claims 1 to 13.
15. An electronic device comprising the electronic assembly of claim 14.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205223B1 (en) * | 1998-03-13 | 2001-03-20 | Cirrus Logic, Inc. | Input data format autodetection systems and methods |
| CN102300060A (en) * | 2010-06-25 | 2011-12-28 | 深圳Tcl新技术有限公司 | Infrared control time-shifting system of television and time-shifting control method thereof |
| CN105659503A (en) * | 2013-10-24 | 2016-06-08 | 高通股份有限公司 | System and method for providing multi-user power saving codebook optimization |
| CN111966281A (en) * | 2019-05-20 | 2020-11-20 | 慧荣科技股份有限公司 | Data storage device and data processing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3680845B2 (en) * | 2003-05-28 | 2005-08-10 | セイコーエプソン株式会社 | Compressed video decompression device and image display device using the same |
| US9106936B2 (en) * | 2012-01-25 | 2015-08-11 | Altera Corporation | Raw format image data processing |
-
2023
- 2023-04-21 CN CN202310429670.4A patent/CN116193138B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205223B1 (en) * | 1998-03-13 | 2001-03-20 | Cirrus Logic, Inc. | Input data format autodetection systems and methods |
| CN102300060A (en) * | 2010-06-25 | 2011-12-28 | 深圳Tcl新技术有限公司 | Infrared control time-shifting system of television and time-shifting control method thereof |
| CN105659503A (en) * | 2013-10-24 | 2016-06-08 | 高通股份有限公司 | System and method for providing multi-user power saving codebook optimization |
| CN111966281A (en) * | 2019-05-20 | 2020-11-20 | 慧荣科技股份有限公司 | Data storage device and data processing method |
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