CN116185745B - Quick soft error detection method for Beidou signal processing complex operation chip - Google Patents

Quick soft error detection method for Beidou signal processing complex operation chip Download PDF

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CN116185745B
CN116185745B CN202310458594.XA CN202310458594A CN116185745B CN 116185745 B CN116185745 B CN 116185745B CN 202310458594 A CN202310458594 A CN 202310458594A CN 116185745 B CN116185745 B CN 116185745B
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CN116185745A (en
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范毓洋
李开泰
王鹏
马振洋
金志威
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Civil Aviation University of China
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

A fast soft error detection method for a Beidou signal processing complex operation chip. It includes constructing a fast soft error detection circuit; obtaining output data; compiling a rule set; obtaining a bit vector array and storing the bit vector array in a processing unit; obtaining an address of a static random access memory; then, theoretical output data and actual output data are sent to a data comparator; and comparing the theoretical output data with actual output data given by the circuit to be tested. The method can be applied to chips containing complex operations such as Beidou signal processing and the like, supports on-line detection of the SEU effect of the chip, and judges whether the chip is in error operation or not. In addition, the detection circuit has high soft error detection speed and small resource occupation, and can rapidly sample and check the chip output result and even the intermediate operation process result under various application scenes, so that the problem that soft errors are difficult to find under complex operation scenes can be solved.

Description

Quick soft error detection method for Beidou signal processing complex operation chip
Technical Field
The invention belongs to the technical field of integrated circuit design and reliability, and particularly relates to a rapid soft error detection method which can be applied to Beidou signal processing and the like and comprises complex operation chips.
Background
With the continuous development of integrated circuit technology and the reduction of the feature size of devices, the power supply voltage of the circuit is reduced, and the scale and the complexity are exponentially increased. Therefore, electronic hardware in the safety fields of aerospace, automobiles, medical treatment and the like is more easily affected by soft errors, particularly SEU (Single Event Upset ) interference, so that potential safety hazards are brought. How to quickly determine whether the output result of an integrated circuit (especially a configurable device) performing complex operations is correct becomes a design focus of attention for high security integrated circuits.
For example, the relevant signal receiving and transmitting process of the airborne Beidou digital signal processing chip involves a large number of complex operations, and the complex operations are easily interfered by SEU, so that soft operation errors are generated, and unexpected security threats (such as positioning errors, navigation errors and the like) are caused, which are unacceptable in the field of high security.
Aiming at the problem of soft error detection, the current hardware level is mainly solved by a circuit redundancy technology or by using check codes; but in certain scenarios are limited by area and cost, or designed code is not easily modified. At this time, a cost-controllable detection scheme is needed, and when a soft error occurs, the soft error can be found and warned with a certain probability, so as to reduce the probability of silence failure of the product.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a fast soft error detection method for a complex operation chip for Beidou signal processing, so as to avoid the adverse effect of soft errors on the operation of a digital circuit without affecting the operation processing speed of the device itself.
In order to achieve the above objective, the rapid soft error detection method for the Beidou signal processing complex operation chip provided by the invention comprises the following steps in sequence:
step 0) constructing a fast soft error detection circuit, wherein the fast soft error detection circuit comprises a fast stream table matching module, a Static Random-Access Memory (SRAM), a counter and a data comparator; wherein the fast flow table matching module comprises a processing unit (Processing Element, PE) and an address decoder;
step 1): according to application scenes of different designs, selecting data with high occurrence frequency and typical characteristics as input data of a quick soft error detection circuit, and obtaining correct output data of the data through theoretical calculation or test simulation;
step 2): storing the output data obtained in the step 1) into an appointed address in a static random access memory, and compiling a rule set on the address in the static random access memory by utilizing the input data and the output data corresponding to the input data;
step (a)3): pre-encoding the output data obtained in step 1) and the rule set obtained in step 2) by using a rule encoder to obtain a Bit Vector (Bit Vector,BV) The array is stored in a processing unit of the fast flow table matching module and is used for subsequent searching matching operation;
step 4): respectively inputting data to be tested into a fast flow table matching module and a circuit to be tested (Device Under Test, DUT); when the data to be tested is a typical data set in advance, the circuit to be tested executes complex operation, the fast flow table matching module directly reads out the corresponding bit vector value from the bit vector array stored in the processing unit obtained in the step 3) according to the matching relation between the data to be tested and the coding rule, and sends the bit vector value into the address decoder, and the address decoder is utilized to decode the bit vector value to obtain the address of the corresponding static random access memory, and the address is used for subsequently reading the data in the static random access memory;
step 5): reading theoretical output data corresponding to the input data to be tested from the static random access memory through the address obtained in the step 4), finishing operation when the circuit to be tested reaches the set value of the counter to obtain actual output data, and then sending the theoretical output data and the actual output data into the data comparator;
step 6): comparing the theoretical output data obtained in the step 5) with the actual output data given by the circuit to be tested by a data comparator, if the theoretical output data is consistent with the actual output data, the data of the circuit to be tested is not affected by soft errors, the actual operation result is reliable, the correct and wrong judgment signal is true, and the final operation result is output; if the data of the circuit to be tested is not consistent, the data is influenced by soft errors, the output result is unreliable, the final operation result is output to be 0, and the correct and wrong judgment signal is false, so that the operation of the circuit to be tested is unreliable.
In step 4), the circuit to be tested is Beidou equipment, airborne electronic hardware or related high-safety field equipment.
In step 5), the method for setting the set value of the counter is as follows: let the search completion time of the fast soft error detection circuit be t 0 The operation completion time of the circuit to be tested is t 1 The difference between them is Δt=t 1 - t 0 The clock cycle number in the difference deltat is used as the set value of the counter.
The method can be applied to chips containing complex operations such as Beidou signal processing and the like, supports on-line detection of the SEU effect of the chip, and judges whether the chip is in error operation or not. In addition, the detection circuit has high soft error detection speed and small resource occupation, and can rapidly sample and check the chip output result and even the intermediate operation process result under various application scenes, so that the problem that soft errors are difficult to find under complex operation scenes can be solved.
Drawings
Fig. 1 is a flowchart of a fast soft error detection method for a Beidou signal processing complex operation chip.
FIG. 2 is a schematic diagram of a conventional devicesThe bit vector array constructs the result when=2.
FIG. 3 is a schematic diagram of a preferred embodiment of the present inventionsBit vector when=2BV 0 And storing a process schematic.
Fig. 4 is a fast flow table matching module port diagram.
Fig. 5 is a processing unit port diagram.
Fig. 6 is an address decoder port diagram.
Fig. 7 is a static random access memory port diagram.
Fig. 8 is a counter port diagram.
Fig. 9 is a data comparator port diagram.
Fig. 10 is a circuit diagram of a fast soft error detection.
Detailed Description
As shown in fig. 1, the rapid soft error detection method for the Beidou signal processing complex operation chip provided by the invention comprises the following steps in sequence:
step 0) constructing a quick soft error detection circuit, wherein the quick soft error detection circuit comprises a quick flow table matching module, a static random access memory, a counter and a data comparator; the fast flow table matching module comprises a processing unit and an address decoder;
step 1): according to the application scenes of Beidou equipment, airborne electronic hardware or related high-safety field equipment, selecting data with high occurrence frequency and typical characteristics in the complex operation process as input data of a quick soft error detection circuit, and acquiring correct output data of the data through theoretical calculation or test simulation;
step 2): storing the output data of the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment obtained in the step 1) into an appointed address in a static random access memory, and compiling a rule set on the address in the static random access memory by utilizing the input data and the output data corresponding to the input data;
step 3): pre-encoding the output data obtained in step 1) and the rule set obtained in step 2) by using a rule encoder to obtain a Bit Vector (Bit Vector,BV) The array is stored in a processing unit of the fast flow table matching module through a Bv_input port and is used for subsequent searching matching operation;
the precoding process is shown in FIG. 2, and is performed by inputting a group of L-bit data according to s-bit (s>1) Split as a subfield, divided into a total of
Figure SMS_1
Sub-field, number->
Figure SMS_2
Wherein the value of each bit is 0 and 1; let->
Figure SMS_3
Represents the->
Figure SMS_4
Subfields, th->
Figure SMS_5
Subfields->
Figure SMS_6
Is s bits in length.
Assuming that there are N coding rules, wherein the value of each coding rule bit is 0,1 and x; * The result of matching 0 and 1 is 1.
To be used for
Figure SMS_7
Bit vector in the example +.>
Figure SMS_10
For example, the stream table contains three coding rules, < >>
Figure SMS_13
、
Figure SMS_9
And->
Figure SMS_12
. When->
Figure SMS_15
，/>
Figure SMS_17
When (I)>
Figure SMS_8
Is "×" matched to 2' b11, encoded as 1; />
Figure SMS_11
Is "01" and 2' b11, and is encoded as 0; />
Figure SMS_14
Is "0 x" matched to 2' b11 and encoded as 1. Thus, bit vector +.>
Figure SMS_16
=“100”
The storage process of the bit vector arrays is shown in fig. 3, in the storage of the bit vector arrays, each bit vector array corresponds to a depth of
Figure SMS_19
A memory with a width of n>
Figure SMS_22
Subfields->
Figure SMS_25
For the corresponding bit vector->
Figure SMS_20
Is a logical address of the host. With bit vector array in FIG. 3->
Figure SMS_23
For example, due to the storage ofs=2, thus bit vector array +.>
Figure SMS_26
Comprises->
Figure SMS_28
A plurality of bit vectors, respectively->
Figure SMS_18
、/>
Figure SMS_21
、/>
Figure SMS_24
And->
Figure SMS_27
Sequentially stored in addresses 00, 01, 10 and 11.
As shown in fig. 4, the input signals of the fast flow table matching module are: the method comprises the steps of searching a bit vector array signal input by a rule encoder, searching a matching start mark input signal and an input signal of data to be detected; the output signal is the address of the static random access memory.
The fast flow table matching module illustrates: clk is a clock, rst is a reset signal, lookup_en is a search enabling signal, when input data need to be judged, lookup_en is set to 1, data_input is input of data to be detected, bv_input is input of a bit vector array acquired by a rule encoder, and Address is an Address output signal of a static random access memory obtained by decoding of an Address decoder.
The processing unit is shown in FIG. 5, the number of sub-field partitions is
Figure SMS_29
Is common->
Figure SMS_30
Each processing unit is capable of processing input data of one subfield, and en_out of the previous processing unit is used as en_in of the next processing unit to form a serial structure.
The processing unit is described as follows: clk is clock, rst is reset signal, en_iniTo match the enable signal, if a subfield starts to match then set to 1, subfield_iniFor inputting a certain subfield of the data to be tested, bv_iniBv_out for bit vector array input to a regular encoderiThe obtained bit vector value for this subfield, en_outiFor the match enable input of the next processing unit, if the subfields processed by that processing unit match errors, en_outiOutputting 0, and stopping the matching operation of the processing unit of the next subfield so as to save the matching time.
The sram is shown in fig. 7, in which various theoretical output data corresponding to the data to be measured are stored.
Static random access memory description: clk is clock, rst is reset signal, address is Address given by Address decoder, data_output is theoretical output found in static random access memory, cnt_en is counter enable given after finding is completed.
Step 4): respectively inputting data to be tested into a rapid flow table matching module, beidou equipment, airborne electronic hardware or related high-safety field equipment; when the data to be detected is a certain typical data set in advance, the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment executes complex operation, the fast flow table matching module directly reads out corresponding bit vector values from the bit vector array stored in the processing unit obtained in the step 3) according to the matching relation between the data to be detected and the coding rule, the bit vector values are sent to an address decoder, the address decoder is utilized to decode the bit vector values to obtain the corresponding addresses of the static random access memories, and the addresses are used for subsequently reading the data in the static random access memories;
when the fast soft error detection circuit operates, the Lookup_en enables to be 1 to start searching operation, and meanwhile, a group of L-bit data to be detected is divided into two paths to be respectively input into the circuit to be detected and the fast flow table matching module to execute complex operation and fast flow table matching operation. When the group of L-bit data to be tested is input into the fast flow table matching module, the module divides the group of L-bit data into a group according to s-bit
Figure SMS_31
Sub-fields. The first subfield is sent to the processing unit 0 through the sub_0, the enabling en_in of the processing unit 0 is set to 1, the bit vector matching operation is started, the obtained bit vector value is output through the Bv_0, the bit vector value is sent to the Address decoder to obtain an Address, and then the Address is input to the static random access memory, and theoretical output data of the subfield is searched and obtained; subsequent fields 2 to +.>
Figure SMS_32
-1 subfield operation is the same. And finally obtaining theoretical output data of the whole data to be tested.
The address decoder is shown in FIG. 6, which can decode the processing unit PEiThe bit vector values of the array outputs are translated into a set of addresses that are used to find the theoretical output data in the sram.
Address decoder description: clk is a clock, rst is a reset signal, en_out is a decode enable signal output from a processing unit, bv_out is a bit vector value obtained from a certain processing unit, and Address is an Address pointing to a static random access memory.
Step 5): reading theoretical output data corresponding to the input data to be tested from the static random access memory through the address obtained in the step 4), finishing operation to obtain actual output data when the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment reaches the set value of the counter, and then sending the theoretical output data and the actual output data into the data comparator;
the data comparator in the step is provided with two groups of data input signals, one group of data is derived from the output data stored in the static random access memory in the step 2), and the other group of data is derived from the actual output data after the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment in the step 5) completes operation. The output signals comprise reset signals, detection positive and negative judgment signals and final operation results.
Because the speed of acquiring theoretical output data by the fast soft error detection circuit is usually faster than the speed of executing complex operation by Beidou equipment, airborne electronic hardware or related high-safety field equipment, a counter is arranged, and the searching completion time of the fast soft error detection circuit is set as t 0 The calculation completion time of Beidou equipment, airborne electronic hardware or related high-safety field equipment is t 1 The difference between them is Δt=t 1 - t 0 The clock cycle number in the difference delta t is taken as a set value of the counter, and when the count value reaches the set value, a comparison enable signal Compare_en is output to the data comparator.
Step 6): comparing the theoretical output data obtained in the step 5) with actual output data given by Beidou equipment, airborne electronic hardware or related high-safety field equipment by a data comparator, if the theoretical output data are consistent, the data of the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment are not affected by soft errors, the actual operation result is reliable, a correct and incorrect judgment signal is true, and a final operation result is output; if the data of the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment are not consistent, the data are affected by soft errors, the output result is unreliable, the final operation result is output to be 0, the correct and wrong judgment signal is false, and the Beidou equipment, the airborne electronic hardware or the related high-safety field equipment are unreliable in operation.
When the counter reaches a set value, a comparison enabling signal Compare_en is set to 1, a data comparator starts to perform comparison operation, the theoretical output data and the actual output data are compared, if the theoretical output data and the actual output data are consistent, the DUT_out is output to a Final calculation result Final_out, a reset signal does not act, a Judge_out result judges a flag bit output 1, and the next subfield is continuously searched; if the two are inconsistent, the final_out does not output any result, rst_out is set to 1, reset operation is executed, the Beidou equipment, the airborne electronic hardware or related high-safety field equipment recalculates, the Judge_out result judges that the flag bit outputs 0, and the next sub-field searching is stopped, so that the actual matching time is saved.
The counter is shown in fig. 8. The counter description: clk is a clock, rst is a reset signal, the initial value of the counter is set to be the clock cycle number in delta t, and when the SRAM reads out the theoretical value, cnt_en is set to be 1, and counting is started to wait for the completion of the operation of Beidou equipment, airborne electronic hardware or related high-safety field equipment. After the count reaches the set value, the comparison enable signal Compare_en outputs 1, and the comparison operation is started.
The data comparator is shown in fig. 9, and compares the theoretical output data matched by the fast soft error detection circuit with the actual output data obtained by the operation of the Beidou equipment, the onboard electronic hardware or the related high-safety field equipment, so as to detect whether the Beidou equipment, the onboard electronic hardware or the related high-safety field equipment is affected by the soft error or not, and give out corresponding operation.
Data comparator description: clk is a clock, rst is a reset signal, compare_en is a comparison enabling signal, a counter gives out, data_output is theoretical output Data of a static random access memory, DUT_output is actual output Data of Beidou equipment, airborne electronic hardware or related high-safety field equipment, rst_out is a reset signal output, final_out is Final Data output, and if comparison results are consistent, DUT_output is output through Final_out, and Judge_out flag bit is output 1; if the comparison results are inconsistent, the final_out is not output, the Judge_out flag bit is output 0, and meanwhile, the reset signal Rst_out is set to 1, so that the Beidou equipment, the airborne electronic hardware or related high-safety field equipment is reset, and the operation is carried out again.
FIG. 10 is a circuit diagram of a fast soft error detection circuit, in which the signal flow and logic relationship between the modules can be clearly seen.
Note that: for the sake of brevity, all clock signals and reset signals in FIG. 10 have been omitted.

Claims (3)

1. A rapid soft error detection method for a Beidou signal processing complex operation chip is characterized by comprising the following steps of: the rapid soft error detection method comprises the following steps in sequence:
step 0) constructing a quick soft error detection circuit, wherein the quick soft error detection circuit comprises a quick flow table matching module, a static random access memory, a counter and a data comparator; the fast flow table matching module comprises a processing unit and an address decoder;
step 1): according to application scenes of different designs, selecting data with high occurrence frequency and typical characteristics as input data of a quick soft error detection circuit, and obtaining correct output data of the data through theoretical calculation or test simulation;
step 2): storing the output data obtained in the step 1) into an appointed address in a static random access memory, and compiling a rule set on the address in the static random access memory by utilizing the input data and the output data corresponding to the input data;
step 3): pre-coding the output data obtained in the step 1) and the rule set obtained in the step 2) by using a rule encoder to obtain a bit vector array, and storing the bit vector array in a processing unit of a fast flow table matching module for subsequent searching and matching operation;
step 4): respectively inputting data to be tested into a fast flow table matching module and a circuit to be tested; when the data to be tested is a typical data set in advance, the circuit to be tested executes complex operation, the fast flow table matching module directly reads out the corresponding bit vector value from the bit vector array stored in the processing unit obtained in the step 3) according to the matching relation between the data to be tested and the coding rule, and sends the bit vector value into the address decoder, and the address decoder is utilized to decode the bit vector value to obtain the address of the corresponding static random access memory, and the address is used for subsequently reading the data in the static random access memory;
step 5): reading theoretical output data corresponding to the input data to be tested from the static random access memory through the address obtained in the step 4), finishing operation when the circuit to be tested reaches the set value of the counter to obtain actual output data, and then sending the theoretical output data and the actual output data into the data comparator;
step 6): comparing the theoretical output data obtained in the step 5) with the actual output data given by the circuit to be tested by a data comparator, if the theoretical output data is consistent with the actual output data, the data of the circuit to be tested is not affected by soft errors, the actual operation result is reliable, the correct and wrong judgment signal is true, and the final operation result is output; if the data of the circuit to be tested is not consistent, the data is influenced by soft errors, the output result is unreliable, the final operation result is output to be 0, and the correct and wrong judgment signal is false, so that the operation of the circuit to be tested is unreliable.
2. The rapid soft error detection method for the Beidou signal processing complex operation chip of claim 1, wherein the rapid soft error detection method is characterized by comprising the following steps of: in step 4), the circuit to be tested is Beidou equipment, airborne electronic hardware or related high-safety field equipment.
3. The rapid soft error detection method for the Beidou signal processing complex operation chip of claim 1, wherein the rapid soft error detection method is characterized by comprising the following steps of: in step 5), the method for setting the set value of the counter is as follows: let the search completion time of the fast soft error detection circuit be t 0 The operation completion time of the circuit to be tested is t 1 The difference between them is Δt=t 1 - t 0 The clock cycle number in the difference deltat is used as the set value of the counter.
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