CN116150054B - Interrupt information processing method based on PCIE - Google Patents
Interrupt information processing method based on PCIE Download PDFInfo
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- CN116150054B CN116150054B CN202310174347.7A CN202310174347A CN116150054B CN 116150054 B CN116150054 B CN 116150054B CN 202310174347 A CN202310174347 A CN 202310174347A CN 116150054 B CN116150054 B CN 116150054B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the application discloses an interrupt information processing method based on PCIE, which comprises the following steps: when the equipment end detects an interrupt event each time, sending a corresponding interrupt vector, an interrupt request signal and a response frame to the PCIE end, and carrying out first marking on the interrupt request signal; the PCIE receives the response frame and the interrupt vector, sends the response frame to the PC, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, responds to the interrupt information if the interrupt vector is shielded, receives the interrupt vector again within a preset time, and sends an interrupt response signal to the equipment terminal and sends the interrupt information to the PC if the interrupt vector is not shielded; the equipment receives the interrupt response signal and marks the interrupt request signal for the second time; the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frame based on each interrupt information, and carries out corresponding processing, so that the data channel resource is saved, and the interrupt information loss and the occupation of a large amount of CPU of the PC side are avoided.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a method and a device for processing interrupt information based on PCIE and a storage medium.
Background
In a computer system, when an abnormal situation or special situation occurs in the process of executing a program, the computer stops running the current program and processes an abnormal process or a special request, thereby generating an interrupt vector.
In the prior art, when a PCIE interface device generally needs to report an interrupt, the interrupt information generally needs to be interacted with a PCIE Controller through a data channel, so that the data channel resource is occupied for a long time, meanwhile, the control flow and the interface are more complex, and when the corresponding interrupt vector is shielded, the interrupt information is possibly lost; or the equipment only returns a response frame to report the completion information, and the CPU at the PC end needs to deal with a large number of data processing, moving and other transactions, so that the CPU needs to continuously poll the response frame address, and the occupancy rate of the equipment to the CPU is larger.
Disclosure of Invention
The embodiment of the application provides an interrupt information processing method and a storage medium based on PCIE, which are used for solving the problems that data channel resources are occupied, interrupt information is lost and the occupancy rate of a device CPU is large, saving the data channel resources and avoiding the interrupt information loss and occupying a large amount of the device CPU.
In a first aspect, an embodiment of the present application provides a PCIE-based interrupt information processing method, including:
when an equipment end detects an interrupt event each time, the equipment end sends a corresponding interrupt vector, an interrupt request signal and a response frame to a PCIE end, and carries out first marking on the interrupt request signal so as to indicate that the interrupt vector is sent;
the PCIE terminal receives the response frame and the interrupt vector, sends the response frame to a PC terminal, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, does not respond to the interrupt information if the interrupt vector is shielded, receives the interrupt vector and the interrupt request signal sent by the equipment terminal again within a preset time, and sends an interrupt response signal to the equipment terminal if the interrupt vector is detected not to be shielded, and sends the interrupt information to the PC terminal, wherein the interrupt information comprises an interrupt vector number;
the equipment end receives the interrupt response signal, and carries out a second mark on the interrupt request signal so as to indicate that the interrupt vector is successfully sent, and stops sending the interrupt vector;
and the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and performs corresponding processing.
Further, before the device side detects the interrupt event, the method further includes:
the PC side is configured with a preset number of interrupt vectors, and the interrupt vectors are used for determining whether the interrupt information can be successfully sent, wherein the number of interrupt request signals is the same as that of the interrupt vectors, and one interrupt request signal corresponds to one interrupt vector.
Further, the first marking the interrupt request signal includes:
marking the interrupt request signal by pulling up a signal value corresponding to the interrupt request signal;
said second marking of said interrupt request signal comprises:
and marking the interrupt request signal by pulling down a signal value corresponding to the interrupt request signal.
Further, searching for a corresponding response frame based on the interrupt information includes:
and after receiving the interrupt information, searching a corresponding response frame from the response frame address according to the interrupt vector number in the interrupt information.
Further, sending the interrupt information to the PC side includes:
and sending the interrupt information to the PC side in a form of a TLP (tunnel protocol) message.
Further, if the interrupt vector is detected to be unmasked, the method further includes:
and adjusting the bit value corresponding to the interrupt vector to indicate whether the PC side processes the interrupt information.
Further, the adjusting the bit value, configured to indicate whether the PC side has processed the interrupt information, includes:
if the bit value is 1, the PC side does not process the interrupt information;
if the bit value is 0, the PC side is indicated to process the interrupt information.
In a second aspect, an embodiment of the present application provides an interrupt information processing apparatus based on PCIE, including:
and a sending module: the device side is used for sending interrupt information and interrupt request signals and reporting response frames to the PCIE side; the PCIE terminal is also used for transmitting a response frame to the PC terminal, and transmitting an interrupt response signal to the equipment terminal and transmitting the interrupt information to the PC terminal when detecting that the interrupt vector is not shielded;
and a determination module: the interrupt information corresponding to the interrupt vector is determined by the PCIE terminal;
and a receiving module: the PCIE terminal is used for receiving the response frame and the interrupt vector, and when the interrupt vector is shielded, the PCIE terminal is used for receiving the interrupt vector sent by the equipment terminal again within preset time;
and a judging module: the PCIE terminal is used for judging whether the interrupt vector is shielded or not;
and a marking module: the device side is used for marking the interrupt request signal to indicate that the interrupt vector is sent, the interrupt information comprises an interrupt vector number, and the device side is also used for marking the interrupt request signal after receiving the interrupt response signal to indicate that the interrupt vector is sent successfully and stopping sending the interrupt vector;
and (3) a searching module: after the PC side receives the interrupt information and the response frames respectively, searching the corresponding response frames based on each interrupt information, and performing corresponding processing.
In a third aspect, an embodiment of the present application provides a PCIE-based interrupt information processing method, including a memory and one or more processors;
the memory is used for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement a PCIE-based interrupt information processing method as described in the first aspect.
In a fourth aspect, an embodiment of the present application provides a storage medium containing computer executable instructions, which when executed by a computer processor, are configured to perform the PCIE-based interrupt information processing method according to the first aspect.
According to the embodiment of the application, when the equipment end detects an interrupt event each time, the equipment end sends a corresponding interrupt vector, an interrupt request signal and a response frame to the PCIE end, and carries out first marking on the interrupt request signal so as to indicate that the interrupt vector is sent; the PCIE terminal receives the response frame and the interrupt vector, sends the response frame to the PC terminal, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, does not respond to the interrupt information if the interrupt vector is shielded, receives the interrupt vector and the interrupt request signal sent by the equipment terminal again within preset time, sends an interrupt response signal to the equipment terminal if the interrupt vector is detected not to be shielded, sends the interrupt information to the PC terminal, the interrupt information comprises an interrupt vector number, avoids the condition that the response frame sent by equipment is lost, receives the interrupt response signal, and carries out a second mark on the interrupt request signal so as to be used for indicating that the interrupt vector is successfully sent, stops sending the interrupt vector, avoids long-time normal use of a data channel by a handshake mode of the interrupt request signal and the interrupt response signal, and simplifies the information reporting process and interface; the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and carries out corresponding processing, so that the CPU is prevented from continuously polling the response frames, and the occupancy rate of the equipment to the CPU is reduced.
Drawings
Fig. 1 is a flowchart of a PCIE-based interrupt information processing method provided by an embodiment of the present application;
fig. 2 is a schematic diagram of an interrupt information reporting method according to an embodiment of the present application;
FIG. 3 is a flow chart of a method for marking an interrupt request signal provided by an embodiment of the present application;
FIG. 4 is a flowchart of a method for adjusting bit values corresponding to an interrupt vector according to an embodiment of the present application;
fig. 5 is a block diagram of a module structure of an interrupt information processing method based on PCIE according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an interrupt information processing device based on PCIE according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the following detailed description of specific embodiments of the present application is given with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the matters related to the present application are shown in the accompanying drawings. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently, or at the same time. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Fig. 1 is a flowchart of a PCIE-based interrupt information processing method according to an embodiment of the present application, where, as shown in fig. 1, the method specifically includes:
step S101, when the device side detects an interrupt event, the device side sends a corresponding interrupt vector, an interrupt request signal, and a response frame to the PCIE side, and marks the interrupt request signal for indicating that the interrupt vector is sent.
The application scene of the scheme is that the response frame is searched and processed after the interrupt information is received and reported by the PC, so that the occupation of CPU resources is avoided. In this process, a specific reporting process of the interrupt information and a handshake process between the interrupt request signal and the interrupt response signal may be involved. Fig. 2 is a schematic diagram of an interrupt information reporting method provided by an embodiment of the present application, as shown in fig. 2, where the interrupt information reporting method includes information interaction of a device side, a PCIE side, and a PC side. The equipment end can be a mobile phone, a tablet personal computer or a notebook computer and the like, the PC end comprises a memory, a CPU and the like, and the PCIE end comprises a query module, an interrupt information control module, a TLP module, a configuration module, a data control module and the like. And the transmission of the data to be processed and the response frame between the PC end and the equipment end is realized through a data path.
In one embodiment, the interrupt event may be a program and execution process in which the CPU temporarily stops execution of the current program and instead executes to handle the new situation, and the interrupt event may include an external interrupt and an internal interrupt, where the internal interrupt may be an interrupt event to be initiated by a software interrupt instruction. The external interrupt may be an interrupt from outside the CPU, and may also be referred to as a hardware interrupt. Since the external devices are very numerous in kind and number, it is impossible for the CPU to specially design an interface for each external device to process his interrupt signal. Only a unified interface can be provided as a common line for interrupt signals, all interrupt signals from the peripheral devices sharing a common line connection with all CPUs. The CPU sends the data to be processed to the equipment end through the data channel, and the equipment end performs data processing on the data to be processed, so that the specific occurrence condition of the interrupt event is obtained. The interrupt vector may refer to an interrupt entry address generated by hardware in the microcomputer system or a head address where an interrupt service routine is deposited. The interrupt request signal may be used to transmit a transmission signal of an interrupt vector, where each bit signal in the interrupt request signal represents a determined interrupt vector, and may be represented in req [ n:0] form, and is used to represent that the device side includes n+1 functions such as function n to function 0, where n represents that function n corresponds to an nbit, and 0 represents that function 0 corresponds to an 0 th bit. For example, if the device contains three functions in total, function 0, function 1, and function 2, respectively, the interrupt request signal may be denoted as req [2:0]. The reply frame may contain different fields, where the different fields represent different meanings, and may include a frame header, a table address, a data length, a data type, a check, a frame end, and the like. The first flag may be used to flag whether a certain determined interrupt vector has been sent.
In one embodiment, the device side performs data processing on data to be processed, detects whether an interrupt event occurs at the device side, and when detecting that an interrupt event of a certain function occurs, sends an interrupt vector, an interrupt request signal and a response frame corresponding to the interrupt event of the function to the PCIE side. After the interrupt request signal is sent out, the equipment side records that the interrupt vector corresponding to a certain interrupt event is sent out in a mode of marking the interrupt request signal, so that the equipment side can conveniently know whether the interrupt vector corresponding to each interrupt event is sent out or not in time, and the condition that the interrupt information report is omitted is avoided.
Step S102, the PCIE side receives the response frame and the interrupt vector, sends the response frame to the PC side, determines interrupt information corresponding to the interrupt vector, determines whether the interrupt vector is masked, does not respond to the interrupt information if the interrupt vector is masked, and receives the interrupt vector and the interrupt request signal sent by the device side again within a preset time, and sends an interrupt response signal to the device side if it is detected that the interrupt vector is not masked, and sends the interrupt information to the PC side, where the interrupt information includes an interrupt vector number.
In one embodiment, the interrupt information may be specific information for representing an interrupt vector, and is used to prompt that a response frame of a certain function at the PC side has been uploaded, and the response frame address may be used to query the response frame. Optionally, in one embodiment, the interrupt information includes an interrupt vector number. The interrupt vector numbers may be used to distinguish between different functions of the device, one interrupt vector number corresponding to each function of the device, i.e. to each interrupt vector. The interrupt response signal may be a signal that feeds back the interrupt request signal, and may be expressed in an ack [ n:0], where n in ack [ n:0] is consistent with n in req [ n: 0].
In one embodiment, the PCIE side receives the interrupt vector and the response frame sent by the device side. Specifically, the interrupt vector is received through an interrupt information control module at the PCIE end, and the response frame is received through a data control module. Further, the query module actively queries whether the interrupt vector is masked according to the interrupt vector received in the interrupt information module. If the interrupt information corresponding to the interrupt vector can be queried, the interrupt vector is considered to be unmasked, otherwise, if the interrupt information corresponding to the interrupt vector can not be queried, the interrupt vector is considered to be unmasked. Further, if it is detected that the interrupt vector is masked and no interrupt information for the interrupt vector is queried, the PCIE terminal cannot respond to the interrupt information and receives the interrupt vector corresponding to the function again within a preset time. Specifically, if the interrupt vector is masked, the device side cannot receive the feedback signal of the interrupt request signal. Therefore, in one embodiment, the device side may preset a preset time, and when the device side does not receive the feedback signal corresponding to the interrupt request signal within the preset time, the same interrupt vector and interrupt request signal are sent to the PCIE side again. Therefore, if the interrupt vector is detected not to be shielded, the interrupt vector and the interrupt request signal sent by the equipment terminal are received again within the preset time, and the interrupt request signal is kept unchanged at the moment. If the interrupt vector is detected not to be shielded, the interrupt information corresponding to the interrupt vector is sent to the PC end, and an interrupt response signal corresponding to the interrupt vector is sent to the equipment end. And the interrupt information corresponding to the corresponding function in the equipment is prevented from being omitted by judging whether the interrupt vector is shielded or not.
Step 103, the device side receives the interrupt response signal, and marks the interrupt request signal for indicating that the interrupt vector is successfully sent, and stops sending the interrupt vector.
The second flag may be used to flag that a certain determined interrupt vector has been sent successfully. In one embodiment, the device receives an interrupt response signal fed back by the PCIE terminal, marks the interrupt response signal, determines that an interrupt vector corresponding to the interrupt response signal is not masked, and sends interrupt information corresponding to the interrupt vector to the PC terminal. The device side can determine that the interrupt vector corresponding to the function does not need to be sent again within the preset time according to the received interrupt response signal. Interaction between the equipment and the PCIE terminal interrupt vector is realized through handshake between the interrupt request signal and the interrupt response signal, so that the interrupt information reporting flow is simpler, and the long-time occupation of a data channel is avoided.
Step S104, the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and carries out corresponding processing.
In one embodiment, the PC side receives the interrupt information and the response frame respectively, where the PC side does not necessarily receive the interrupt information and the response frame corresponding to the same function at the same time, and the receiving time of the interrupt information and the response frame has a time difference because the interrupt vector may be masked. And a response frame is received each time the occurrence of an interrupt event is detected, there may be a plurality of response frames in the CPU. After the PC receives the interrupt information, searching a corresponding response frame according to the interrupt information, and processing the searched response frame according to different sent data to be processed. The PC receives the interrupt information and searches the corresponding response frame, so that the CPU can be prevented from continuously polling the response frame, the resources of the CPU are occupied, and meanwhile, the interrupt information can be prevented from being lost.
In the above-mentioned embodiment, when the device side detects an interrupt event, the device side sends a corresponding interrupt vector, an interrupt request signal and a response frame to the PCIE side, and performs a first flag on the interrupt request signal to indicate that the interrupt vector is sent, so that the device side can conveniently know in time whether the interrupt vector corresponding to each interrupt event has been sent, and avoid the situation that reporting of interrupt information is omitted; the PCIE terminal receives the response frame and the interrupt vector, sends the response frame to a PC terminal, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, does not respond to the interrupt information if the interrupt vector is shielded, receives the interrupt vector and the interrupt request signal sent by the equipment terminal again within a preset time, and sends an interrupt response signal to the equipment terminal if the interrupt vector is detected not to be shielded, and sends the interrupt information to the PC terminal, wherein the interrupt information comprises an interrupt vector number; the interrupt information corresponding to the corresponding function in the equipment is prevented from being omitted by judging whether the interrupt vector is shielded or not; the equipment end receives the interrupt response signal, carries out a second mark on the interrupt request signal to be used for indicating that the interrupt vector is successfully sent and stopping sending the interrupt vector, and realizes interaction between the equipment and the PCIE end interrupt vector through handshake between the interrupt request signal and the interrupt response signal, so that the interrupt information reporting flow is simpler, and long-time occupation of a data channel is avoided; the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and carries out corresponding processing, so that the CPU can be prevented from continuously polling the response frames, the resources of the CPU are occupied, and meanwhile, the loss of the interrupt information can be prevented.
In one embodiment, optionally, before the device side detects the interrupt event, the method further includes:
the PC side is configured with a preset number of interrupt vectors, and the interrupt vectors are used for determining whether the interrupt information can be successfully sent, wherein the number of interrupt request signals is the same as that of the interrupt vectors, and one interrupt request signal corresponds to one interrupt vector.
In one embodiment, the number of interrupt request signals is the number of interrupt events that occur. Optionally, the number of interrupt request signals is the same as the number of interrupt vectors, and one interrupt request signal corresponds to one interrupt vector. The PC side can configure a preset number of interrupt vectors for the equipment in advance, and when a corresponding interrupt event occurs, the interrupt information can be conveniently reported in time. The number of the configuration interrupt vectors can be determined according to the number of the functions in the device, and one function in the device corresponds to one interrupt vector, that is, one function in the device corresponds to one interrupt request signal.
As can be seen from the foregoing, in one embodiment, the PC side configures a preset number of interrupt vectors to determine whether the interrupt information can be sent successfully, where the number of interrupt request signals is the same as the number of interrupt vectors, and one interrupt request signal corresponds to one interrupt vector, which can facilitate timely reporting of interrupt information.
In one embodiment, optionally, searching for a corresponding response frame based on the interrupt information includes:
and after receiving the interrupt information, searching a corresponding response frame from the response frame address according to the interrupt vector number in the interrupt information.
The reply frame address may be used to identify a specific location of a reply frame corresponding to a function, where the same function in the device side may correspond to multiple reply frame addresses. In one embodiment, after the PC receives the interrupt information, the interrupt vector number included in the interrupt information is determined, and further, all response frames corresponding to the function are searched in the response frame address according to the interrupt vector number. From the above, in one embodiment, the PC side searches for the corresponding response frame based on the interrupt information only after receiving the interrupt information, so as to avoid the CPU from continuously polling the response frame and reduce the occupancy rate of the device to the CPU.
In one embodiment, optionally, sending the interrupt information to the PC side includes:
and sending the interrupt information to the PC side in a form of a TLP (tunnel protocol) message.
In one embodiment, the TLP module at the PCIE side is responsible for generating TLP transport layer packets at the sending side, and decoding TLP packets at the receiving side, and is responsible for qos control and transmission order of interrupt information. In one embodiment, the interrupt information is transmitted to the PC end in the form of a TLP, which is favorable for implementing mutual communication between different types of data interrupt devices, and can greatly improve the transmission efficiency of the line.
Fig. 3 is a flowchart of a method for marking an interrupt request signal according to an embodiment of the present application, as shown in fig. 3, specifically including:
step S301, when the device side detects an interrupt event, the device side sends a corresponding interrupt vector, an interrupt request signal, and a response frame to the PCIE side, and marks the interrupt request signal by pulling up a signal value corresponding to the interrupt request signal, so as to be used to indicate that the interrupt vector corresponding to the interrupt request signal is sent.
The signal values may include 0 and 1. The signal value corresponding to the pull-up interrupt request signal may be that the signal value corresponding to the corresponding function is adjusted to 1 at the device side. In one embodiment, when an interrupt event is detected, a function corresponding to the interrupt event is determined to occur accordingly, so that a signal value corresponding to the function is pulled up, which is used to indicate that an interrupt vector corresponding to the function has been sent to the PCIE end. For example, if the device side includes 3 functions, namely, function 0, function 1 and function 2, when an interrupt event occurs in function 1, req [2:0] is sent to the PCIE side, and the signal value corresponding to the function 1 is pulled up correspondingly at the device side. Specifically, the signal value corresponding to the function 1 is adjusted to be 1, so as to indicate that the interrupt vector corresponding to the function 1 is sent to the PCIE end.
Step S302, the PCIE side receives the response frame and the interrupt vector, sends the response frame to the PC side, determines interrupt information corresponding to the interrupt vector, determines whether the interrupt vector is masked, does not respond to the interrupt information if the interrupt vector is masked, and receives the interrupt vector and the interrupt request signal sent by the device side again within a preset time, and sends an interrupt response signal to the device side if it is detected that the interrupt vector is not masked, and sends the interrupt information to the PC side, where the interrupt information includes an interrupt vector number.
Step S303, the device side receives the interrupt response signal, marks the interrupt request signal by pulling down a signal value corresponding to the interrupt request signal, so as to indicate that the interrupt vector corresponding to the interrupt request signal is successfully sent, and stops sending the interrupt vector.
The signal value corresponding to the interrupt request signal may be pulled down by adjusting the signal value corresponding to the corresponding function to 0 at the device side. In one embodiment, when the PCIE end detects that a certain interrupt vector is not masked, an interrupt response signal is sent to the device end, and after the device end receives the interrupt response signal, a function for the interrupt response signal is correspondingly determined, so that a signal value corresponding to the function is pulled down, which is used to indicate that the interrupt vector corresponding to the function has been sent successfully. For example, if the device side includes 3 functions, namely, function 0, function 1 and function 2, when an interrupt event occurs in function 1, req [2:0] is sent to the PCIE side, and if the PCIE side detects that the interrupt vector corresponding to the function is not masked, ack [2:0] is sent to the device side, and the device side receives ack [2:0] sent by the PCIE side and pulls down the signal value corresponding to the function 1 accordingly. Specifically, the signal value corresponding to the function 1 is adjusted to 0, so as to indicate that the interrupt vector corresponding to the function 1 has been sent successfully.
Step S304, the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and carries out corresponding processing.
As can be seen from the foregoing, in one embodiment, the interrupt request signal is marked by pulling high a signal value corresponding to the interrupt request signal to indicate that an interrupt vector corresponding to the interrupt request signal has been sent, the interrupt request signal is marked by pulling low a signal value corresponding to the interrupt request signal to indicate that an interrupt vector corresponding to the interrupt request signal has been sent, and sending of the interrupt vector is stopped. By means of handshake between the interrupt request signal and the interrupt response signal, long-time common use of the data channel is avoided, and the information reporting flow and interface are simplified.
Fig. 4 is a flowchart of a method for adjusting a bit value corresponding to an interrupt vector according to an embodiment of the present application, as shown in fig. 4, specifically including:
in step S401, when the device side detects an interrupt event, the device side sends a corresponding interrupt vector, an interrupt request signal, and a response frame to the PCIE side, and marks the interrupt request signal for indicating that the interrupt vector is sent.
Step S402, the PCIE side receives the response frame and the interrupt vector, sends the response frame to the PC side, determines interrupt information corresponding to the interrupt vector, determines whether the interrupt vector is masked, does not respond to the interrupt information if the interrupt vector is masked, receives the interrupt vector and the interrupt request signal sent by the device side again within a preset time, and adjusts a bit value corresponding to the interrupt vector if it is detected that the interrupt vector is not masked, so as to indicate whether the PC side has processed the interrupt information.
The bit value (Pending bit) may include 0 and 1. Specifically, the bit value is configured through a configuration module of the PCIE end. In one embodiment, after the query module at the PCIE end detects that the interrupt vector is not masked, the interrupt information corresponding to the interrupt information is sent to the PC end, and the bit value is adjusted accordingly, so that the bit value indicates whether the PC end processes the received interrupt information.
Step S403, the device side receives the interrupt response signal, and marks the interrupt request signal for indicating that the interrupt vector is successfully sent, and stops sending the interrupt vector.
Step S404, the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and performs corresponding processing.
In the above embodiment, by adjusting the bit value corresponding to the interrupt vector, it is indicated whether the PC side has processed the interrupt information, which is beneficial to ensuring that the response frame is not lost.
In an embodiment, optionally, the adjusting the bit value to indicate whether the PC side has processed the interrupt information includes:
if the bit value is 1, the PC side does not process the interrupt information;
if the bit value is 0, the PC side is indicated to process the interrupt information.
Processing the interrupt information may be searching for the response frame based on the interrupt vector number in the interrupt information. In one embodiment, the bit value is adjusted to 1 if the interrupt vector is not masked, and remains different if the bit value is already 1, indicating that there is unprocessed interrupt information. When all interrupt information processing is completed, the bit value information is adjusted to 0, which indicates that unprocessed interrupt information does not exist.
In the above embodiment, whether the unprocessed interrupt information exists is indicated by a bit value, which is favorable for processing the unprocessed interrupt information in time, and avoids missing a certain interrupt information, thereby leading to the loss of the response frame.
Fig. 5 is a block diagram of a module structure of an interrupt information processing method based on PCIE according to an embodiment of the present application, where, as shown in fig. 5, the method specifically includes:
the transmission module 51: the device side is used for sending interrupt information, interrupt request signals and response frames to the PCIE side; the PCIE terminal is also used for transmitting a response frame to the PC terminal, and transmitting an interrupt response signal to the equipment terminal and transmitting the interrupt information to the PC terminal when detecting that the interrupt vector is not shielded;
determination module 52: the interrupt information corresponding to the interrupt vector is determined by the PCIE terminal;
the receiving module 53: the PCIE terminal is used for receiving the response frame and the interrupt vector, and when the interrupt vector is shielded, the PCIE terminal is used for receiving the interrupt vector sent by the equipment terminal again within preset time;
the judgment module 54: the PCIE terminal is used for judging whether the interrupt vector is shielded or not;
marking module 55: the device side is used for marking the interrupt request signal to indicate that the interrupt vector is sent, the interrupt information comprises an interrupt vector number, and the device side is also used for marking the interrupt request signal after receiving the interrupt response signal to indicate that the interrupt vector is sent successfully and stopping sending the interrupt vector;
the lookup module 56: after the PC side receives the interrupt information and the response frames respectively, searching the corresponding response frames based on each interrupt information, and performing corresponding processing.
In the above-mentioned embodiment, when the device side detects an interrupt event, the device side sends a corresponding interrupt vector, an interrupt request signal and a response frame to the PCIE side, and performs a first flag on the interrupt request signal to indicate that the interrupt vector is sent, so that the device side can conveniently know in time whether the interrupt vector corresponding to each interrupt event has been sent, and avoid the situation that reporting of interrupt information is omitted; the PCIE terminal receives the response frame and the interrupt vector, sends the response frame to a PC terminal, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, does not respond to the interrupt information if the interrupt vector is shielded, receives the interrupt vector and the interrupt request signal sent by the equipment terminal again within a preset time, and sends an interrupt response signal to the equipment terminal if the interrupt vector is detected not to be shielded, and sends the interrupt information to the PC terminal, wherein the interrupt information comprises an interrupt vector number; the interrupt information corresponding to the corresponding function in the equipment is prevented from being omitted by judging whether the interrupt vector is shielded or not; the equipment end receives the interrupt response signal, carries out a second mark on the interrupt request signal to be used for indicating that the interrupt vector is successfully sent and stopping sending the interrupt vector, and realizes interaction between the equipment and the PCIE end interrupt vector through handshake between the interrupt request signal and the interrupt response signal, so that the interrupt information reporting flow is simpler, and long-time occupation of a data channel is avoided; the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and carries out corresponding processing, so that the CPU can be prevented from continuously polling the response frames, the resources of the CPU are occupied, and meanwhile, the loss of the interrupt information can be prevented.
In one possible embodiment, the apparatus further comprises a configuration module for:
the PC side is configured with a preset number of interrupt vectors, and the interrupt vectors are used for determining whether the interrupt information can be successfully sent, wherein the number of interrupt request signals is the same as that of the interrupt vectors, and one interrupt request signal corresponds to one interrupt vector.
In one possible embodiment, the marking module 55 is specifically configured to:
marking the interrupt request signal by pulling up a signal value corresponding to the interrupt request signal;
and marking the interrupt request signal by pulling down a signal value corresponding to the interrupt request signal.
In one possible embodiment, the searching module 56 is specifically configured to:
after receiving the interrupt information, searching a corresponding response frame from a response frame address according to the interrupt vector number in the interrupt information
In one possible embodiment, the sending module 51 is specifically configured to:
and sending the interrupt information to the PC side in a form of a TLP (tunnel protocol) message.
In one possible embodiment, the apparatus further comprises a value adjustment module for:
and adjusting the bit value corresponding to the interrupt vector to indicate whether the PC side processes the interrupt information.
In one possible embodiment, the numerical adjustment module is specifically configured to:
if the bit value corresponding to the interrupt vector is 1, the PC side is not used for processing the interrupt information;
if the bit value corresponding to the interrupt vector is 0, the PC side is indicated to process the interrupt information.
Fig. 6 is a schematic structural diagram of an interruption information processing device based on PCIE according to an embodiment of the present application, where, as shown in fig. 6, the device includes a processor 601, a memory 602, an input device 603, and an output device 604; the number of processors 601 in the device may be one or more, one processor 601 being taken as an example in fig. 6; the processor 601, memory 602, input means 603 and output means 604 in the device may be connected by a bus or other means, in fig. 6 by way of example. The memory 602 is used as a computer readable storage medium, and may be used to store a software program, a computer executable program, and a module, such as program instructions/modules corresponding to the PCIE-based interrupt information processing method in the embodiment of the present application. The processor 601 executes various functional applications of the device and data processing by executing software programs, instructions and modules stored in the memory 602, that is, implements the above-described PCIE-based interrupt information processing method. The input means 603 may be used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the device. The output 604 may include a display device such as a display screen.
The embodiment of the application also provides a storage medium containing computer executable instructions, which when executed by a computer processor, are used for executing a method for processing interrupt information based on PCIE, and the method comprises the following steps: when an equipment end detects an interrupt event each time, the equipment end sends a corresponding interrupt vector, an interrupt request signal and a response frame to a PCIE end, and carries out first marking on the interrupt request signal so as to indicate that the interrupt vector is sent; the PCIE terminal receives the response frame and the interrupt vector, sends the response frame to a PC terminal, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, does not respond to the interrupt information if the interrupt vector is shielded, receives the interrupt vector and the interrupt request signal sent by the equipment terminal again within a preset time, and sends an interrupt response signal to the equipment terminal if the interrupt vector is detected not to be shielded, and sends the interrupt information to the PC terminal, wherein the interrupt information comprises an interrupt vector number; the equipment end receives the interrupt response signal, and carries out a second mark on the interrupt request signal so as to indicate that the interrupt vector is successfully sent, and stops sending the interrupt vector; and the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and performs corresponding processing.
It should be noted that, in the embodiment of the above-mentioned interrupt information processing method device based on PCIE, each unit and module included are only divided according to functional logic, but are not limited to the above-mentioned division, so long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the embodiments of the present application.
Note that the above is only a preferred embodiment of the present application and the technical principle applied. It will be understood by those skilled in the art that the embodiments of the present application are not limited to the particular embodiments described herein, but are capable of numerous obvious changes, rearrangements and substitutions without departing from the scope of the embodiments of the present application. Therefore, while the embodiments of the present application have been described in connection with the above embodiments, the embodiments of the present application are not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the embodiments of the present application, and the scope of the embodiments of the present application is determined by the scope of the appended claims.
Claims (10)
1. The interrupt information processing method based on PCIE is characterized by comprising the following steps:
when an equipment end detects an interrupt event each time, the equipment end sends a corresponding interrupt vector, an interrupt request signal and a response frame to a PCIE end, and carries out a first mark on the interrupt request signal so as to indicate that the interrupt vector is sent, the equipment end presets a preset time, and when the equipment end does not receive the interrupt response signal within the preset time, the equipment end sends the same interrupt vector and interrupt request signal to the PCIE end again;
the PCIE terminal receives the response frame and the interrupt vector, sends the response frame to a PC terminal, determines interrupt information corresponding to the interrupt vector, judges whether the interrupt vector is shielded, does not respond to the interrupt information if the interrupt vector is shielded, receives the interrupt vector and the interrupt request signal sent by the equipment terminal again within a preset time, and sends an interrupt response signal to the equipment terminal if the interrupt vector is detected not to be shielded, and sends the interrupt information to the PC terminal, wherein the interrupt information comprises an interrupt vector number;
the equipment end receives the interrupt response signal, and carries out a second mark on the interrupt request signal so as to indicate that the interrupt vector is successfully sent, and stops sending the interrupt vector;
and the PC side receives the interrupt information and the response frames respectively, searches the corresponding response frames based on each interrupt information, and performs corresponding processing.
2. The PCIE-based interrupt information processing method of claim 1, further comprising, before the device side detects the interrupt event:
the PC side is configured with a preset number of interrupt vectors, and the interrupt vectors are used for determining whether the interrupt information can be successfully sent, wherein the number of interrupt request signals is the same as that of the interrupt vectors, and one interrupt request signal corresponds to one interrupt vector.
3. The PCIE-based interrupt information processing method of claim 1 wherein said first marking the interrupt request signal comprises:
marking the interrupt request signal by pulling up a signal value corresponding to the interrupt request signal;
said second marking of said interrupt request signal comprises:
and marking the interrupt request signal by pulling down a signal value corresponding to the interrupt request signal.
4. The PCIE-based interrupt information processing method of claim 1 wherein searching for a corresponding response frame based on the interrupt information comprises:
and after receiving the interrupt information, searching a corresponding response frame from the response frame address according to the interrupt vector number in the interrupt information.
5. The PCIE-based interrupt information processing method according to any one of claims 1-3 wherein sending the interrupt information to the PC side comprises:
and sending the interrupt information to the PC side in a form of a TLP (tunnel protocol) message.
6. The PCIE-based interrupt information processing method according to any one of claims 1-3, further comprising, after detecting that the interrupt vector is not masked:
and adjusting the bit value corresponding to the interrupt vector to indicate whether the PC side processes the interrupt information.
7. The PCIE-based interrupt information processing method of claim 6 wherein adjusting the bit value to indicate whether the PC side has processed the interrupt information comprises:
if the bit value is 1, the PC side does not process the interrupt information;
if the bit value is 0, the PC side is indicated to process the interrupt information.
8. An interrupt information processing apparatus based on PCIE, the apparatus comprising:
and a sending module: the device side is used for sending interrupt information, interrupt request signals and response frames to the PCIE side; the PCIE terminal is also used for transmitting a response frame to the PC terminal, and transmitting an interrupt response signal to the equipment terminal and transmitting the interrupt information to the PC terminal when detecting that the interrupt vector is not shielded; the equipment end presets a preset time, and when the equipment end does not receive an interrupt response signal within the preset time, the same interrupt vector and interrupt request signal are sent to the PCIE end again;
and a determination module: the interrupt information corresponding to the interrupt vector is determined by the PCIE terminal;
and a receiving module: the PCIE terminal is used for receiving the response frame and the interrupt vector, and when the interrupt vector is shielded, the PCIE terminal is used for receiving the interrupt vector sent by the equipment terminal again within preset time;
and a judging module: the PCIE terminal is used for judging whether the interrupt vector is shielded or not;
and a marking module: the device side is used for marking the interrupt request signal to indicate that the interrupt vector is sent, the interrupt information comprises an interrupt vector number, and the device side is also used for marking the interrupt request signal after receiving the interrupt response signal to indicate that the interrupt vector is sent successfully and stopping sending the interrupt vector;
and (3) a searching module: after the PC side receives the interrupt information and the response frames respectively, searching the corresponding response frames based on each interrupt information, and performing corresponding processing.
9. An interrupt information processing apparatus based on PCIE, the apparatus comprising: one or more processors; storage means for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement a PCIE-based interrupt information processing method as claimed in any one of claims 1 to 7.
10. A storage medium storing computer executable instructions which, when executed by a computer processor, are for performing a PCIE-based interrupt information processing method according to any one of claims 1-7.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11232210A (en) * | 1998-02-16 | 1999-08-27 | Fuji Xerox Co Ltd | Information processor |
| US6098144A (en) * | 1996-09-20 | 2000-08-01 | U.S. Philips Corporation | Solid state data processor with versatile multisource interrupt organization |
| CN103150146A (en) * | 2013-01-31 | 2013-06-12 | 西安电子科技大学 | ASIP (application-specific instruction-set processor) based on extensible processor architecture and realizing method thereof |
| CN111656336A (en) * | 2018-06-30 | 2020-09-11 | 华为技术有限公司 | PCIE sending and receiving method, device, equipment and system |
| CN115422106A (en) * | 2022-09-30 | 2022-12-02 | 新华三信息技术有限公司 | Interrupt request processing method and device |
-
2023
- 2023-02-24 CN CN202310174347.7A patent/CN116150054B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6098144A (en) * | 1996-09-20 | 2000-08-01 | U.S. Philips Corporation | Solid state data processor with versatile multisource interrupt organization |
| JPH11232210A (en) * | 1998-02-16 | 1999-08-27 | Fuji Xerox Co Ltd | Information processor |
| CN103150146A (en) * | 2013-01-31 | 2013-06-12 | 西安电子科技大学 | ASIP (application-specific instruction-set processor) based on extensible processor architecture and realizing method thereof |
| CN111656336A (en) * | 2018-06-30 | 2020-09-11 | 华为技术有限公司 | PCIE sending and receiving method, device, equipment and system |
| CN115422106A (en) * | 2022-09-30 | 2022-12-02 | 新华三信息技术有限公司 | Interrupt request processing method and device |
Non-Patent Citations (1)
| Title |
|---|
| Linux内核实时性能改进方案;来宾等;微计算机应用;第28卷(第03期);全文 * |
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