CN116127260A

CN116127260A - Data processing method, device, equipment and medium

Info

Publication number: CN116127260A
Application number: CN202310086458.2A
Authority: CN
Inventors: 邰秀瑢; 陈庆澍; 王勇; 欧阳剑; 王京
Original assignee: Kunlun Core Beijing Technology Co ltd
Current assignee: Kunlun Core Beijing Technology Co ltd
Priority date: 2023-01-18
Filing date: 2023-01-18
Publication date: 2023-05-16

Abstract

The disclosure provides a data processing method, a data processing device, data processing equipment and a data processing medium, relates to the technical field of chips, and particularly relates to the technical field of data processing. The implementation scheme is as follows: acquiring a first matrix and a second matrix, and dividing the first matrix into a plurality of first sub-matrices; determining a first sub-element with the largest absolute value for each first sub-matrix and recording the absolute value of the first sub-element as Max1; mapping each element in the first sub-matrix to [0,2 ] based on Max1 ⁿ ]A section to obtain a corresponding conversion element; dividing the second matrix into a plurality of second sub-matrices; determining a second sub-element with the largest absolute value for each second sub-matrix, and recording the absolute value of the second sub-element as Max2; based on mapping each element in the second sub-matrix to [0,2 ] ⁿ ]A section to obtain a corresponding conversion element; and calculating a product of the first matrix and the second matrix based on the conversion element to which each element in the first matrix and the second matrix corresponds, respectively.

Description

Data processing method, device, equipment and medium

Technical Field

The present disclosure relates to the field of chip technology, and in particular, to the field of data processing technology, and in particular, to a data processing method, apparatus, electronic device, computer readable storage medium, and computer program product.

Background

Artificial intelligence is the discipline of studying the process of making a computer mimic certain mental processes and intelligent behaviors (e.g., learning, reasoning, thinking, planning, etc.) of a person, both hardware-level and software-level techniques. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing, and the like; the artificial intelligence software technology mainly comprises a computer vision technology, a voice recognition technology, a natural language processing technology, a machine learning/deep learning technology, a big data processing technology, a knowledge graph technology and the like.

Artificial intelligence models exist with a large number of computationally intensive operators, mainly including matrix multiplication, convolution, pooling, activation, and the like. These calculations are time consuming, and the computational power of conventional CPUs is difficult to meet in terms of performance, so heterogeneous calculations are becoming the mainstream, and various artificial intelligence processors including GPU, FPGA, ASIC are largely applied to artificial intelligence model calculations. Meanwhile, the selection of the data type plays a very important role in the precision, performance and the like of the artificial intelligence calculation.

The approaches described in this section are not necessarily approaches that have been previously conceived or pursued. Unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. Similarly, the problems mentioned in this section should not be considered as having been recognized in any prior art unless otherwise indicated.

Disclosure of Invention

The present disclosure provides a data processing method, apparatus, electronic device, computer readable storage medium, and computer program product.

According to an aspect of the present disclosure, there is provided a data processing method including: obtaining a first matrix and a second matrix, whichWherein each element in the first matrix and the second matrix is in a first data format, and the first data format comprises a floating point type; dividing the first matrix into a plurality of first sub-matrices, wherein the absolute value of an element in each of the plurality of first sub-matrices meets a preset condition; for each first sub-matrix in the plurality of first sub-matrices, determining a first sub-element with the largest absolute value in the first sub-matrix, and marking the largest absolute value of the first sub-element as a first sub-matrix maximum value Max1; converting the element into a conversion element of a second data format based on the first sub-matrix maximum Max1, the second data format comprising n mantissa digits, n being an integer greater than 1, and wherein each element of the first sub-matrix is mapped to [0,2 ] based on the first sub-matrix maximum Max1 ⁿ ]A section to determine the tail number of the conversion element corresponding to the element; dividing the second matrix into a plurality of second sub-matrices, wherein the absolute value of an element in each of the plurality of second sub-matrices meets a preset condition; for each second sub-matrix in the plurality of second sub-matrices, determining a second sub-element with the largest absolute value in the second sub-matrix, and marking the largest absolute value of the second sub-element as a second sub-matrix maximum value Max2; mapping each element in the second submatrix to [0,2 ζ ] based on the second submatrix maximum value Max2]A section to convert the element into a conversion element in a second data format; and calculating the product of the first matrix and the second matrix based on the conversion elements respectively corresponding to each element in the first matrix and the second matrix.

According to another aspect of the present disclosure, there is provided a data processing apparatus including: a first acquisition unit configured to acquire a first matrix and a second matrix, wherein each element in the first matrix and the second matrix is in a first data format, and the first data format comprises a floating point type; a dividing unit configured to divide the first matrix into a plurality of first sub-matrices, wherein an absolute value of an element in each of the plurality of first sub-matrices satisfies a pre-criterion Setting conditions; a first determining unit configured to determine, for each of the plurality of first sub-matrices, a first sub-element having a largest absolute value among the first sub-matrices, and record the largest absolute value of the first sub-element as a first sub-matrix maximum value Max1; a conversion unit configured to convert the element into a conversion element of a second data format based on the first sub-matrix maximum Max1, the second data format comprising n mantissa bits, n being an integer greater than 1, and wherein each element in the first sub-matrix is mapped to [0,2 ] based on the first sub-matrix maximum Max1 ⁿ ]A section to determine the tail number of the conversion element corresponding to the element; the dividing unit is further configured to divide the second matrix into a plurality of second sub-matrices, wherein an absolute value of an element in each of the plurality of second sub-matrices satisfies a preset condition; the first determining unit is further configured to determine, for each of the plurality of second sub-matrices, a second sub-element having a largest absolute value in the second sub-matrix, and record the largest absolute value of the second sub-element as a second sub-matrix maximum value Max2; the conversion unit is further configured to map each element in the second sub-matrix to [0,2 ] based on the second sub-matrix maximum Max2 ⁿ ]A section to convert the element into a conversion element in a second data format; and a calculation unit configured to calculate a product of the first matrix and the second matrix based on the conversion element to which each element in the first matrix and the second matrix corresponds, respectively.

According to another aspect of the present disclosure, there is provided a chip comprising a data processing apparatus as described above.

According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the data processing method described above.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the above-described data processing method.

According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program is capable of implementing the above-mentioned data processing method when being executed by a processor.

According to one or more embodiments of the present disclosure, the calculation accuracy can be ensured while improving the calculation efficiency.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The accompanying drawings illustrate exemplary embodiments and, together with the description, serve to explain exemplary implementations of the embodiments. The illustrated embodiments are for exemplary purposes only and do not limit the scope of the claims. Throughout the drawings, identical reference numerals designate similar, but not necessarily identical, elements.

FIG. 1 illustrates a schematic diagram of an exemplary system in which various methods described herein may be implemented, according to an exemplary embodiment of the present disclosure;

FIG. 2 illustrates a flow chart of a data processing method according to an exemplary embodiment of the present disclosure;

FIG. 3 illustrates a flowchart of a method of converting elements in a matrix into converted elements, according to an exemplary embodiment of the present disclosure;

FIG. 4 shows a block diagram of a data processing apparatus according to an exemplary embodiment of the present disclosure;

Fig. 5 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

In the present disclosure, the use of the terms "first," "second," and the like to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of the elements, unless otherwise indicated, and such terms are merely used to distinguish one element from another. In some examples, a first element and a second element may refer to the same instance of the element, and in some cases, they may also refer to different instances based on the description of the context.

The terminology used in the description of the various illustrated examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context clearly indicates otherwise, the elements may be one or more if the number of the elements is not specifically limited. Furthermore, the term "and/or" as used in this disclosure encompasses any and all possible combinations of the listed items.

In the related art, in the calculation process of the artificial intelligence model, the standard IEEE float type is mainly adopted, and with the continuous development of technology, new calculation types are generated to replace standard float, such as new semi-precision calculation types of bfoat 16, fp16, int16 and the like. fp16 and bfoat 16 comprise sign bits, exponent bits and mantissa bits, and because of the exponent bits, the range of values that can be represented is large, but because of the complexity of the computation due to the large number of exponent bits, the computational efficiency is low relative to int 16. Since int16 is a fixed point calculation, the calculation efficiency will be higher than fp 16/bfoat 16, but the data format of int16 does not contain a digit, the numerical range that can be represented is smaller than fp 16/bfoat 16, and in many artificial intelligence model training processes, the situation of non-convergence can occur, so the range of use is limited.

Based on this, the present disclosure provides a data processing method of dividing a matrix to be calculated into a plurality of submatrices in a matrix calculation process, mapping each element in the submatrices to [0,2 ] based on a maximum value of each submatrix ⁿ ]The interval is used for obtaining the conversion elements of the second data format comprising n tail digits, and the matrix to be calculated is utilized for summarizing the corresponding conversion elements of each element to calculate, so that floating point number calculation is converted into fixed point calculation without indexes, the calculation difficulty is reduced, the calculation efficiency is improved, and the hardware resources for calculation are saved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 1 illustrates a schematic diagram of an exemplary system 100 in which various methods and apparatus described herein may be implemented, in accordance with an embodiment of the present disclosure. Referring to fig. 1, the system 100 includes one or

more client devices

101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120.

Client devices

101, 102, 103, 104, 105, and 106 may be configured to execute one or more applications.

In embodiments of the present disclosure, the server 120 may run one or more services or software applications that enable execution of the data processing methods.

In some embodiments, server 120 may also provide other services or software applications, which may include non-virtual environments and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, for example, provided to users of

client devices

101, 102, 103, 104, 105, and/or 106 under a software as a service (SaaS) model.

In the configuration shown in fig. 1, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or a combination thereof that are executable by one or more processors. A user

operating client devices

101, 102, 103, 104, 105, and/or 106 may in turn utilize one or more client applications to interact with server 120 to utilize the services provided by these components. It should be appreciated that a variety of different system configurations are possible, which may differ from system 100. Accordingly, FIG. 1 is one example of a system for implementing the various methods described herein and is not intended to be limiting.

The user may use

client devices

101, 102, 103, 104, 105 and/or 106 to send matrix data to be calculated. The client device may provide an interface that enables a user of the client device to interact with the client device. The client device may also output information to the user via the interface. Although fig. 1 depicts only six client devices, those skilled in the art will appreciate that the present disclosure may support any number of client devices.

Client devices

101, 102, 103, 104, 105, and/or 106 may include various types of computer devices, such as portable handheld devices, general purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors or other sensing devices, and the like. These computer devices may run various classes and versions of software applications and operating systems, such as MICROSOFT Windows, APPLE iOS, UNIX-like operating systems, linux, or Linux-like operating systems (e.g., GOOGLE Chrome OS); or include various mobile operating systems such as MICROSOFT Windows Mobile OS, iOS, windows Phone, android. Portable handheld devices may include cellular telephones, smart phones, tablet computers, personal Digital Assistants (PDAs), and the like. Wearable devices may include head mounted displays (such as smart glasses) and other devices. The gaming system may include various handheld gaming devices, internet-enabled gaming devices, and the like. The client device is capable of executing a variety of different applications, such as various Internet-related applications, communication applications (e.g., email applications), short Message Service (SMS) applications, and may use a variety of communication protocols.

Network 110 may be any of a variety of networks known to those skilled in the art that may support data communications using any of a variety of available protocols, including but not limited to TCP/IP, SNA, IPX, etc. For example only, the one or more networks 110 may be a Local Area Network (LAN), an ethernet-based network, a token ring, a Wide Area Network (WAN), the internet, a virtual network, a Virtual Private Network (VPN), an intranet, an extranet, a blockchain network, a Public Switched Telephone Network (PSTN), an infrared network, a wireless network (e.g., bluetooth, WIFI), and/or any combination of these and/or other networks.

The server 120 may include one or more general purpose computers, special purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-end servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and/or combination. The server 120 may include one or more virtual machines running a virtual operating system, or other computing architecture that involves virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain virtual storage devices of the server). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

The computing units in server 120 may run one or more operating systems including any of the operating systems described above as well as any commercially available server operating systems. Server 120 may also run any of a variety of additional server applications and/or middle tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

In some implementations, server 120 may include one or more applications to analyze and consolidate data feeds and/or event updates received from users of

client devices

101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and/or real-time events via one or more display devices of

client devices

101, 102, 103, 104, 105, and 106.

In some implementations, the server 120 may be a server of a distributed system or a server that incorporates a blockchain. The server 120 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. The cloud server is a host product in a cloud computing service system, so as to solve the defects of large management difficulty and weak service expansibility in the traditional physical host and virtual private server (VPS, virtual Private Server) service.

The system 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of databases 130 may be used to store information such as audio files and video files. Database 130 may reside in various locations. For example, the database used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. Database 130 may be of different categories. In some embodiments, the database used by server 120 may be, for example, a relational database. One or more of these databases may store, update, and retrieve the databases and data from the databases in response to the commands.

In some embodiments, one or more of databases 130 may also be used by applications to store application data. The databases used by the application may be different types of databases, such as key value stores, object stores, or conventional stores supported by the file system.

The system 100 of fig. 1 may be configured and operated in various ways to enable application of the various methods and apparatus described in accordance with the present disclosure.

Fig. 2 shows a flow chart of a data processing method 200 according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the method 200 includes:

step S201, a first matrix and a second matrix are obtained, wherein each element in the first matrix and the second matrix is in a first data format, and the first data format comprises a floating point type;

step S202, dividing the first matrix into a plurality of first sub-matrices, wherein the absolute value of an element in each first sub-matrix in the plurality of first sub-matrices meets a preset condition;

step S203, for each first sub-matrix in the plurality of first sub-matrices, determining a first sub-element with the largest absolute value in the first sub-matrix, and recording the largest absolute value of the first sub-element as a first sub-matrix maximum value Max1;

step S204, converting the element into a conversion element of a second data format based on the first sub-matrix maximum Max1, the second data format comprising n mantissa digits, n being an integer greater than 1, and wherein each element in the first sub-matrix is mapped to [0,2 ] based on the first sub-matrix maximum Max1 ⁿ ]A section to determine the tail number of the conversion element corresponding to the element;

Thus, the first matrix is divided into a plurality of first sub-matrices by step S202, each element stored in the first data format in the first matrix is converted into a conversion element stored in the second data format by step S204, respectively, and data format conversion can be performed based on each sub-matrix maximum value to obtain a corresponding conversion element of higher precision for each element.

Step S205, dividing the second matrix into a plurality of second sub-matrices, wherein the absolute value of an element in each of the plurality of second sub-matrices meets a preset condition;

step S206, for each second sub-matrix in the plurality of second sub-matrices, determining a second sub-element with the largest absolute value in the second sub-matrix, and recording the largest absolute value of the second sub-element as a second sub-matrix maximum value Max2;

step S207, mapping each element in the second sub-matrix to [0,2 ] based on the maximum value Max2 of the second sub-matrix ⁿ ]A section to convert the element into a conversion element in a second data format; and

step S208, calculating the product of the first matrix and the second matrix based on the conversion elements corresponding to each element in the first matrix and the second matrix.

Thus, the second matrix is divided into a plurality of second sub-matrices by step S205, each element stored in the first data format in the second matrix is converted into a conversion element stored in the second data format by step S207, respectively, and data format conversion can be performed based on each sub-matrix maximum value to obtain a corresponding conversion element of higher precision for each element.

The conversion elements corresponding to each element in the first matrix and the second matrix are used for calculation, so that the floating-point type matrix calculation can be converted into the fixed-point type matrix calculation, the difficulty of matrix calculation is effectively reduced, the calculation efficiency is improved, and meanwhile, the conversion elements obtained based on the maximum value of each submatrix can represent higher numerical precision, so that the calculation efficiency is improved, and meanwhile, the calculation precision is ensured.

In some examples, the second data format further includes 1 sign bit and at least 1 exponent bit, thereby enabling improved accuracy of the numerical representation. In one example, the first data format and the second data format each have 16 bits. Therefore, the product operation of the traditional floating point type data such as fp16, bfoat 16 and the like in the first data format is converted into fixed point calculation on 14 mantissas by providing the second data format which has 16 bits of data and 14 digits of data, so that the method is simpler in hardware realization, higher in efficiency, can approach to integer type int16 with the same digits in energy efficiency, can reduce the use of hardware resources relative to the calculation types such as fp16, bfoat 16 and the like, and improves the peak performance of the artificial intelligent chip.

For convenience of description, description will be made below taking an example in which the second data format contains 16-bit data and the number of mantissa bits n is 14. It will be appreciated that the present disclosure is not limited to 16-bit data conversion, but may be used for conversion of 32-bit single-precision floating point numbers or 64-bit double-precision floating point numbers to convert floating point operations including exponent operations to fixed point operations that do not include exponents, thereby improving operation efficiency and saving hardware computing resources.

According to some embodiments, according to the preset condition, the range of absolute values of elements in each of the plurality of first sub-matrices is less than a preset threshold. Thereby, the accuracy of the converted data can be ensured in the case where the data format conversion is performed based on the maximum value of each data block.

In some examples, the preset condition may also include other content, for example, it may be defined that a variance of absolute values of elements in each of the plurality of first sub-matrices is less than a preset threshold. The present disclosure is not limited as long as it can achieve that the numerical distribution of the plurality of elements in each data block satisfies the required uniformity. In some examples, the dividing conditions of the first sub-matrix and the second sub-matrix may be manually determined according to the calculation accuracy requirement and the numerical values of the respective elements in the first matrix and the second matrix.

Fig. 3 illustrates a flow chart of a method of converting elements in a matrix into converted elements, according to an embodiment of the present disclosure. As shown in fig. 3, in some embodiments, the second data format further includes 1 exponent bit, and converting the element into a corresponding conversion element based on the first submatrix maximum value Max1 in step S204 includes: step S301, based on the first sub-matrix maximum value Max1, determining a first partition point to divide the interval [0, max1 ]]Dividing into two subintervals; step S302, for each element in the first submatrix, determining the index bit of the conversion element corresponding to the element based on the subinterval in which the element is located, and mapping the element to [0,2 ] ⁿ ]To determine the mantissa digit of the conversion element to which the element corresponds. Thus, the distribution range of each element in the first sub-matrix, i.e. [0, max1 ], can be determined by determining the maximum value Max1 of the absolute values of the elements in the sub-matrix]. The distribution range is further segmented by determining the segmentation points, so that mapping calculation is performed according to subintervals in which each element falls, the distribution range of the data is divided more carefully, and therefore higher calculation accuracy is obtained.

According to some embodiments, the determining is based on the first sub-matrix maximum Max1Dividing the points to divide the interval [0, max1 ]]The division into two subintervals includes: determining the first division point as based on the first sub-matrix maximum value Max1

To divide the interval [0, max1 ]]Divided into two subintervals->

And->

Taking n as 14 as an example, i.e. when the second data format is 16-bit data with 14 mantissas, each element in the first sub-matrix is mapped to [0,2 ] ¹⁴ ]To represent the absolute value of each element with 14 mantissa digits. The distribution interval of the elements in the first sub-matrix [0, max1 ]]Divided into 2 ¹⁴ Parts and at the position of the first part

As the dividing point, the distribution interval [0, max1 ]]Divided into two subintervals->

And->

So that the data represented in the second data format has at least +.>

Is a precision of (a). Therefore, the element values in the matrix to be calculated can be more accurately represented by using the second data format comprising 14 mantissa digits, and the calculation accuracy is improved.

According to some embodiments, for each element in the first sub-matrix, the index bit of the conversion element corresponding to the element is determined based on the subinterval in which the element is located, and the element is mapped to [0,2 ] ⁿ ]Determining mantissa bits of a conversion element corresponding to the element includes: for each element in the first sub-matrix, determining an absolute value a of the element; responsive to determining that the element is located in a subinterval

In, the index bit of the conversion element corresponding to the element is determined to be 0, and the element is mapped to [0,2 ] ⁿ ]To determine the mantissa digit of the conversion element corresponding to the element as +.>

Or in response to determining that the element is located in the subinterval +.>

In, the index bit of the conversion element corresponding to the element is determined to be 1, and the element is mapped to [0,2 ] ⁿ ]To determine that the element is converted into the tail number of the corresponding conversion element as

Further, by determining the subinterval in which the element is located, the distribution range of the element can be determined more accurately, so that higher calculation accuracy is obtained. When it is determined that the element falls into

When the interval has smaller value distribution, the +.>

This interval is again divided into 2 ¹⁴ Parts, make->

The accuracy in the interval can be improved to +.>

And number ofElements with larger values fall into subintervals with larger ranges +.>

In (a) still have->

Is a precision of (a).

According to some embodiments, the method 200 further comprises: for each element in the first matrix and each element in the second matrix, determining a recovery factor corresponding to the element, wherein the recovery factor satisfies the following condition: multiplying the conversion element corresponding to the element by the recovery factor corresponding to the element is equal to the absolute value of the element, and calculating the product of the first matrix and the second matrix based on the conversion element respectively corresponding to each element in the first matrix and the second matrix in step S208 includes: and calculating the product of the first matrix and the second matrix as a third matrix based on the conversion elements respectively corresponding to each element in the first matrix and the second matrix, wherein the absolute value of each element in the third matrix is equal to the mantissa bit of the conversion element of the third element corresponding to the element in the first matrix multiplied by the mantissa bit of the conversion element of the fourth element corresponding to the element in the second matrix multiplied by the recovery factor corresponding to the third element multiplied by the recovery factor corresponding to the fourth element.

It will be appreciated that the data processing method 200 is used to convert a conventional floating point data type into a new data type with n mantissa bits, so as to convert a matrix calculation of the floating point type into a fixed point calculation, thereby reducing the complexity of calculation and achieving the purpose of saving hardware resources. After the conversion to the fixed point to perform matrix calculation, the calculation result still needs to be converted into the original data type, so that the conversion process is agnostic at the user angle, and the user experience is improved.

The process of converting the matrix calculation result into the original data type requires the above-mentioned recovery factor to be implemented. Specifically, when converting an element of a first data format into a second data formatWhen converting an element of the formula, the element is mapped to [0,2 ] by multiplying the absolute value of the element by a factor ⁿ ]Converting the matrix calculation result to the original data type may be accomplished by multiplying the calculation result by the inverse of this factor, which is the recovery factor. The recovery factor is calculated by satisfying the following condition: the conversion element corresponding to the element is multiplied by the recovery factor corresponding to the element to be equal to the absolute value of the element, so as to realize the conversion of the matrix calculation result into the original data type.

According to some embodiments, the first data format and the second data format further comprise 1 sign bit, and the sign bit of each element in the third matrix is an exclusive or value of the sign bit of the third element corresponding to the element in the first matrix and the sign bit of the fourth element corresponding to the element in the second matrix. Therefore, the matrix calculation of the floating point number is converted into the fixed point calculation of more tail bits, the calculation complexity is reduced, and the calculation efficiency is improved. Due to the increase of the mantissa digits, the accuracy of the data is also improved. Meanwhile, through the process, the automatic conversion of the data is realized, the calculation result can be automatically converted back to the original data type, the user can not feel the data type and the conversion process of the data which are specifically used in the calculation, and the calculation result and the calculation process with higher precision and higher efficiency can be obtained.

According to another aspect of the present disclosure, a data processing apparatus is provided. Fig. 4 shows a block diagram of a data processing apparatus 400 according to an exemplary embodiment of the present disclosure. As shown in fig. 4, the apparatus 400 includes:

a first obtaining unit 401 configured to obtain a first matrix and a second matrix, where each element in the first matrix and the second matrix is in a first data format, and the first data format includes a floating point type;

A dividing unit 402 configured to divide the first matrix into a plurality of first sub-matrices, wherein an absolute value of an element in each of the plurality of first sub-matrices satisfies a preset condition;

a first determining unit 403 configured to determine, for each of the plurality of first sub-matrices, a first sub-element having the largest absolute value among the first sub-matrices, and record the largest absolute value of the first sub-element as a first sub-matrix maximum value Max1;

a conversion unit 404 configured to convert the element into a conversion element of a second data format based on the first sub-matrix maximum Max1, the second data format comprising n mantissa digits, n being an integer greater than 1, and wherein each element in the first sub-matrix is mapped to [0,2 ] based on the first sub-matrix maximum Max1 ⁿ ]Interval to determine the mantissa bit of the conversion element corresponding to the element,

wherein the dividing unit 401 is further configured to divide the second matrix into a plurality of second sub-matrices, wherein the absolute value of an element in each of the plurality of second sub-matrices satisfies a preset condition,

the first determining unit 402 is further configured to determine, for each of the plurality of second sub-matrices, a second sub-element of the second sub-matrix having the largest absolute value, and to record the largest absolute value of the second sub-element as a second sub-matrix maximum value Max2,

The conversion unit 403 is further configured to map each element in the second sub-matrix to [0,2 ] based on the second sub-matrix maximum Max2 ⁿ ]A section to convert the element into a conversion element in a second data format; and

a calculation unit 405 configured to calculate a product of the first matrix and the second matrix based on the conversion element corresponding to each element in the first matrix and the second matrix, respectively.

According to some embodiments, according to the preset condition, the range of absolute values of elements in each of the plurality of first sub-matrices is less than a preset threshold.

According to some embodiments, the second data format further comprises 1 index bit, the conversion unit comprises: a first determination subunit configured to, based on the first sub-momentMatrix maximum value Max1, first division point is determined to divide interval 0, max1]Dividing into two subintervals; and a second determination subunit configured to determine, for each element in the first submatrix, an index bit of a conversion element corresponding to the element based on a subinterval in which the element is located, and map the element to [0,2 ] ⁿ ]To determine the mantissa digit of the conversion element to which the element corresponds.

According to some embodiments, the first determination subunit is configured to:

determining the first division point as based on the first sub-matrix maximum value Max1

To divide the interval [0, max1 ]]Divided into two subintervals->

And->

According to some embodiments, the second determination subunit is configured to: for each element in the first sub-matrix, determining an absolute value a of the element; responsive to determining that the element is located in a subinterval

In, the index of the conversion element corresponding to the element is determinedA digit of 1 and maps the element to [0,2 ] ⁿ ]To determine that the element is converted into the tail number of the corresponding conversion element as

According to some embodiments, the apparatus 400 further comprises: a second determining unit configured to determine, for each element in the first matrix and each element in the second matrix, a recovery factor corresponding to the element, wherein the recovery factor satisfies the following condition: the conversion element corresponding to the element multiplied by the recovery factor corresponding to the element is equal to the absolute value of the element, and wherein the computing unit is configured to: and calculating the product of the first matrix and the second matrix as a third matrix based on the conversion elements respectively corresponding to each element in the first matrix and the second matrix, wherein the absolute value of each element in the third matrix is equal to the mantissa bit of the conversion element of the third element corresponding to the element in the first matrix multiplied by the mantissa bit of the conversion element of the fourth element corresponding to the element in the second matrix multiplied by the recovery factor corresponding to the third element multiplied by the recovery factor corresponding to the fourth element.

According to some embodiments, the first data format and the second data format further comprise 1 sign bit, and the sign bit of each element in the third matrix is an exclusive or value of the sign bit of the third element corresponding to the element in the first matrix and the sign bit of the fourth element corresponding to the element in the second matrix.

According to another aspect of the present disclosure, there is also provided a chip including the data processing apparatus 400 as described above.

According to another aspect of the present disclosure, there is also provided an electronic apparatus including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the data processing method described above.

According to another aspect of the present disclosure, there is also provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the above-described data processing method.

According to another aspect of the present disclosure, there is also provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the above-mentioned data processing method.

Referring to fig. 5, a block diagram of an electronic device 500 that may be a server or a client of the present disclosure, which is an example of a hardware device that may be applied to aspects of the present disclosure, will now be described. Electronic devices are intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 5, the apparatus 500 includes a computing unit 501 that can perform various suitable actions and processes according to a computer program stored in a Read Only Memory (ROM) 502 or a computer program loaded from a storage unit 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, ROM 502, and RAM 503 are connected to each other by a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.

Various components in the device 500 are connected to the I/O interface 505, including: an input unit 506, an output unit 507, a storage unit 508, and a communication unit 509. The input unit 506 may be any type of device capable of inputting information to the device 500, the input unit 506 may receive input numeric or character information and generate key signal inputs related to user settings and/or function control of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and/or a remote control. The output unit 507 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, video/audio output terminals, vibrators, and/or printers. Storage unit 508 may include, but is not limited to, magnetic disks, optical disks. The communication unit 509 allows the device 500 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers and/or chipsets, such as bluetooth (TM) devices, 802.11 devices, wiFi devices, wiMax devices, cellular communication devices, and/or the like.

The computing unit 501 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 501 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the respective methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 500 via the ROM 502 and/or the communication unit 509. When a computer program is loaded into RAM 503 and executed by computing unit 501, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the method by any other suitable means (e.g. by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), the internet, and blockchain networks.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

Although embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it is to be understood that the foregoing methods, systems, and apparatus are merely exemplary embodiments or examples, and that the scope of the present invention is not limited by these embodiments or examples but only by the claims following the grant and their equivalents. Various elements of the embodiments or examples may be omitted or replaced with equivalent elements thereof. Furthermore, the steps may be performed in a different order than described in the present disclosure. Further, various elements of the embodiments or examples may be combined in various ways. It is important that as technology evolves, many of the elements described herein may be replaced by equivalent elements that appear after the disclosure.

Claims

1. A data processing method, comprising:

acquiring a first matrix and a second matrix, wherein each element in the first matrix and the second matrix is in a first data format, and the first data format comprises a floating point type;

Dividing the first matrix into a plurality of first sub-matrices, wherein the absolute value of an element in each of the plurality of first sub-matrices meets a preset condition;

for each first sub-matrix of the plurality of first sub-matrices,

determining a first sub-element with the largest absolute value in the first sub-matrix, and marking the largest absolute value of the first sub-element as a first sub-matrix maximum value Max1;

converting the element into a conversion element of a second data format based on the first submatrix maximum value Max1, theThe second data format comprises n mantissa bits, n being an integer greater than 1, and wherein each element in the first sub-matrix is mapped to [0,2 ] based on the first sub-matrix maximum value Max1 ⁿ ]A section to determine the tail number of the conversion element corresponding to the element;

dividing the second matrix into a plurality of second sub-matrices, wherein the absolute value of an element in each of the plurality of second sub-matrices meets a preset condition;

for each second sub-matrix of the plurality of second sub-matrices,

determining a second sub-element with the largest absolute value in the second sub-matrix, and marking the largest absolute value of the second sub-element as a second sub-matrix maximum value Max2;

Mapping each element in the second sub-matrix to [0,2 ] based on the second sub-matrix maximum Max2 ⁿ ]A section to convert the element into a conversion element in a second data format; and

and calculating the product of the first matrix and the second matrix based on the conversion elements respectively corresponding to each element in the first matrix and the second matrix.

2. The method of claim 1, wherein a range of absolute values of elements in each of the plurality of first sub-matrices is less than a preset threshold according to the preset condition.

3. The method of claim 1 or 2, wherein the second data format further comprises 1 exponent bit, and the converting the element into a corresponding conversion element based on the first submatrix maximum value Max1 comprises:

determining a first division point based on the first submatrix maximum value Max1 to divide the interval [0, max1] into two subintervals; and

for each element in the first submatrix, determining the index bit of the conversion element corresponding to the element based on the subinterval of the element, and mapping the element to [0,2 ] ⁿ ]To ensureAnd determining the tail number of the conversion element corresponding to the element.

4. A method according to claim 3, wherein said determining a partition point to partition the interval [0, max1] into two sub-intervals based on said first sub-matrix maximum Max1 comprises:

To divide the interval [0, max1]]Divided into two subintervals->

And->

5. The method of claim 4, wherein, for each element in the first submatrix, the exponent bits of the transformed element corresponding to the element are determined based on the subinterval in which the element is located, and the element is mapped to [0,2 ] ⁿ ]Determining mantissa bits of a conversion element corresponding to the element includes:

for each element in the first sub-matrix,

determining an absolute value a of the element;

responsive to determining that the element is located in a subinterval

Or (b)

Responsive to determining that the element is located in a subinterval

6. The method of any one of claims 1-5, further comprising:

for each element in the first matrix and each element in the second matrix, determining a recovery factor corresponding to the element, wherein the recovery factor satisfies the following condition:

the conversion element corresponding to the element multiplied by the recovery factor corresponding to the element is equal to the absolute value of the element,

and wherein said calculating a product of the first matrix and the second matrix based on the conversion elements respectively corresponding to each element in the first matrix and the second matrix comprises:

and calculating the product of the first matrix and the second matrix as a third matrix based on the conversion elements respectively corresponding to each element in the first matrix and the second matrix, wherein the absolute value of each element in the third matrix is equal to the mantissa bit of the conversion element of the third element corresponding to the element in the first matrix multiplied by the mantissa bit of the conversion element of the fourth element corresponding to the element in the second matrix multiplied by the recovery factor corresponding to the third element multiplied by the recovery factor corresponding to the fourth element.

7. The method of claim 6, wherein the first data format and the second data format further comprise 1 sign bit, the sign bit of each element in the third matrix being an exclusive or value of the sign bit of the corresponding third element of the element in the first matrix and the sign bit of the corresponding fourth element of the element in the second matrix.

8. A data processing apparatus comprising:

a first acquisition unit configured to acquire a first matrix and a second matrix, wherein each element in the first matrix and the second matrix is in a first data format, and the first data format comprises a floating point type;

a dividing unit configured to divide the first matrix into a plurality of first sub-matrices, wherein an absolute value of an element in each of the plurality of first sub-matrices satisfies a preset condition;

a first determining unit configured to determine, for each of the plurality of first sub-matrices, a first sub-element having a largest absolute value among the first sub-matrices, and record the largest absolute value of the first sub-element as a first sub-matrix maximum value Max1;

a conversion unit configured to convert the element into a conversion element of a second data format based on the first sub-matrix maximum Max1, the second data format comprising n mantissa bits, n being an integer greater than 1, and wherein each element in the first sub-matrix is mapped to [0,2 ] based on the first sub-matrix maximum Max1 ⁿ ]Interval to determine the mantissa bit of the conversion element corresponding to the element,

Wherein the dividing unit is further configured to divide the second matrix into a plurality of second sub-matrices, wherein an absolute value of an element in each of the plurality of second sub-matrices satisfies a preset condition,

the first determining unit is further configured to determine, for each of the plurality of second sub-matrices, a second sub-element of the second sub-matrix having the largest absolute value, and to record the largest absolute value of the second sub-element as a second sub-matrix maximum value Max2,

the conversion unit is further configured to map each element in the second sub-matrix to [0,2 ] based on the second sub-matrix maximum Max2 ⁿ ]A section to convert the element into a conversion element in a second data format; and

and a calculation unit configured to calculate a product of the first matrix and the second matrix based on the conversion element to which each element in the first matrix and the second matrix corresponds, respectively.

9. The apparatus of claim 8, wherein a range of absolute values of elements in each of the plurality of first sub-matrices is less than a preset threshold according to the preset condition.

10. The apparatus of claim 8 or 9, wherein the second data format further comprises 1 exponent bit, the conversion unit comprising:

A first determination subunit configured to determine a first division point to divide the section [0, max1] into two sub-sections based on the first sub-matrix maximum value Max 1; and

a second determination subunit configured to determine, for each element in the first submatrix, an index bit of a conversion element corresponding to the element based on a subinterval in which the element is located, and map the element to [0,2 ] ⁿ ]To determine the mantissa digit of the conversion element to which the element corresponds.

11. The apparatus of claim 10, wherein the first determination subunit is configured to:

To divide the interval [0, max1]]Divided into two subintervals->

And->

12. The apparatus of claim 11, wherein the second determination subunit is configured to:

for each element in the first sub-matrix,

determining an absolute value a of the element;

responsive to determining that the element is located in a subinterval

Or (b)

Responsive to determining that the element is located in a subinterval

13. The apparatus of any of claims 8-12, further comprising:

a second determining unit configured to determine, for each element in the first matrix and each element in the second matrix, a recovery factor corresponding to the element, wherein the recovery factor satisfies the following condition:

and wherein the computing unit is configured to:

14. The apparatus of claim 13, wherein the first data format and the second data format further comprise 1 sign bit, the sign bit of each element in the third matrix being an exclusive or value of the sign bit of a corresponding third element for the element in the first matrix and the sign bit of a corresponding fourth element for the element in the second matrix.

15. A chip comprising the apparatus of any one of claims 8-14.

16. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the method comprises the steps of

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

17. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-7.

18. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method according to any of claims 1-7.