CN116015250B - Improved relaxation oscillator - Google Patents
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- CN116015250B CN116015250B CN202111232764.XA CN202111232764A CN116015250B CN 116015250 B CN116015250 B CN 116015250B CN 202111232764 A CN202111232764 A CN 202111232764A CN 116015250 B CN116015250 B CN 116015250B
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Abstract
An improved relaxation oscillator, characterized by: the oscillator comprises a comparator; wherein the comparator is connected with a control signal and based on the control signalThe input signal in the interval of level switching of the non-overlapping clock signals realizes the recovery of the output voltage of the comparator. The method is simple, few elements are added in the circuit, the control signal is accurate, the output of the comparator can be effectively controlled in the period of unstable output of the comparator, and meanwhile, the working state of the comparator in the normal period is not influenced.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to an improved relaxation oscillator.
Background
Currently, relaxation oscillators are widely used in various integrated circuits. In general, a relaxation oscillator can be controlled with respect to a comparator inside thereof based on a control signal, and oscillation is achieved by a flipping process performed by the comparator. In the prior art, the negative input voltage of the comparator is a stable reference voltage provided by a resistor, and the positive input voltage is a non-overlapping clock signalAnd/>Provided in combination. According to non-overlapping clock signals/>And/>The two different amplitude levels V 1 and V 2 are alternately input into the non-inverting input of the comparator. Thus, the two different levels V 1、V2 are compared with the negative phase input voltage V ref, respectively, to achieve a constant flip of the comparator.
However, the relaxation oscillator in the prior art has a serious defect. That is, due to the clock signalAndIs non-overlapping, and therefore, there must be a brief non-overlapping time, so that two clock signals/>And/>The values of (2) are all low. And if the clock signal/>And/>When the values of the two PMOS transistors are low, the PMOS transistors at the positive and negative phase input ends of the comparator are in a conducting state, the drain states of the two PMOS transistors in the comparator are not fixed, the drain voltages of the two PMOS transistors are dithered in the period, and the fixed and stable current injection still cannot be maintained after the dithering. This makes the output voltage of the comparator impossible to determine, and thus may cause the output voltage of the comparator to be unnecessarily inverted, resulting in an error in the oscillation signal output from the relaxation oscillator.
In order to avoid this, there is a need for an improved relaxation oscillator.
Disclosure of Invention
To solve the deficiencies of the prior art, it is an object of the present invention to provide an improved relaxation oscillator for controlling the output voltage of a comparator in a section where non-overlapping clock signals are level-switched by adding a control signal to the comparator.
The invention adopts the following technical scheme.
An improved relaxation oscillator, wherein the oscillator comprises a comparator; the comparator is connected with the control signal and based on the control signalThe input signal in the section where the non-overlapping clock signals are level switched achieves recovery of the comparator output voltage.
Preferably, the recovery of the comparator output voltage includes: the output voltage V CLA of the comparator is not continuously in the low-level state; the output voltage V CLA of the comparator is based on the control signal in the interval of level switching of the non-overlapping clock signalsThe control of (2) is restored to the stable voltage of the non-overlapping clock signal before the level switching is performed.
Preferably, the control signalNon-overlapping clock signal/>, based on relaxation oscillatorAnd/>Obtained by nor operation.
Preferably, the comparator comprises a control current source, a first control end, a second control end and a third control end; one end of the control current source is connected with the power supply voltage, and the other end of the control current source is connected with the grid electrode and the drain electrode of the NMOS tube of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator through the first control end; one end of the second control end is connected with the drain electrode of the PMOS tube at the negative phase input end in the comparator, and the other end of the second control end is grounded; and one end of the third control end is connected with the power supply voltage, and the other end of the third control end is respectively connected with the input end of the inverter in the comparator and one end of the output current source I CLA.
Preferably, the comparator comprises an input current source I CMP, a positive-phase input end PMOS tube and an NMOS tube, a negative-phase input end PMOS tube and an NMOS tube, an output current source I CLA, an output power tube M CLA and an inverter; one end of the input current source I CMP is connected with the power supply voltage, and the other end of the input current source I CMP is respectively connected with the source electrode of the positive-phase input end PMOS tube and the source electrode of the negative-phase input end PMOS tube; the grid electrode of the positive phase input end PMOS tube is used as the positive phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the positive phase input end NMOS tube, the grid electrode of the negative phase input end NMOS tube, and the source electrode of the positive phase input end NMOS tube is grounded; the grid electrode of the PMOS tube at the negative phase input end is used as the negative phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the NMOS tube at the negative phase input end and the grid electrode of the output power tube M CLA, and the source electrode of the NMOS tube at the negative phase input end is grounded; one end of the output current source I CLA is connected with the power supply voltage, the other end is connected with the input end of the inverter and the drain electrode of the output power tube M CLA, the source electrode of the output power tube M CLA is grounded, and the output end of the inverter is used as the output end of the comparator.
Preferably, when the control signalWhen the voltage is in a high level state, the control current source and the first control end stabilize the grid voltages of NMOS tubes of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator.
Preferably, the second control terminal is connected with the control signalWhen the voltage is in the high level state, the gate voltage of the output power transistor M CLA is controlled to be in the low level state.
Preferably, the third control terminal is connected with the control signalWhen the voltage is in a high level state, the input end voltage of the control inverter is the power supply voltage.
Preferably, when the control signalIn the low state, the first to third control terminals disconnect the control of the comparator.
Preferably, the first to third control terminals are closed when the non-overlapping clock signals are in the level-switching interval; when the non-overlapping clock signals are not in the level switching interval, the first to third control terminals are disconnected.
Compared with the prior art, the improved relaxation oscillator has the advantages that the control signal can be added into the comparator to control the output voltage of the comparator in the interval of level switching of non-overlapping clock signals. The method is simple, few elements are added in the circuit, the control signal is accurate, the output of the comparator can be effectively controlled in the period of unstable output of the comparator, and meanwhile, the working state of the comparator in the normal period is not influenced.
The beneficial effects of the invention also include:
1. The method effectively controls the output voltage of the comparator, thereby preventing the unnecessary overturn of the output voltage of the comparator in an unstable interval and ensuring the reliability and the accuracy of the output signal of the relaxation oscillator.
2. The method of the invention can quickly recover the output voltage, reduce the recovery time of the output voltage and ensure that the output voltage is more stable.
Drawings
FIG. 1 is a schematic diagram of a prior art relaxation oscillator;
FIG. 2 is a schematic diagram showing a circuit structure of a comparator in a relaxation oscillator according to the prior art;
FIG. 3 is a schematic diagram of a voltage curve of a comparator circuit of the prior art under normal operation of a relaxation oscillator;
FIG. 4 is a schematic diagram of a voltage curve of a comparator in case of false inversion under abnormal operation of a relaxation oscillator in the prior art;
FIG. 5 is a schematic diagram of a circuit configuration of an improved relaxation oscillator of the present invention;
FIG. 6 is a schematic diagram of the voltage curve of the comparator circuit of the improved relaxation oscillator under normal operation;
fig. 7 is a schematic diagram of a voltage curve of a comparator circuit under non-overlapping clock intervals for normal operation of an improved relaxation oscillator according to the present invention.
Detailed Description
The application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and are not intended to limit the scope of the present application.
Fig. 1 is a schematic circuit diagram of a relaxation oscillator in the prior art. As shown in fig. 1, a relaxation oscillator commonly used in the prior art generally includes a comparator, a control circuit at an input of the comparator, and a logic circuit at an output of the comparator. The circuit signal at the non-inverting input of the comparator input can typically be controlled based on the alternating switching of two different voltages V 1 and V 2.
Specifically, a current source I 1, a capacitor C 1 and a control switchAnd/>A first branch is formed for providing a first voltage V 1 to the comparator, and a current source I 2, a capacitor C 2 and a control switch/>And/>A second branch is formed to provide a second voltage V 2 to the comparator.
In the invention, the first voltage V 1 and the second voltage V 2 can be respectively based on a control switchAnd/>An alternate input to the comparator is achieved and compared with the negative input voltage V mn of the comparator.
It can be seen that the comparator plays an essential role in the overall oscillator and can be used to determine the difference between the voltages at the inputs and to determine the switching time of the oscillator output.
Fig. 2 is a schematic circuit diagram of a comparator in a relaxation oscillator according to the prior art. As shown in fig. 2, the comparator is operated with the current of current source I cmp supplied by the amplifier current and the current of current source I cla supplied by the portion of the amplifier that is Class-a. When two non-overlapping clock signalsAnd/>Meanwhile, when the circuit is in a low level state, obvious jitter can occur to V cnp in the circuit, and stable current injection can not be maintained after the jitter. Thus, in the non-overlapping state of the clocks, the voltages at both points V np and V nn are unstable.
The non-overlapping clock signals in the present invention refer to overlapping states in which two clock signals are not at the same time high level in order to avoid an output error of the comparator. That is, in order to prevent this from happening, the falling edge of one clock signal is positioned before the rising edge of the other clock signal, so that the two signals do not overlap at a high level by providing a very short non-overlapping period between the falling edge of one signal and the rising edge of the other signal. Hereinafter, for this very short non-overlapping period, a non-overlapping section is simply used for description.
Fig. 3 is a schematic diagram of a voltage curve of a comparator circuit of the prior art under normal operation of a relaxation oscillator. As shown in fig. 3, the unstable states of the two voltages may cause V np to reach or exceed the threshold start voltage of the output power transistor M CLA again during the ramp-up process. When V np is greater than the threshold start voltage of the power tube, the output power tube is turned on, the energy of the voltage V CLA is led out to the ground through the source leakage current of the power tube, the voltage V CLA is set to 0, and after passing through the inverter, a rising edge is generated in the output voltage V o, and the high level and the low level are turned over. After the voltage switching is completed in V mp along with the end of the non-overlapping interval, the voltage is stabilized on V 1 or V 2, at this time, V np gradually drops along with the conduction of the two mirror NMOS transistors, the output power transistor M cla is not turned on any more, at this time, V CLA is restored to the voltage state of Class-a, and a falling edge is generated by the output V o.
Typically, when the clock signal is at the end of one or half of a cycle, as the V mp voltage signal increases before entering the non-overlapping region by the falling edge, V np in the comparator will gradually increase from a low state when the V mp voltage is higher than V mn, thereby rendering the M CLA tube conductive and reducing the voltage V CLA.
Fig. 4 is a schematic diagram of a voltage curve when a comparator is turned over by mistake under an abnormal operation condition of a relaxation oscillator in the prior art. As shown in fig. 4, after the two clock signals enter the non-overlapping interval, the voltage of V np is in an uncertain jitter state, and at this time, if the voltage of V np is continuously in a higher state, the M CLA tube is always turned on, which results in that the voltage V CLA is always in a low level state and cannot be raised. Even when the clock signal is switched so that the voltage of V mp rises again, the power tube M CLA takes a certain time to recover the off state and rise the voltage V cla again.
In addition, since the states of V np and V nn cannot be determined in the non-overlapping interval, if V np is excessively dithered due to an uncertainty factor such as clock feedthrough during this period, V np may occur to be lower than the threshold voltage of the output power transistor M CLA, at which time the output power transistor may be turned from the on state to the off state, the voltage V CLA increases, and the output voltage V o turns. In this case, the output voltage V o may be unnecessarily inverted a plurality of times due to the unstable state of V np, greatly reducing the stability and accuracy of the output signal of the oscillator.
In view of the above, the present invention provides an improved relaxation oscillator capable of reducing the degree of instability of the V CLA output state and greatly reducing the time for which V CLA is at a low level by improving the operation state of the comparator in a non-overlapping section.
Fig. 5 is a schematic circuit diagram of an improved relaxation oscillator according to the present invention. As shown in fig. 5, an improved relaxation oscillator, wherein the oscillator includes a comparator; the comparator is connected with the control signal and based on the control signalThe input signal in the section where the non-overlapping clock signals are level switched achieves recovery of the comparator output voltage.
It will be appreciated that in the present invention, the general structure of the oscillator is similar to that of the prior art, and the comparison of V 1、V2 and V ref is achieved by providing voltages V 1 and V 2, which are alternately switched with clock cycles, to the positive input of the comparator, and providing a stable reference voltage V ref to the negative input of the comparator, and generating an oscillating output signal.
Unlike the oscillator in the prior art, the internal structure of the comparator is improved, and the prior comparator cannot realize stable output in a non-overlapping interval, so that the state of an output signal is uncontrollable, and the output signal of the oscillator is unstable. The comparator is improved, so that the comparator can realize stable output in a non-overlapping interval and quickly restore the output voltage to an original state.
Preferably, the recovery of the comparator output voltage comprises: the output voltage V CLA of the comparator is not continuously in the low-level state; the output voltage V CLA of the comparator is based on the control signal in the interval of level switching of the non-overlapping clock signalsThe control of (2) is restored to the stable voltage of the non-overlapping clock signal before the level switching is performed.
Fig. 6 is a schematic diagram of the voltage curve of the comparator circuit of the improved relaxation oscillator under normal operation. As shown in fig. 6, the voltage state of V CLA in the figure is quickly restored to a high level in the non-overlapping section, so that the output voltage V o is reset to zero again. Compared with the content shown in fig. 3 in the prior art, the circuit of the invention effectively ensures that the output voltage is quickly recovered and greatly improves the accuracy of the output clock pulse when the voltage of V CLA is recovered to the high level after the non-overlapping interval is ended.
Preferably, the control signalNon-overlapping clock signal/>, based on relaxation oscillatorAnd/>Obtained by nor operation.
It can be understood that in the present invention, since the improved partial circuit only controls the output state of the comparator in the non-overlapping interval, and in other signal period intervals, the normal working state of the comparator is not disturbed, therefore, in the present invention, a control signal is adoptedThe identification of non-overlapping intervals is achieved.
Specifically, control signalsIs based on nor gate implementation. In one embodiment of the invention, two non-overlapping clock signals/>, of the relaxation oscillator can be usedAnd/>And performing NOR operation. It will be readily appreciated that the non-overlapping interval is simply two signalsAnd/>The intervals, all in a low state, of the control signal obtained thereby/>Only at/>And/>Can be high only in the low state, and in other time, the control signal/>The values of (2) are all 0. By the method, the identification of the non-overlapping interval is effectively realized.
Preferably, the comparator comprises a control current source, a first control terminal, a second control terminal and a third control terminal; one end of the control current source is connected with the power supply voltage, and the other end of the control current source is connected with the grid electrode and the drain electrode of the NMOS tube of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator through the first control end; one end of the second control end is connected with the drain electrode of the PMOS tube at the negative phase input end in the comparator, and the other end of the second control end is grounded; and one end of the third control end is connected with the power supply voltage, and the other end of the third control end is respectively connected with the input end of the inverter in the comparator and one end of the output current source I CLA.
In the present invention, the control signal described above can be usedTo achieve improved and controlled internal circuitry of the comparator. The specific connection mode of the control signal is shown in fig. 5.
Preferably, the comparator comprises an input current source I CMP, a positive-phase input end PMOS tube and an NMOS tube, a negative-phase input end PMOS tube and an NMOS tube, an output current source I CLA, an output power tube M CLA and an inverter; one end of the input current source I CMP is connected with the power supply voltage, and the other end of the input current source I CMP is respectively connected with the source electrode of the positive-phase input end PMOS tube and the source electrode of the negative-phase input end PMOS tube; the grid electrode of the positive phase input end PMOS tube is used as the positive phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the positive phase input end NMOS tube, the grid electrode of the negative phase input end NMOS tube, and the source electrode of the positive phase input end NMOS tube is grounded; the grid electrode of the PMOS tube at the negative phase input end is used as the negative phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the NMOS tube at the negative phase input end and the grid electrode of the output power tube M CLA, and the source electrode of the NMOS tube at the negative phase input end is grounded; one end of the output current source I CLA is connected with the power supply voltage, the other end is connected with the input end of the inverter and the drain electrode of the output power tube M CLA, the source electrode of the output power tube MCLA is grounded, and the output end of the inverter is used as the output end of the comparator.
It will be appreciated that the circuit configuration of the other parts of the comparator of the present invention is similar to that of the prior art.
Preferably, when the control signalWhen the voltage is in a high level state, the control current source and the first control end stabilize the grid voltages of NMOS tubes of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator.
It can be understood that after the control signal is added to control the internal circuit of the comparator, when the comparator works in a non-overlapping section, the voltage V nn can be controlled by the control current source to ensure the stable state, and when the gate voltage V nn of the NMOS transistor is in the stable state, the voltage state of V np can also be kept stable.
Preferably, the second control terminal is connected with the control signalWhen the voltage is in the high level state, the gate voltage of the output power transistor M CLA is controlled to be in the low level state.
It will be appreciated that the second control terminal of the present invention, when the comparator is in the non-overlapping region, the control signal can connect V np in the circuit to the ground level, so that the voltage of V np is rapidly reduced to 0V. Meanwhile, after the voltage of V np is reduced to 0, the output power tube V CLA can be rapidly turned off from the on state, so that the voltage of V CLA is increased.
Preferably, the third control terminal is connected with the control signalWhen the voltage is in a high level state, the input end voltage of the control inverter is the power supply voltage.
In the present invention, a third control terminal is further included, which is capable of raising the level of V CLA to the state of the power supply voltage in the non-overlapping section, so that the level clock of the output voltage V o outputted through the inverter is maintained at 0V.
Fig. 7 is a schematic diagram of a voltage curve of a comparator circuit under non-overlapping clock intervals for normal operation of an improved relaxation oscillator according to the present invention. As shown in fig. 7, the modified comparator, after a very short time in the non-overlapping region, will decrease the level of V np to 0, while at the same time the voltage V CLA controlled by V np will quickly recover, thus making the clock pulse accurate and short.
Preferably, when the control signalIn the low state, the first to third control terminals disconnect the control of the comparator.
It can be appreciated that the control signal in the present invention is based on the output characteristics of the nor gateThe high level is output only in the non-overlapping section, and is in the low level state in the other sections, so that the switch or the like, such as a switching tube, controlled by the control signal is in the low level state. In this state, the plurality of control terminals remain disconnected, and the comparator is not different from the comparator in the prior art.
Preferably, the first to third control terminals are closed when the non-overlapping clock signals are in the interval of level switching; when the non-overlapping clock signals are not in the level switching interval, the first to third control terminals are disconnected.
The control signal can be switched by a switching element such as a MOS tube, so that the control signal has sensitive response capability and no or less time delay.
Compared with the prior art, the improved relaxation oscillator has the advantages that the control signal can be added into the comparator to control the output voltage of the comparator in the interval of level switching of non-overlapping clock signals. The method is simple, few elements are added in the circuit, the control signal is accurate, the output of the comparator can be effectively controlled in the period of unstable output of the comparator, and meanwhile, the working state of the comparator in the normal period is not influenced.
While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.
Claims (7)
1. An improved relaxation oscillator, characterized by:
The oscillator comprises a comparator; wherein,
The comparator is connected with the control signal and based on the control signalThe input signal in the interval of level switching of the non-overlapped clock signals realizes the recovery of the output voltage of the comparator;
The control signal Non-overlapping clock signal/>, based on the relaxation oscillatorAnd/>Obtained by nor operation;
The oscillator comprises a control current source, a first control end, a second control end and a third control end; wherein,
One end of the control current source is connected with the power supply voltage, and the other end of the control current source is connected with the grid electrode and the drain electrode of the NMOS tube at the positive phase input end and the grid electrode of the NMOS tube at the negative phase input end in the comparator through a first control end; the comparator comprises a positive phase input end and a negative phase input end, and an NMOS tube of the positive phase input end and an NMOS tube of the negative phase input end are mirror images;
One end of the second control end is connected with the drain electrode of the PMOS tube at the negative phase input end in the comparator, and the other end of the second control end is grounded;
One end of the third control end is connected with the power supply voltage, and the other end of the third control end is respectively connected with the input end of the inverter in the comparator and one end of the output current source I CLA;
The comparator also comprises an input current source I CMP, a positive-phase input end PMOS tube and an NMOS tube, a negative-phase input end PMOS tube and an NMOS tube, an output current source I CLA, an output power tube M CLA and an inverter; wherein,
One end of the input current source I CMP is connected with the power supply voltage, and the other end of the input current source I CMP is respectively connected with the source electrode of the positive-phase input end PMOS tube and the source electrode of the negative-phase input end PMOS tube;
the grid electrode of the positive phase input end PMOS tube is used as the positive phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the positive phase input end NMOS tube, the grid electrode of the negative phase input end NMOS tube, and the source electrode of the positive phase input end NMOS tube is grounded;
the grid electrode of the PMOS tube at the negative phase input end is used as the negative phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the NMOS tube at the negative phase input end and the grid electrode of the output power tube M CLA, and the source electrode of the NMOS tube at the negative phase input end is grounded;
One end of the output current source I CLA is connected with the power supply voltage, the other end of the output current source I CLA is connected with the input end of the inverter and the drain electrode of the output power tube M CLA, the source electrode of the output power tube M CLA is grounded, and the output end of the inverter is used as the output end of the comparator.
2. An improved relaxation oscillator as claimed in claim 1, wherein:
The recovery of the comparator output voltage includes: the output voltage V CLA of the comparator is not continuously in a low level state;
The output voltage V CLA of the comparator is based on the control signal in the interval of level switching of non-overlapping clock signals Is restored to a stable voltage of the non-overlapping clock signal before level switching is performed.
3. An improved relaxation oscillator as claimed in claim 2, wherein:
When the control signal And when the voltage is in a high level state, the control current source and the first control end stabilize the grid voltages of NMOS tubes of a positive phase input end and a negative phase input end which are mirror images of each other in the comparator.
4. An improved relaxation oscillator according to claim 3, wherein:
the second control end is arranged on the control signal And when the voltage is in a high level state, controlling the grid voltage of the output power tube M CLA to be in a low level state.
5. An improved relaxation oscillator as claimed in claim 4, wherein:
The third control end is arranged on the control signal And when the voltage is in a high level state, controlling the voltage of the input end of the inverter to be a power supply voltage.
6. An improved relaxation oscillator as claimed in claim 5, wherein:
When the control signal In the low level state, the first to third control terminals disconnect the control of the comparator.
7. An improved relaxation oscillator as claimed in claim 6, wherein:
When the non-overlapping clock signals are in a level switching interval, the first control end to the third control end are closed;
the first to third control terminals are turned off when the non-overlapping clock signals are not within a level-switching interval.
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| CN103546123A (en) * | 2013-11-01 | 2014-01-29 | 东南大学 | High-linearity relaxation oscillator |
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| TWI442682B (en) * | 2010-03-16 | 2014-06-21 | Noveltek Semiconductor Corp | Oscillator having time-variant frequency deviation and related power supply |
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| US9054690B2 (en) * | 2012-08-29 | 2015-06-09 | Analog Devices Global | Chopped oscillator |
| CN107809223B (en) * | 2016-09-08 | 2023-06-09 | 恩智浦美国有限公司 | Low temperature coefficient clock signal generator |
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2021
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| CN103546123A (en) * | 2013-11-01 | 2014-01-29 | 东南大学 | High-linearity relaxation oscillator |
| CN105634445A (en) * | 2015-12-28 | 2016-06-01 | 北京时代民芯科技有限公司 | Frequency-configurable oscillator circuit applied to switching power supply |
| WO2018068700A1 (en) * | 2016-10-11 | 2018-04-19 | 卓捷创芯科技（深圳）有限公司 | Half-duplex rfid oscillation maintaining circuit for generating pulse by comparator |
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