CN115995241A - Memory bank and electronic equipment - Google Patents
Memory bank and electronic equipment Download PDFInfo
- Publication number
- CN115995241A CN115995241A CN202111221738.7A CN202111221738A CN115995241A CN 115995241 A CN115995241 A CN 115995241A CN 202111221738 A CN202111221738 A CN 202111221738A CN 115995241 A CN115995241 A CN 115995241A
- Authority
- CN
- China
- Prior art keywords
- voltage
- circuit
- memory bank
- storage medium
- configuration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
Abstract
The application discloses a memory bank. The memory bank includes: a circuit board; a storage medium disposed on the circuit board; the voltage regulating circuit is arranged on the circuit board and connected with the storage medium, and is used for regulating the input voltage and inputting the regulated first target voltage to the storage medium; the configuration circuit is arranged on the circuit board and connected with the voltage regulating circuit, and circuit parameters of the configuration circuit can be configured to regulate the voltage regulating amplitude of the voltage regulating circuit. The application also discloses electronic equipment. By the mode, the normal working performance of the storage medium can be guaranteed under different working environments.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a memory bank and an electronic device.
Background
In order to meet the requirements of speeding up the operating frequency of DRAM (dynamic random access memory ) particles or enhancing their stability of operation at a specific frequency, it is often necessary to boost the DRAM particles. The booster circuit is generally designed inside the DRAM granule, and the booster circuit needs to be designed together when the DRAM granule is designed, which is costly and cannot be changed. Moreover, the designed boosted DRAM particles can work normally on some platforms, while normal performance cannot be achieved on other platforms.
Disclosure of Invention
The application mainly aims to provide a memory bank and electronic equipment so as to solve the technical problem that the working performance of DRAM particles in different platforms is unstable.
In order to solve the technical problems, a first technical scheme adopted by the application is as follows: a memory bank is provided. The memory bank includes: a circuit board; a storage medium disposed on the circuit board; the voltage regulating circuit is arranged on the circuit board and connected with the storage medium, and is used for regulating the input voltage and inputting the regulated first target voltage to the storage medium; the configuration circuit is arranged on the circuit board and connected with the voltage regulating circuit, and circuit parameters of the configuration circuit can be configured to regulate the voltage regulating amplitude of the voltage regulating circuit.
In order to solve the technical problems, a second technical scheme adopted by the application is as follows: an electronic device is provided. The electronic device comprises a memory bank as described in the first technical solution.
The beneficial effects of this application are: by providing the voltage regulating circuit and the configuration circuit inside the memory bank, the configuration circuit can be configured to adjust the voltage regulating circuit, thereby adjusting the voltage input to the storage medium. For different working environments, the voltage output to the storage medium can be adjusted through the configuration circuit so as to ensure the normal working performance of the storage medium.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first embodiment of a memory bank according to the present application;
FIG. 2 is a schematic diagram of a second embodiment of a memory bank according to the present application;
FIG. 3 is a schematic diagram of a third embodiment of a memory bank according to the present application;
FIG. 4 is a schematic diagram of a fourth embodiment of a memory bank according to the present application;
FIG. 5 is a schematic diagram of a memory bank according to a fifth embodiment of the present application;
FIG. 6 is a schematic diagram of a sixth embodiment of a memory bank according to the present application;
FIG. 7 is a schematic diagram of a seventh embodiment of a memory bank according to the present application;
FIG. 8 is a schematic diagram of an eighth embodiment of a memory bank according to the present application;
FIG. 9 is a schematic diagram of a ninth embodiment of a memory bank according to the present application;
fig. 10 is a schematic structural view of the first embodiment of the electronic device of the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," and the like in this application are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of a memory bank of the present application.
In this embodiment, the memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a voltage regulating circuit 130. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the voltage regulating circuit 130 are all disposed on the circuit board 110. The voltage regulating circuit 130 is connected to the relevant voltage pin to obtain an input voltage, and adjusts the input voltage to obtain a first target voltage, and then inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the voltage regulating circuit 130, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The first target voltage obtained by the voltage regulating circuit 130 can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that may be individually configured to adjust the voltage adjustment amplitude of the voltage regulator circuit 130.
In this embodiment, the voltage regulator circuit 130 obtains the input voltage from the VDD voltage input pin.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of a memory bank of the present application.
In this embodiment, the memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a voltage regulating circuit 130. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the voltage regulating circuit 130 are all disposed on the circuit board 110. The voltage regulating circuit 130 is connected to the relevant voltage pin to obtain an input voltage, and adjusts the input voltage to obtain a first target voltage, and then inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the voltage regulating circuit 130, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The first target voltage obtained by the voltage regulating circuit 130 can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that may be individually configured to adjust the voltage adjustment amplitude of the voltage regulator circuit 130.
In this embodiment, the voltage regulating circuit 130 obtains the input voltage from the VTT voltage input pin.
As shown in fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of a memory bank of the present application.
In this embodiment, the memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a voltage regulating circuit 130. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the voltage regulating circuit 130 are all disposed on the circuit board 110. The voltage regulating circuit 130 is connected to the relevant voltage pin to obtain an input voltage, and adjusts the input voltage to obtain a first target voltage, and then inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the voltage regulating circuit 130, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The first target voltage obtained by the voltage regulating circuit 130 can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that may be individually configured to adjust the voltage adjustment amplitude of the voltage regulator circuit 130.
In this embodiment, the voltage regulator circuit 130 obtains the input voltage from the VRECFA voltage input pin.
As shown in fig. 4, fig. 4 is a schematic structural diagram of a fourth embodiment of a memory bank of the present application.
In this embodiment, the memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a voltage regulating circuit 130. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the voltage regulating circuit 130 are all disposed on the circuit board 110. The voltage regulating circuit 130 is connected to the relevant voltage pin to obtain an input voltage, and adjusts the input voltage to obtain a first target voltage, and then inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the voltage regulating circuit 130, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The first target voltage obtained by the voltage regulating circuit 130 can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that may be individually configured to adjust the voltage adjustment amplitude of the voltage regulator circuit 130.
In this embodiment, the voltage regulating circuit 130 obtains the input voltage from the VPP voltage input pin.
In the above embodiment, the voltage-regulating voltage includes at least one of a voltage-boosting circuit, a voltage-reducing circuit, and a voltage-stabilizing circuit. For specific settings, reference is made to the following examples.
As shown in fig. 5, fig. 5 is a schematic structural diagram of a fifth embodiment of a memory bank of the present application.
In this embodiment, the voltage regulating circuit includes a voltage boosting circuit 140. The memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a booster circuit 140. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the booster circuit 140 are all disposed on the circuit board 110. The boost circuit 140 is connected to the relevant voltage pin to obtain an input voltage, adjusts the input voltage to obtain a first target voltage, and inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the booster circuit 140, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The first target voltage obtained by the boost circuit 140 can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that is individually configurable to adjust the voltage adjustment amplitude of the voltage regulating circuit.
In this embodiment, the boost circuit 140 obtains the input voltage from the VDD voltage input pin.
As shown in fig. 6, fig. 6 is a schematic structural diagram of a sixth embodiment of a memory bank of the present application.
In this embodiment, the voltage regulating circuit includes a voltage reducing circuit 150. The memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a step-down circuit 150. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the step-down circuit 150 are all disposed on the circuit board 110. The voltage step-down circuit 150 is connected to the relevant voltage pin to obtain an input voltage, adjusts the input voltage to obtain a first target voltage, and inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the step-down circuit 150, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The first target voltage obtained by the step-down circuit 150 can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that is individually configurable to adjust the voltage adjustment amplitude of the voltage regulating circuit.
In this embodiment, the step-down circuit 150 obtains the input voltage from the VPP voltage input pin.
As shown in fig. 7, fig. 7 is a schematic structural diagram of a seventh embodiment of a memory bank of the present application.
In this embodiment, the voltage regulating circuit includes a voltage boosting circuit 140 and a voltage reducing circuit 150. The memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, a voltage boosting circuit 140, and a voltage dropping circuit 150. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, the voltage boosting circuit 140, and the voltage reducing circuit 150 are all disposed on the circuit board 110. The boost circuit 140 is connected to the relevant voltage pin to obtain an input voltage, and the input voltage is adjusted by the boost circuit 140 and the buck circuit 150 to obtain a first target voltage, and then the first target voltage is input to the storage medium 100. The configuration circuit 120 is connected to the booster circuit 140, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. Alternatively, the configuration circuit 120 may be connected to the step-down circuit 150. The obtained first target voltage can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that is individually configurable to adjust the voltage adjustment amplitude of the voltage regulating circuit.
In this embodiment, the boost circuit 140 obtains the input voltage from the VDD voltage input pin.
As shown in fig. 8, fig. 8 is a schematic structural diagram of an eighth embodiment of a memory bank of the present application.
In this embodiment, the voltage regulating circuit includes a voltage boosting circuit 140 and a voltage stabilizing circuit 160. The memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, a booster circuit 140, and a voltage regulator circuit 160. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, the booster circuit 140, and the voltage stabilizing circuit 160 are all disposed on the circuit board 110. The boost circuit 140 is connected to the relevant voltage pin to obtain an input voltage, and the input voltage is adjusted by the boost circuit 140 and the voltage stabilizing circuit 160 to obtain a first target voltage, and then the first target voltage is input to the storage medium 100. The configuration circuit 120 is connected to the booster circuit 140, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The obtained first target voltage can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The voltage stabilizing circuit 160 makes the voltage input to the storage medium 100 more stable. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that is individually configurable to adjust the voltage adjustment amplitude of the voltage regulating circuit.
In this embodiment, the boost circuit 140 obtains the input voltage from the VDD voltage input pin.
As shown in fig. 9, fig. 9 is a schematic structural diagram of a ninth embodiment of a memory bank of the present application.
In this embodiment, the voltage regulating circuit includes a voltage boosting circuit 140. The memory bank includes a storage medium 100, a circuit board 110, a configuration circuit 120, and a booster circuit 140. A conventional VDD, VTT, VRECFA, VPP constant voltage input pin is also included.
The storage medium 100, the configuration circuit 120, and the booster circuit 140 are all disposed on the circuit board 110. The boost circuit 140 is connected to the relevant voltage pin to obtain an input voltage, and the boost circuit 140 adjusts the input voltage to obtain a first target voltage, and then inputs the first target voltage to the storage medium 100. The configuration circuit 120 is connected to the booster circuit 140, and relevant circuit parameters in the configuration circuit 120 are adjustable and externally configurable. The obtained first target voltage can be adjusted by adjusting the circuit parameters of the configuration circuit 120, so that the first target voltage reaches the required voltage value, and then the first target voltage is input to the storage medium 100 to ensure the normal operation of the storage medium 100.
Wherein the first target voltage is at least 1.2V. The configuration circuit 120 includes a resistive configuration and/or a capacitive configuration that is individually configurable to adjust the voltage adjustment amplitude of the voltage regulating circuit.
In this embodiment, the boost circuit 140 obtains the input voltage from the VDD voltage input pin.
Further, the memory bank further includes a conversion circuit 170. The conversion circuit 170 is connected to the voltage regulating circuit, that is, the booster circuit 140 and the storage medium 100, and adjusts the first target voltage output from the booster circuit 140 to the second target voltage. The second target voltage is then input to the value storage medium 100 as the VTT voltage and/or VREFCA voltage of the storage medium. The voltage value of the second target voltage is half of the voltage value of the first target voltage. The conversion circuit includes a DC-DC conversion circuit.
Alternatively, without the conversion circuit, the VTT voltage and the VREFCA voltage of the storage medium 100 may be provided directly by the voltage input pins VTT, VREFCA of the memory bank.
As shown in fig. 10, fig. 10 is a schematic structural diagram of a first embodiment of the electronic device of the present application.
The electronic device comprises a memory bank 210 according to any one of the above-described first to ninth embodiments and possible combinations thereof.
In summary, according to the above embodiments, by providing the voltage regulating circuit and the configuration circuit in the memory bank, the configuration circuit can be configured to adjust the voltage regulating circuit, thereby adjusting the voltage input to the storage medium. For different working environments, the voltage output to the storage medium can be adjusted through the configuration circuit so as to ensure the normal working performance of the storage medium.
In the several embodiments provided in the present application, it should be understood that the disclosed methods and apparatuses may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units of the other embodiments described above may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as stand alone products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. A memory bank, the memory bank comprising:
a circuit board;
a storage medium disposed on the circuit board;
the voltage regulating circuit is arranged on the circuit board and connected with the storage medium, and is used for regulating the input voltage and inputting the regulated first target voltage to the storage medium;
the configuration circuit is arranged on the circuit board and connected with the voltage regulating circuit, and circuit parameters of the configuration circuit can be configured to regulate the voltage regulating amplitude of the voltage regulating circuit.
2. The memory bank of claim 1, wherein,
the voltage regulating circuit comprises at least one of a voltage boosting circuit, a voltage reducing circuit and a voltage stabilizing circuit.
3. The memory bank according to claim 1 or 2, wherein,
the first target voltage is at least 1.2V.
4. The memory bank of claim 1, wherein,
the memory bank comprises an interface, the interface comprises a voltage input pin, the voltage regulating circuit is connected with the voltage input pin and used for regulating the voltage input by the voltage input pin and inputting the regulated first target voltage to the storage medium.
5. The memory bank of claim 4, wherein,
the voltage input pins include at least one of VDD pin, VTT pin, VREFCA pin, VPP pin.
6. The memory bank of claim 4, wherein,
the VTT voltage and/or VREFCA voltage of the storage medium are directly input by the VTT pin and/or VREFCA pin; or (b)
The memory bank further includes:
and the conversion circuit is connected with the voltage regulating circuit and the storage medium and is used for regulating the first target voltage output by the voltage regulating circuit into a second target voltage and inputting the second target voltage to the storage medium as a VTT voltage and/or a VREFCA voltage.
7. The memory bank of claim 6, wherein,
the conversion circuit is a DC-DC conversion circuit.
8. The memory bank of claim 6, wherein,
the second target voltage is half of the first target voltage.
9. The memory bank of claim 1, wherein,
the configuration circuit comprises a resistor and/or a capacitor, and the resistance value of the resistor and/or the capacitance value of the capacitor can be configured to adjust the voltage adjustment amplitude of the voltage adjustment circuit.
10. An electronic device, characterized in that the electronic device comprises a memory bank according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111221738.7A CN115995241A (en) | 2021-10-20 | 2021-10-20 | Memory bank and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111221738.7A CN115995241A (en) | 2021-10-20 | 2021-10-20 | Memory bank and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115995241A true CN115995241A (en) | 2023-04-21 |
Family
ID=85989176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111221738.7A Pending CN115995241A (en) | 2021-10-20 | 2021-10-20 | Memory bank and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115995241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113393878A (en) * | 2020-03-11 | 2021-09-14 | 深圳市江波龙电子股份有限公司 | DRAM's voltage control circuit, DRAM and electronic equipment |
-
2021
- 2021-10-20 CN CN202111221738.7A patent/CN115995241A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113393878A (en) * | 2020-03-11 | 2021-09-14 | 深圳市江波龙电子股份有限公司 | DRAM's voltage control circuit, DRAM and electronic equipment |
| CN113393878B (en) * | 2020-03-11 | 2024-05-14 | 深圳市江波龙电子股份有限公司 | Voltage control circuit, memory bank and electronic equipment of DRAM |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10852756B2 (en) | Low dropout voltage regulator integrated with digital power gate driver | |
| US10498214B2 (en) | Multi-stage amplifier | |
| CN103138577B (en) | Maintain the system and method for the linear gain of variable frequency modulator | |
| DE112018006436B4 (en) | Dual loop LDO adaptive voltage regulator and voltage regulation method | |
| US9323263B2 (en) | Low dropout regulator with hysteretic control | |
| DE112019002883T5 (en) | DEVICE AND PROCEDURE FOR PROACTIVE PERFORMANCE MANAGEMENT | |
| KR101873137B1 (en) | Shunt integrated voltage regulator | |
| DE102014001268A1 (en) | POWER ARCHITECTURE WITH MULTIPLE VOLTAGE IDENTIFICATION (VID), DIGITALLY SYNTHETIZABLE LOW-DROPUT CONTROLLER AND DEVICE TO IMPROVE THE RELIABILITY OF POWER-GATES | |
| DE102011005270A1 (en) | Method and device for calibrating power converters | |
| US9110643B2 (en) | Leakage current reduction in an integrated circuit | |
| CN110244808B (en) | Voltage regulation method, device, equipment and storage medium | |
| CN109213247A (en) | To supply the circuit and method that adjust voltage to objective circuit | |
| CN209980116U (en) | Overshoot elimination circuit and undershoot elimination circuit of low dropout regulator and chip | |
| DE102015218648A1 (en) | Multi-stage amplifier with improved operating efficiency | |
| DE112020004531T5 (en) | DOUBLE LOOP LDO VOLTAGE REGULATOR | |
| CN110999056A (en) | Voltage regulator for integrated circuit chip | |
| US10614185B2 (en) | Low drop-out voltage regulator modeling systems and methods | |
| Rozman et al. | Circuit considerations for fast, sensitive, low-voltage loads in a distributed power system | |
| WO2015103768A1 (en) | Linear regulator with improved power supply ripple rejection | |
| CN115995241A (en) | Memory bank and electronic equipment | |
| CN103076835A (en) | Low drop-out linear voltage stabilizer and regulation circuit thereof | |
| US20200089300A1 (en) | Load line regulation via clamping voltage | |
| US20090160421A1 (en) | Multi-regulator power delivery system for ASIC cores | |
| US20150276819A1 (en) | Method and Apparatus for Determining Resistance Values of Dynamic Voltage-Adjusting Circuit | |
| US11209848B2 (en) | Fast regulator architecture having transistor helper |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |