CN115981971A

CN115981971A - Lighting method of server hard disk and server

Info

Publication number: CN115981971A
Application number: CN202211494823.5A
Authority: CN
Inventors: 蔡一诺
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2022-11-26
Filing date: 2022-11-26
Publication date: 2023-04-18

Abstract

The embodiment of the application discloses a lighting method of a server hard disk and a server, wherein the method comprises the following steps: the first logic device acquires a serial lighting signal sent by the processor in a serial mode, wherein the serial lighting signal comprises a plurality of lighting signals, and each lighting signal comprises a VPP address; each lighting signal is used for lighting one hard disk indicator lamp unit; the first logic device analyzes the serial lighting signal into a plurality of lighting signals comprising the same address, and transmits each lighting signal to the second logic device in parallel according to the corresponding relation between the preset VPP address and the communication link; the second logic device receives each lighting signal transmitted by the first logic device in parallel, analyzes each received lighting signal and then indicates the hard disk indicator lamp to light. The embodiment of the application is beneficial to reducing a large amount of address adaptation work in the second logic device, thereby reducing the lighting complexity of the hard disk.

Description

Lighting method of server hard disk and server

Technical Field

The invention relates to the technical field of server hard disk lighting, in particular to a server hard disk lighting method and a server.

Background

In recent years, with rapid development of industries such as cloud computing, big data, internet of things and the like, the demand of data storage is increasing, and it is difficult for a traditional Solid State Drive (SSD) to meet diversified data storage demands in some scenarios. Due to the characteristics of large capacity, high read-write speed, low input and output delay and the like, non-Volatile Memory host controller interface specification (NVMe) SSD has been applied in large scale in the field of servers. At present, the realization of the hot plug lighting function of the nvmesd needs to configure and adapt a large number of Virtual Pin Port (VPP) addresses, which generates huge workload and increases the lighting complexity of the nvmesd.

Disclosure of Invention

The embodiment of the application provides a lighting method of a server hard disk and the server, a first logic device can convert a serial lighting signal sent by a processor into a plurality of lighting signals, and addresses in the lighting signals are configured to be the same, so that the second logic device at the back board end of the hard disk can finish analysis operation on the lighting signals by only configuring one address, a large amount of address adaptation work in the second logic device is reduced, and the lighting complexity of the hard disk is favorably reduced.

In a first aspect, an embodiment of the present application provides a server, where the server includes a motherboard, a hard disk backplane, and a first logic device, the motherboard includes a processor, the processor includes a plurality of VPP addresses, the processor sends a serial lighting signal to the first logic device, and the serial lighting signal includes a plurality of lighting signals; each lighting signal includes a VPP address; each lighting signal is used for lighting one hard disk indicator lamp unit;

the hard disk backboard comprises a second logic device and a hard disk indicator light, and the second logic device is communicated with the first logic device through a plurality of communication links; the second logic device is electrically connected with the hard disk indicator lamp;

the first logic device is used for analyzing the serial lighting signals into a plurality of lighting signals comprising the same address, transmitting each lighting signal to the second logic device in parallel through the corresponding communication link according to the corresponding relation between the preset VPP address and the communication link, and the second logic device analyzes each received lighting signal and then indicates the hard disk indicator lamp to light.

It can be seen that, in the embodiment of the present application, the first logic device may analyze the serial lighting signal into a plurality of lighting signals including the same address according to the VPP address in the serial lighting signal, and transmit the converted lighting signals in parallel to the second logic device at the hard disk backplane end through the corresponding communication link, so that the second logic device may perform a lighting operation after analyzing the received lighting signal in an adaptation-free manner without performing a large amount of address adaptation with the BIOS, thereby facilitating to reduce a large amount of address adaptation at the hard disk backplane end, and further reducing the complexity of lighting the hard disk.

In some possible embodiments, the motherboard includes a plurality of first connectors, the hard disk backplane includes a plurality of second connectors, and each communication link includes one first connector and one second connector; the first connector and the second connector are connected by a cable;

the first logic device transmits each lighting signal in parallel to the first connector of the communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and the second connector connected to the first connector of the communication link.

In this embodiment, since the first logic device transmits each lighting signal to the second logic device in parallel through the first connector and the second connector connected to the first connector on the corresponding communication link, the first logic device is required to convert a complex virtual address (i.e., a VPP address) into a hardware address of the connector (i.e., an address in the analyzed plurality of lighting signals) when performing the conversion operation, and the hardware address of the connector does not need to be configured and adapted on the hard disk backplane side, which is beneficial to saving workload.

In some possible embodiments, the second logic device includes a normalized address, and the second logic device matches the address in each received lighting signal with the normalized address, and analyzes lighting information from each received lighting signal if matching is successful.

In this embodiment, because the first logic device performs the conversion operation on the serial lighting signals to configure the VPP addresses in the multiple lighting signals as the same address, the second logic device can complete the matching with all the VPP addresses by configuring only one address (i.e., a normalized address), and compared with the scheme that a large number of VPP addresses need to be adapted for matching to analyze the lighting information, the method is beneficial to improving the matching efficiency of the VPP addresses at the backplane end of the hard disk, and the second logic device can analyze the lighting information without being adapted.

In some possible embodiments, the second logic device determines, according to a preset correspondence between the second connector and the hard disk, at least one hard disk for lighting each received lighting signal, and instructs, based on the lighting information, to light a hard disk indicator lamp of the at least one hard disk.

In this embodiment, the second logic device can specify at least one hard disk corresponding to the second connector whose address matching is successful based on the one-to-one correspondence relationship between the plurality of second connectors and the plurality of hard disks, and can perform a lighting operation on the hard disk indicator lamp of the at least one hard disk based on the lighting information in each lighting signal, thereby shifting the lighting operation based on the VPP address to the lighting operation based on the connectors.

In some possible embodiments, the first logic device analyzes a plurality of lighting signals from the serial lighting signal according to the VPP address in each lighting signal, configures the VPP address in each lighting signal to the same address, and obtains a plurality of lighting signals including the same address.

In this embodiment, since the first logic device performs the conversion operation on the serial lighting signals to configure the VPP addresses in the plurality of lighting signals to the same address, the hard disk backplane can analyze the lighting signals by configuring only one address, thereby avoiding the hard disk backplane from performing a large address adaptation with the BIOS to analyze the lighting signals.

In a second aspect, an embodiment of the present application provides a lighting method for a server hard disk, which is applied to the server in the first aspect, and the method includes:

the method comprises the steps that a first logic device obtains serial lighting signals sent by a processor in a serial mode, the serial lighting signals comprise a plurality of lighting signals, and each lighting signal comprises a VPP address; each lighting signal is used for lighting one hard disk indicator lamp unit;

the first logic device analyzes the serial lighting signal into a plurality of lighting signals comprising the same address, and transmits each lighting signal to the second logic device in parallel according to the corresponding relation between the preset VPP address and the communication link;

the second logic device receives each lighting signal transmitted by the first logic device in parallel, analyzes each received lighting signal and then indicates the hard disk indicator lamp to light.

In some possible embodiments, transmitting each lighting signal in parallel to the second logic device includes:

the first logic device transmits each lighting signal in parallel to the first connector of the corresponding communication link, and each lighting signal is transmitted to the second logic device through the first connector of the communication link and the second connector connected to the first connector of the communication link.

In some possible embodiments, the second logic device includes a normalized address, and after receiving each lighting signal transmitted in parallel by the first logic device, the method further includes:

the second logic device matches the address in each received lighting signal with the normalized address;

and the second logic device analyzes lighting information from each received lighting signal under the condition of successful matching.

In some possible embodiments, the indicating hard disk indicator lamp is lighted, including:

the second logic device determines at least one hard disk for lighting each received lighting signal according to a preset corresponding relation between the second connector and the hard disk;

the second logic device indicates the hard disk indicator lamp of the at least one hard disk to be turned on based on the lighting information.

It should be noted that, for implementation details of each step in the second aspect, reference may be made to corresponding descriptions of the server embodiment shown in the first aspect, and the same or similar beneficial effects may be achieved.

In a third aspect, the present application provides a computer-readable storage medium, where a computer program for an apparatus to execute is stored, and when the computer program is executed, the method in the second aspect is implemented.

In a fourth aspect, the present application provides a computer program product, which when executed by an apparatus, causes the apparatus to perform the method of the second aspect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present invention, the drawings required to be used in the embodiments or the background art of the present invention will be described below.

Fig. 1 is a hardware architecture diagram of a design method for implementing lighting of multiple NVMe hard disk backplanes proposed by the related art;

fig. 2 is a schematic flow chart of a design method for lighting multiple NVMe hard disk backplanes in the related art;

fig. 3 is a schematic diagram of a hardware architecture according to an embodiment of the present application;

fig. 4 is a schematic flowchart of a lighting method for a server hard disk according to an embodiment of the present disclosure;

fig. 5 is an overall schematic diagram of a server hard disk lighting provided in the embodiment of the present application;

fig. 6 is a schematic diagram of a serial lighting signal according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a server according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another server according to an embodiment of the present application.

Detailed Description

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different elements and not for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.

As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a terminal device and the terminal device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between 2 or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another at a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

It should be noted that, in the description of the present application:

CPU (Central Processing Unit) is a Central Processing Unit;

I2C (Inter-Integrated Circuit) is a serial bus;

PCIe (Peripheral Component Interconnect-express) is a high-speed serial computer expansion bus standard;

PLD (Programmable Logic Device) is a Programmable Logic Device;

CPLD (Complex Programmable Logic Device) is a Complex Programmable Logic Device;

FPGA (Field Programmable Gate Array) is Programmable Array logic;

the BIOS (Basic Input Output System) is a Basic Input Output System;

UBC (unionbus connector) is a high-speed line-end IO connector.

In order to facilitate understanding of the embodiments of the present application, and further analyze and present technical problems to be solved by the present application, the following briefly introduces related technical solutions of the present application.

For example, referring to fig. 1, fig. 1 is a hardware architecture diagram of a design method for implementing multi-NVMe hard disk backplane lighting proposed by the related art, as shown in fig. 1, a CPU1 on a motherboard includes five ports, namely PCIe0, PCIe1, PCIe2, PCIe3, and PCIe4, where PCIe0 and PCIe1 have one PCIe5.0 × 16 channel, PCIe2, PCIe3, and PCIe4 have two PCIe5.0 × 8 channels, and each channel is connected to a backplane through a connector configured for each channel. The BIOS allocates a VPP address for each PCIe port of the CPU1, and the VPP address finally points to the address or the identification of the NVMeSSD mounted under the CPU1 on the backplane. Based on the architecture, please refer to fig. 2, a design method for implementing lighting of multiple NVMe hard disk backplanes is proposed in the related art, as shown in fig. 2, including the following steps:

a group of VPP signal lines are connected to each controller of the mainboard and transmitted to the backboard through a connector sideband channel of each port;

the controller circularly sends a VPP address to the back board end, and a programmable logic unit of the back board analyzes address information sent by the controller after receiving a data stream sent by the controller;

if the VPP address simulated by the backboard channel is the same as the address sent by the controller, the controller sends the lighting information of the hard disk corresponding to the disk to the programmable logic device of the backboard;

and the programmable logic device of the backboard performs logic conversion on the lighting information of the hard disk sent by the controller, converts the serial data stream on the VPP into parallel signals, lights the backboard lamp of the corresponding port, and uploads the in-place information of the hard disk monitored by the backboard to the controller.

In the development process, the number of NVMe backplanes is large, VPP addresses and the number of the NVMe backplanes configured on each backplane are different, the workload of address merging in the BIOS is relatively large, and the address of each hard disk needs to be adapted through the backplane CPLD, so that a large amount of adaptation workload is brought to the backplane end undoubtedly, and if the address adaptation needs to be performed at the backplane end of each lighting, the lighting efficiency is greatly influenced. In addition, the backplane borrowing often exists between the projects, a large number of VPP addresses need to be merged into a new backplane BIOS, the backplane end needs to be adapted again, and the process is relatively complicated. Based on the two points mentioned above, when the hard disk configuration is expanded, the BIOS and the two ends of the backplane need to re-incorporate new VPP addresses, and the adaptation work at the backplane end is performed all the time.

In summary of the defects and shortcomings of the related art, the embodiments of the present application mainly solve the following technical problems: how to carry out VPP address adaptation-free at the back board end so as to reduce the lighting complexity of the hard disk and improve the lighting efficiency.

The following describes a lighting method for a server hard disk and a server in detail, which are provided in an embodiment of the present application, with reference to the accompanying drawings.

Based on the above technical problem, please refer to fig. 3, fig. 3 is a schematic diagram of a hardware architecture provided in an embodiment of the present application, and as shown in fig. 3, the hardware architecture includes a motherboard and a hard disk backplane, the motherboard includes one or more CPUs (e.g., CPU1, CPU2, etc.), a CPLD, and a plurality of connectors (e.g., connector 1, connector 2, ..., connector n). The hard disk backplane comprises a plurality of connectors, a CPLD, a plurality of inserted hard disks (such as hard disk 0, hard disk 1, ..., hard disk n) and a hard disk indicator lamp of each hard disk, wherein each CPU on the mainboard is connected with the CPLD through a hot-plug I2C communication line, such as: CPU1 is connected with CPLD through hot plug I2C 1, and CPU2 is connected with CPLD through hot plug I2C 2, and CPLD is connected with a plurality of connectors through I2C communication line. Each connector on the hard disk backboard is connected with the CPLD through an I2C communication line, and the plurality of connectors are connected with the plurality of connectors on the motherboard through cables, respectively, to form a plurality of communication links between the motherboard end CPLD and the hard disk backboard end CPLD, for example: the connector 1 is connected with the connector 1 on the mainboard, the connector 2 is connected with the connector 2 on the mainboard, and so on. The CPLD at the hard disk backplane end lights up the corresponding hard disk indicator lamp based on the lighting signal received by each connector, for example: the lighting signal received by the connector 1 is used for lighting the hard disk 0 and the hard disk 1, and the lighting signal received by the connector 2 is used for lighting the hard disk 2 and the hard disk 3, and so on.

Referring to fig. 4, fig. 4 is a schematic flowchart of a lighting method for a hard disk of a server according to an embodiment of the present disclosure, where the method can be implemented based on the architecture shown in fig. 3, and is particularly applicable to a server, where the server includes a motherboard, a hard disk backplane, and a first logic device, the motherboard includes a processor, the processor includes a plurality of virtual ports, and each virtual port has a corresponding VPP address. The hard disk backboard comprises a second logic device, a plurality of inserted hard disks (the plurality of hard disks can be NVMe SSD) and a hard disk indicator lamp, and the second logic device is communicated with the first logic device through a plurality of communication links; the second logic device is electrically connected with the hard disk indicator lamp. As shown in fig. 4, the method may include steps 401-403:

401: the first logic device obtains a serial lighting signal sent by the processor in a serial mode.

In this embodiment of the present application, the first logic device may be a logic device located on the motherboard, or may be a logic device located in another place outside the motherboard. The processor sends a serial lighting signal to the first logic device, the serial lighting signal comprises a plurality of lighting signals, each lighting signal comprises a VPP address and lighting information, and each lighting signal is used for lighting one hard disk indicator lamp unit. Wherein, a hard disk indicating unit includes the hard disk pilot lamp of at least one hard disk, for example: a hard disk pack. The processor may be any one of the CPUs on the motherboard, such as CPU1 or CPU2 in fig. 3. The VPP address in each lighting signal may specifically be an address allocated by the BIOS for a PCIe port of the CPU, where each VPP address corresponds to at least one hard disk of the plurality of hard disks, for example: the VPP address of PCIe0 corresponds to hard disk 0 or a hard disk group including hard disk 0 and hard disk 1 among the plurality of hard disks. The processor generates a corresponding lighting command based on the VPP address of each PCIe port, where each lighting command includes the VPP address and lighting information, for example: the lighting information may be green constant brightness, green flashing, etc. of an Active lamp indicating the corresponding hard disk. For example, if the VPP address of PCIe0 corresponds to hard disk 0 and hard disk 1, the lighting command of hard disk 0 and hard disk 1 is the same. The processor sends a plurality of lighting commands in a serial mode through the hot plug I2C signal wire, namely serial lighting signals, and each lighting command is one lighting signal in the serial lighting signals.

For example, referring to fig. 5, the bios allocates VPP addresses to five PCIe ports of the CPU1, and then the CPU1 takes each VPP address and corresponding lighting information as a lighting command, and sends the five lighting commands to the first logic device in a serial manner through the hot-plug I2C signal line, and then the first logic device receives the serial lighting signal.

402: the first logic device analyzes the serial lighting signal into a plurality of lighting signals comprising the same address, and transmits each lighting signal to the second logic device in parallel according to the corresponding relation between the preset VPP address and the communication link.

In the embodiment of the application, for the first logic device end, each lighting command is a lighting signal, and the first logic device end analyzes each lighting signal from the serial lighting signal according to the VPP address in the serial lighting signal, so as to obtain a plurality of lighting signals in the serial lighting signal. For example, as shown in fig. 6, if the five lighting commands in fig. 5 are "VPP0+ lighting information 0, VPP1+ lighting information 1, ..., VPP4+ lighting information 4", respectively, the first logic device may obtain the lighting information corresponding to each VPP address according to the VPP address, so as to obtain the corresponding lighting signal, for example: the lighting information 0 can be obtained from VPP0 to analyze the corresponding lighting signal 1, the lighting signal 1 can be obtained from VPP1 to analyze the corresponding lighting signal 2, and the lighting signal 4 can be obtained from VPP4 to analyze the corresponding lighting signal 5, and so on.

The first logic device configures the VPP address in each lighting signal to be the same address, and repacks the address and the lighting information into a new lighting command, thereby obtaining a plurality of new lighting commands. The first logic device is configured with a corresponding relationship between a VPP address and a communication link, such as: VPP0 corresponds to communication link 1, VPP1 corresponds to communication link 2, and so on, and the first logic device puts the plurality of new lighting commands on different communication links based on the correspondence, i.e., generates a plurality of lighting signals including the same address (i.e., a plurality of lighting signals in parallel). The address for replacing the VPP address may be an address pre-configured in the first logic device, such as: the address may be x 40.

In this embodiment, since the VPP addresses in the lighting signals are configured to be the same address by the conversion operation of the serial lighting signal by the first logic device, the lighting signal can be analyzed by configuring only one address at the hard disk backplane side, thereby avoiding the hard disk backplane side from performing a large number of address adaptations with the BIOS to analyze the lighting signal.

Illustratively, the motherboard includes a plurality of first connectors, the hard disk backplane includes a plurality of second connectors, and each communication link includes one first connector and one second connector, the first connector and the second connector are connected by a cable, such as: the first connector 1 is connected to the second connector 1, the first connector 2 is connected to the second connector 2, and so on. Wherein each communication link may be an I2C communication link.

The first logic device transmits each lighting signal to the second logic device in parallel, including:

For example, continuing with fig. 5, the first logic device transmits five new lighting commands in parallel to the second logic device using five I2C communication links, such as: the lighting command 1 needs to be transmitted to the second logic device through the communication link 1, the communication link 1 includes a first connector 1 located on the motherboard and a second connector 1 located on the hard disk backplane, the first logic device sends the lighting command 1 to the I2C communication line (i.e. generates the lighting signal 1) to transmit to the first connector 1, and the lighting signal 1 is transmitted to the second logic device through the first connector 1 and the second connector 1 connected to the first connector 1.

Illustratively, the plurality of first connectors and the plurality of second connectors may be UBC connectors. The first and second logic devices may be PLDs, CPLDs, FPGAs, etc.

403: the second logic device receives each lighting signal transmitted by the first logic device in parallel, analyzes each received lighting signal and then indicates the hard disk indicator lamp to light.

In the embodiment of the application, corresponding to the motherboard, since the first logic device sends the plurality of lighting signals in parallel through the plurality of first connectors, the second logic device at the hard disk backplane end acquires the plurality of lighting signals through the plurality of second connectors. Specifically, when the plurality of second connectors are connected to the second logic device via the plurality of I2C communication lines, respectively, the plurality of lighting signals are transmitted to the plurality of second connectors in parallel, and then transmitted to the second logic device via the plurality of I2C communication lines.

Illustratively, the second logic device includes a normalized address, and after receiving each of the lighting signals transmitted in parallel by the first logic device, the method further includes:

In the embodiment of the present application, the second logic device is configured with an address including normalization, for example: x 40, for each lighting signal transmitted to the second logic device by each second connector, the second logic device first extracts an address in each lighting signal, then matches the address with the normalized address, and analyzes lighting information from each lighting signal when the address is the same as the normalized address. Such as: if the address in one lighting signal is equal to x 40, the matching is successful, and the second logic device analyzes lighting information from the lighting signal. On the contrary, if the address in the received lighting signal is not matched with the normalized address, the second logic device cannot analyze the lighting information from the lighting signal.

In this embodiment, because the VPP addresses in the plurality of lighting signals are configured as the same address by the conversion operation of the serial lighting signal by the first logic device, the second logic device can complete matching with all VPP addresses by configuring only one address (i.e., a normalized address), and compared with a scheme that matching needs to be performed by adapting a large number of VPP addresses to analyze lighting information, the method is beneficial to improving the matching efficiency of the VPP addresses at the backplane end of the hard disk, and simultaneously, the second logic device can analyze lighting information without adaptation.

Illustratively, instruct hard disk pilot lamp to light up, include:

the second logic device determines at least one hard disk for lighting each received lighting signal according to the preset corresponding relation between the second connector and the hard disk;

the second logic device indicates the hard disk indicator lamp of the at least one hard disk to light up based on the lighting information.

In this embodiment of the application, the second logic device is configured with a corresponding relationship between a plurality of hard disks at the hard disk backplane end and a plurality of second connectors, for example: the second connector 1 corresponds to the hard disk 0 (or a hard disk group consisting of the hard disk 0 and the hard disk 1), and the corresponding relationship may be an association relationship between the identifier of the hard disk and the second connector. For a target second connector with the same address as the normalized address in the lighting signal received by the plurality of second connectors, based on the correspondence relationship, the second logic device may determine at least one hard disk (i.e., a hard disk to be lit) corresponding to the target second connector from the plurality of hard disks, and then perform lighting information to light a hard disk indicator lamp of the at least one hard disk. Such as: in fig. 5, if the address in each lighting signal received by the second logic device is x 40, the hard disk group corresponding to each second connector is determined, and then the hard disks in the hard disk group are lighted based on the lighting information. Illustratively, when the hard disk is in the hot plug process, the lighting information indicates that the Active lamp flickers and the Fault lamp flickers.

It can be seen that, in the embodiment of the present application, the first logic device may analyze the serial lighting signal into a plurality of lighting signals including the same address according to the VPP address in the serial lighting signal, so that the second logic device at the hard disk backplane end may not need to perform a large amount of address adaptation work with the BIOS. After the second logic device receives a plurality of lighting signals sent by the first logic device in parallel, the lighting information in the corresponding lighting signals can be analyzed only by matching one configured address with addresses in all the lighting signals, the normalization of the VPP address is realized at the hard disk backplane end, and meanwhile, the hard disk backplane end can avoid the adaptation analysis of the lighting signals and execute the lighting operation, so that the large amount of address adaptation work at the hard disk backplane end is reduced, and the complexity of the lighting of the hard disk is reduced. In addition, only one address needs to be configured at the hard disk backboard end, the problem that the VPP address configuration is inflexible is solved, the number of the addresses needing to be configured is greatly reduced, and management and maintenance are facilitated. Because the first logic device can convert all VPP addresses sent by the processor into the same address, when the backplane expansion is needed, the hard disk backplane end does not need to be configured again, and the expandability of software and hardware systems is improved.

The embodiment of the application further provides a server. Referring to fig. 7, fig. 7 is a schematic structural diagram of a server 700 according to an embodiment of the present disclosure, where the server 700 at least includes a main board 701, a hard disk backplane 702, and a first logic device 703, the main board 701 includes a processor 7011, the processor 7011 includes a plurality of VPP addresses, and the processor 7011 sends a serial lighting signal to the first logic device 703, where the serial lighting signal includes a plurality of lighting signals; each lighting signal includes a VPP address; each lighting signal is used for lighting one hard disk indicator lamp unit; the first logic device 703 may be a logic device located on the main board 701, or may be a logic device located elsewhere than on the main board 701.

The hard disk backboard 702 comprises a second logic device 7021, an inserted hard disk 7022 and a hard disk indicator light 7023, and the second logic device 7021 communicates with the first logic device 703 through a plurality of communication links 704; the second logic device 7021 is electrically connected with the hard disk indicator lamp 7023;

the first logic device 703 is configured to analyze the serial lighting signal into a plurality of lighting signals including the same address, and transmit each lighting signal to the second logic device 7021 in parallel through the corresponding communication link 704 according to a correspondence between a preset VPP address and the communication link, where the second logic device 7021 analyzes each received lighting signal and then instructs the hard disk indicator 7023 to light up.

For example, referring to fig. 8, the motherboard 701 includes a plurality of first connectors 7012, the hard disk backplane 702 includes a plurality of second connectors 7024, and each communication link 704 includes one first connector 7012 and one second connector 7024; the first connector 7012 and the second connector 7024 are connected by a cable;

the first logic device 703 transmits each lighting signal in parallel to the first connector 7012 of the communication link 704, and transmits each lighting signal to the second logic device 7021 through the first connector 7012 of the communication link 704 and the second connector 7024 connected to the first connector 7012 of the communication link 704.

Illustratively, the second logic device 7021 includes a normalized address, and the second logic device 7021 matches the address in each received lighting signal with the normalized address, and analyzes lighting information from each received lighting signal if matching is successful.

Illustratively, the second logic device 7021 determines at least one hard disk for lighting each received lighting signal according to a preset correspondence between the second connector and the hard disk, and instructs the hard disk indicator 7023 of the at least one hard disk to light on the basis of the lighting information.

For example, the first logic device 703 analyzes a plurality of lighting signals from the serial lighting signal according to the VPP address in each lighting signal, configures the VPP address in each lighting signal to the same address, and obtains a plurality of lighting signals including the same address.

The specific implementation in the server 700 can refer to the related description in the embodiment shown in fig. 4, and can achieve the same or similar advantages.

It can be seen that, in the server 700, the first logic device 703 can resolve the serial lighting signal into multiple lighting signals including the same address according to the VPP address in the serial lighting signal, which makes the second logic device 7021 at the hard disk backplane 702 end not need to perform a lot of address adaptation work with the BIOS. After receiving a plurality of lighting signals sent by the first logic device 703 in parallel, the second logic device 7021 only needs to match one configured address with addresses in all the lighting signals to analyze lighting information in the corresponding lighting signals, so that the normalization of the VPP address is realized at the end of the hard disk backplane 702, and meanwhile, the end of the hard disk backplane 702 can avoid adaptively analyzing the lighting signals and perform lighting operation, which is beneficial to reducing a large amount of address adaptation work at the end of the hard disk backplane 702, thereby reducing the complexity of lighting the hard disk.

Illustratively, the server 700 may further include a Memory including, but not limited to, a Random Access Memory (RAM), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (EPROM), or a portable Read-Only Memory (CD-ROM) for storing related computer programs and data.

The first logic device 703 and the second logic device 7021 in the server 700 are configured to read one or more programs stored in the memory to perform operations in the firmware information obtaining method in the server.

It should be noted that although the server 700 only shows the main board 701, the processor 7011, the hard disk backplane 702, the first logic device 703, the second logic device 7021, the hard disk 7022, the hard disk indicator light 7023, the plurality of communication links 704, the plurality of first connectors 7012, and the plurality of second connectors 7024, in a specific implementation process, it should be understood by those skilled in the art that the server 700 also includes other devices necessary for normal operation, such as: input and output devices, fans, network cards, power modules, and the like. Also, those skilled in the art will appreciate that server 700 may also include hardware components to implement other additional functions, according to particular needs. In addition, those skilled in the art will appreciate that the server 700 may also include only the components necessary to implement the embodiments of the present application, and need not include all of the components described above.

Embodiments of the present application further provide a computer-readable storage medium (Memory), which is a Memory device in the server 700, and is used to store a computer program for device execution, where when the computer program is executed on the server 700, the method flow shown in fig. 4 is implemented. It is understood that the computer readable storage medium herein may include a built-in storage medium in the server 700, and may also include an extended storage medium supported by the server 700. The computer readable storage medium provides a storage space that stores an operating system of the server 700. Also, one or more computer programs adapted to be loaded and executed by the first logic device and the second logic device are also stored in the memory space. It should be noted that the computer-readable storage medium may be a high-speed RAM, or may be a non-volatile memory (non-volatile memory), such as at least one disk memory; optionally, at least one computer readable storage medium located remotely from the aforementioned network card and PLD may also be present.

Embodiments of the present application also provide a computer program product, and when the computer program product is executed by a device, the method flow shown in fig. 4 is implemented.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

It should be understood that the Processor mentioned in the embodiments of the present Application may be a CPU, and may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory referred to in the embodiments herein may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a ROM, a Programmable Read Only Memory (PROM), an EPROM, an Electrically Erasable Programmable Read-Only Memory (EEPROM), or a flash Memory. Volatile memory can be RAM, which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), enhanced Synchronous SDRAM (ESDRAM), synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

It should be noted that when the processor is a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, the memory (memory module) is integrated in the processor.

It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely exemplary, for example, the division of the units into only one type of logical functional division may be implemented in other ways, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a alone, A and B together, and B alone, wherein A and B may be singular or plural. In the description of the text of this application, the character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device can be merged, divided and deleted according to actual needs.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A server is characterized by comprising a mainboard, a hard disk backboard and a first logic device, wherein the mainboard comprises a processor, the processor comprises a plurality of VPP addresses, the processor sends a serial lighting signal to the first logic device, and the serial lighting signal comprises a plurality of lighting signals; each lighting signal includes a VPP address; each lighting signal is used for lighting one hard disk indicator lamp unit;

the hard disk backboard comprises a second logic device and a hard disk indicator light, and the second logic device is communicated with the first logic device through a plurality of communication links; the second logic device is electrically connected with the hard disk indicating lamp;

the first logic device is used for analyzing the serial lighting signal into a plurality of lighting signals with the same address, each lighting signal is transmitted to the second logic device in parallel through the corresponding communication link according to the corresponding relation between the preset VPP address and the communication link, and the second logic device analyzes each received lighting signal and then indicates the hard disk indicator lamp to light.

2. The server according to claim 1, wherein the motherboard comprises a plurality of first connectors, the hard disk backplane comprises a plurality of second connectors, and each communication link comprises one first connector and one second connector; the first connector and the second connector are connected by a cable;

the first logic device transmits each lighting signal in parallel to a first connector of the communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and a second connector connected to the first connector of the communication link.

3. The server according to claim 1 or 2, wherein the second logic device includes a normalized address, and the second logic device matches an address in each received lighting signal with the normalized address, and analyzes lighting information from each received lighting signal if matching is successful.

4. The server according to claim 3, wherein the second logic device determines at least one hard disk for lighting each received lighting signal according to a preset correspondence between the second connector and the hard disk, and instructs, based on the lighting information, lighting of a hard disk indicator lamp of the at least one hard disk.

5. The server according to any one of claims 1 to 4, wherein the first logic device parses the plurality of lighting signals from the serial lighting signal according to a VPP address in each lighting signal, configures the VPP address in each lighting signal to be the same address, and obtains a plurality of lighting signals including the same address.

6. A lighting method for a server hard disk, which is applied to the server according to any one of claims 1 to 5, the method comprising:

7. The method of claim 6, wherein transmitting each lighting signal to the second logic device in parallel comprises:

the first logic device transmits each lighting signal in parallel to a first connector of a corresponding communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and a second connector connected to the first connector of the communication link.

8. The method of claim 6 or 7, wherein the second logic device includes a normalized address, and wherein after receiving each lighting signal transmitted in parallel by the first logic device, the method further comprises:

9. The method of claim 8, wherein the indicating hard disk light is illuminated, comprising:

10. The method according to any of claims 6-9, wherein said parsing said serial lighting signal into a plurality of lighting signals including the same address comprises:

the first logic device analyzes the plurality of lighting signals from the serial lighting signals according to a VPP address in each lighting signal;

the first logic device configures the VPP address in each lighting signal to be the same address, and obtains a plurality of lighting signals comprising the same address.