CN115981437A - DDR5 memory bank power-on and power-off method, device, equipment and medium - Google Patents
DDR5 memory bank power-on and power-off method, device, equipment and medium Download PDFInfo
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Abstract
The application discloses a DDR5 memory bank power-on and power-off method, device, equipment and medium, and relates to the technical field of computer storage. The method is applied to a DDR5 memory bank power-on and power-off system which comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays. The method comprises the steps that preset power-on and power-off information of each DDR5 memory bank is obtained, and time information transmitted by a clock chip is received; and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information so that the encoder can respectively control the conduction condition of each relay according to the control signal to respectively control the power-on and power-off of each DDR5 memory bank. Therefore, the direct power-on and power-off of the DDR5 memory bank can be realized without plugging and unplugging the memory bank by the scheme, the power-on or power-off of the DDR5 memory bank in various modes can be realized according to the preset power-on and power-off information, and the direct impact on the DDR5 memory in the stability test stage is realized.
Description
Technical Field
The present application relates to the field of computer storage technologies, and in particular, to a method, an apparatus, a device, and a medium for powering on and powering off a DDR5 memory bank.
Background
DDR5 is a computer memory specification. Compared with a DDR4 memory, the DDR5 memory has stronger standard performance and lower power consumption. The voltage of the bus is reduced from 1.2V to 1.1V, and simultaneously 32/40 bits per channel (Error correction Code (ECC) can be realized), the bus efficiency is improved, the number of prefetched Bank groups is increased to improve the performance, and the like. The improved DDR5 functionality will increase the actual bandwidth by 36% compared to DDR4, even starting at 3200MT/s (this statement must be tested) and 4800MT/s speed, which will be 87% higher compared to DDR 4-3200. Meanwhile, one of the most important characteristics of DDR5 is a monolithic chip density exceeding 16 Gb.
The stability of DDR5 Dual-Inline-Memory-Modules (DIMMs) is affected by the power stability of DDR5 DIMMs. The stability of DDR5 DIMMs affects the stability of the entire server system. The common test mode for DDR5 stability is to perform power-on and power-off operation on a DDR5DIMM, but the power-on and power-off operation is based on power-on and power-off of a server mainboard, and the server mainboard also has a power protection circuit which plays a role in buffering when the server mainboard is powered on and powered off and does not necessarily impact the DDR5DIMM effectively, so that the DDR5 stability test device has certain limitation.
In view of the above problems, an urgent need exists in the art to realize direct power-on and power-off of DDR5 memory banks in a server system.
Disclosure of Invention
The application aims to provide a DDR5 memory bank power-on and power-off method, device, equipment and medium, so that direct power-on and power-off of a DDR5 memory bank in a server system can be realized.
In order to solve the technical problem, the application provides a method for powering on and powering off a DDR5 memory bank, which is applied to a system for powering on and powering off the DDR5 memory bank; the DDR5 memory bank power-on and power-off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and a power supply; the method comprises the following steps:
acquiring preset power-on and power-off information of each DDR5 memory bank, and receiving time information transmitted by the clock chip;
and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information so that the encoder can respectively control the conduction condition of each relay according to the control signal to respectively control the power-on and power-off of each DDR5 memory bank.
Preferably, the DDR5 memory bank power supply and discharge system further comprises an upper computer;
the upper computer is connected with the main control chip and used for setting the preset power-on and power-off information and recording the power-on and power-off times and power-on and power-off modes of the DDR5 memory banks.
Preferably, the DDR5 memory bank power on and power off system further comprises a key device;
the key device is connected with the main control chip and used for setting the preset power-on and power-off information.
Preferably, the acquiring preset power-on and power-off information of each DDR5 memory bank includes:
and acquiring the preset power-on and power-off information of each DDR5 memory bank transmitted by the upper computer.
Preferably, the acquiring preset power-on and power-off information of each DDR5 memory bank includes:
and acquiring the preset power-on and power-off information of each DDR5 memory bank set by the key device.
Preferably, the DDR5 memory bank power-on and power-off system further comprises a display device;
the display device is connected with the main control chip and used for displaying the power-up and power-down states of the DDR5 memory banks.
Preferably, the relay is an electromagnetic relay.
In order to solve the technical problem, the application also provides a DDR5 memory bank power on and power off device which is applied to a DDR5 memory bank power on and power off system; the DDR5 memory bank power on and power off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and a power supply; the device comprises:
the obtaining and receiving module is used for obtaining preset power-on and power-off information of each DDR5 memory bank and receiving time information transmitted by the clock chip;
and the control signal transmission module is used for transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, so that the encoder respectively controls the conduction condition of each relay according to the control signal, and respectively controls the power-on and power-off of each DDR5 memory bank.
In order to solve the above technical problem, the present application further provides a DDR5 memory bank power on/off device, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the DDR5 memory bank power-on and power-off method when executing the computer program.
In order to solve the above technical problem, the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the method for powering on and powering off the DDR5 memory bank are implemented.
The DDR5 memory bank power-on and power-off method is applied to a DDR5 memory bank power-on and power-off system; the DDR5 memory bank power on and power off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and the power supply; the method specifically comprises the steps of obtaining preset power-on and power-off information of each DDR5 memory bank and receiving time information transmitted by a clock chip; and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, wherein the encoder is used for controlling the conduction condition of each relay according to the control signal so as to control the power-on or power-off of each DDR5 memory bank respectively. Therefore, according to the scheme, direct power-on and power-off of the DDR5 memory bank can be achieved without plugging and unplugging the memory bank, multiple modes of power-on or power-off of the DDR5 memory bank can be achieved according to preset power-on and power-off information, and more direct impact on the DDR5 memory in the stability test stage is achieved.
In addition, the embodiment of the application also provides a power-on and power-off device, equipment and medium for the DDR5 memory bank, and the effects are the same as the above.
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In order to more clearly illustrate the embodiments of the present application, the drawings required for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic diagram of a DDR5 memory bank power on/off system according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for powering on and powering off a DDR5 memory bank according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another DDR5 memory bank power-on and power-off system provided in the embodiment of the present application;
fig. 4 is a schematic diagram of a DDR5 memory bank power-on and power-off device according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a DDR5 memory bank power-on and power-off device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide a method, a device, equipment and a medium for powering on and powering off a DDR5 memory bank so as to realize direct powering on and powering off of the DDR5 memory bank in a server system.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
DDR5 is a computer memory specification. Compared with a DDR4 memory, the DDR5 memory has stronger standard performance and lower power consumption. Other variations are that the voltage is reduced from 1.2V to 1.1V with 32/40 bits per channel (ECC), bus efficiency is improved, increasing the number of Bank groups prefetched to improve performance, etc. The improved DDR5 functionality will increase the actual bandwidth by 36% compared to DDR4, even starting at 3200MT/s (this statement must be tested) and 4800MT/s speed, which will be 87% higher compared to DDR 4-3200. Meanwhile, one of the most important characteristics of DDR5 is a monolithic chip density exceeding 16 Gb.
A Power Management Integrated Circuit (PMIC) is an application specific integrated circuit that functions as a Power Management circuit for a host system. PMICs are commonly used in devices that have a battery as a power source, such as mobile phones or portable media players. Since such devices generally have more than one power source, such as a battery and a USB power source, and the system needs a plurality of power sources with different voltages, and the charging and discharging of the battery are controlled, satisfying such requirements in a conventional manner occupies a lot of space, and increases the product development time, thereby resulting in the appearance of PMIC. The main function of the PMIC is to control the flow of electricity and the direction of flow to match the needs of the main system. In a plurality of power supplies (e.g., external live current power supply, battery, USB power supply, etc.), power is selected and distributed to various parts of the main system, for example, to provide a plurality of power supplies with different voltages, and to charge the internal battery. Because the system is mostly powered by battery, it is mostly designed with high conversion efficiency to reduce power consumption. The PMIC also includes a number of functions including a DC-DC converter, a Low-dropout regulator (LDO), a battery charger, power selection, dynamic voltage regulation, power on/off sequence control, power voltage detection, and temperature detection.
In DDR5 applications, the PMIC will interact with the CPU through registers and has the ability to manage the three power supplies on the DIMM alone, VDD, VDDQ, and VPP respectively. The power stability of DDR5 DIMMs affects the stability of DDR5 DIMMs. The stability of DDR5 DIMMs in turn affects the stability of the entire server system. A common test method for DDR5 stability is to power up and down the DDR5DIMM, generally perform DC power down by a Baseboard Management Controller (BMC) or a power switch (power button), or directly pull up a server power supply by a tester or an automation device. However, the two power-up and power-down operations are based on power-up and power-down of a server mainboard, and the server mainboard also has a power protection circuit, so that the power-up and power-down operations can play a role in buffering, and effective impact on DDR5 DIMMs is not necessarily formed, and therefore, the power-up and power-down operations have certain limitations. In order to solve the above problems, the present application provides a power-up and power-down method for a DDR5 memory bank, which is intended to directly perform power-up and power-down operations on a DDR5DIMM, so as to verify the stability of the DDR5DIMM more directly, and to prevent the DIMM from being repeatedly plugged and unplugged to a certain extent. The DDR5 memory bank power-on and power-off method provided by the embodiment of the application is applied to a DDR5 memory bank power-on and power-off system.
Fig. 1 is a schematic diagram of a DDR5 memory bank power on/off system according to an embodiment of the present disclosure. As shown in fig. 1, the DDR5 memory bank power on/off system includes a main control chip 10 provided with a crystal oscillator, a clock chip 11, an encoder 12, and a plurality of relays 13; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and the power supply;
it can be understood that the DDR5 memory bank power supply and discharge system mainly comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays. The clock chip is used for providing time information for the main control chip; the encoder is used for receiving the control signal transmitted by the main control chip and further sending a signal to drive the relay to act (switch on or switch off) according to the control signal; the number of the relays is the same as that of the DDR5 memory banks, the relays correspond to the DDR5 memory banks one by one, when the relays are switched on, the DDR5 memory banks are switched on, and when the relays are switched off, the DDR5 memory banks are switched off.
It should be noted that, in this embodiment, specific selection conditions of each device in the power on/off system of the DDR5 memory bank are not limited, and are determined according to specific implementation conditions. Preferably, the main control chip can select a model 430F149, and the relay can select an electromagnetic relay.
Fig. 2 is a flowchart of a DDR5 memory bank power-on and power-off method according to an embodiment of the present disclosure. Based on the above DDR5 memory bank power on/off system, as shown in fig. 2, the method specifically includes:
s10: and acquiring preset power-on and power-off information of each DDR5 memory bank, and receiving time information transmitted by a clock chip.
S11: and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, wherein the encoder is used for controlling the conduction condition of each relay according to the control signal so as to control the power-on or power-off of each DDR5 memory bank respectively.
In order to realize direct power-on and power-off of the DDR5 memory banks, preset power-on and power-off information of each DDR5 memory bank is obtained through a main control chip, and time information transmitted by a clock chip is received. It can be understood that the preset power-on and power-off information of the DDR5 memory bank is the power-on information and the power-off information of the DDR5 memory bank, and specifically includes information on whether the DDR5 memory bank is powered on and whether the DDR5 memory bank is powered off, and further includes information on a power-on sequence, a power-on time, a power-on frequency, a power-off sequence, a power-off time, a power-off frequency, and the like. Through setting up and predetermine the power-on and power-off information, can realize the management of power-on and power-off to each DDR5 memory bank.
Furthermore, the main control chip generates and transmits a control signal to the encoder by combining the time information transmitted by the clock chip, so that the encoder controls the relay to act according to the control signal, and the DDR memory bank is powered on or powered off.
Fig. 3 is a schematic diagram of another DDR5 memory bank power on/off system according to an embodiment of the present application. In a specific implementation, in order to implement the setting of the preset power-on and power-off information, as a preferred embodiment, as shown in fig. 3, the DDR5 memory bank power-on and power-off system further includes a key device 15; the key device 15 is connected to the main control chip 10 and is used for setting preset power-on and power-off information. Meanwhile, the DDR5 memory bank power supply and discharge system can also comprise an upper computer 14; the upper computer 14 is connected with the main control chip 10. The upper computer can be used for setting preset power-on and power-off information and recording power-on and power-off times and power-on and power-off modes of each DDR5 memory bank. Therefore, when the main control chip acquires the preset power-on and power-off information of each DDR5 memory bank, the preset power-on and power-off information of each DDR5 memory bank transmitted by the upper computer can be acquired, and the preset power-on and power-off information of each DDR5 memory bank set by the key device can also be acquired. It should be noted that, in this embodiment, specific selection of the upper computer is not limited, and the upper computer may be a computer or other control equipment, which is determined according to specific implementation conditions.
In order to better enable the user to know the power-on and power-off states of each DDR5 memory bank, as a preferred embodiment, the power-on and power-off system of the DDR5 memory bank may further include a display device 16; the display device 16 is connected with the main control chip and used for displaying the power-up and power-down states of the DDR5 memory banks, so that a user can know the power-up and power-down conditions of the DDR5 memory banks in time.
In this embodiment, the DDR5 memory bank power on/off method is applied to the DDR5 memory bank power on/off system; the DDR5 memory bank power on and power off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and the power supply; the method specifically comprises the steps of obtaining preset power-on and power-off information of each DDR5 memory bank and receiving time information transmitted by a clock chip; and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information so that the encoder can respectively control the conduction condition of each relay according to the control signal to respectively control the power-on and power-off of each DDR5 memory bank. Therefore, according to the scheme, direct power-on and power-off of the DDR5 memory bank can be achieved without plugging and unplugging the memory bank, multiple modes of power-on or power-off of the DDR5 memory bank can be achieved according to preset power-on and power-off information, and more direct impact on the DDR5 memory in the stability test stage is achieved.
In order to make those skilled in the art better understand the technical solution of the present application, the following describes the present application in further detail with reference to the DDR5 memory bank power-up and power-down embodiments.
In specific implementation, the DDR5 memory bank power supply system is connected to a DDR5 memory bank power supply channel pin reserved on a server mainboard. Typically, one Central Processing Unit (CPU) in a server has 8-slot DDR5 memory banks. In this embodiment, an 8 slot DDR5 memory bank is taken as an example.
Specifically, the relays of the DDR5 memory bank power supply and power supply system are respectively connected between the 8 DDR5 memory banks and the power supply, and are respectively denoted as P1, P2, P3, P4, P5, P6, P7, and P8.
When the DDR5 memory bank needs debugging (debug), the preset power-on and power-off information is set to only contain the power-on information of the DDR5 memory bank corresponding to the P1, so that a control signal is transmitted to the encoder according to the preset power-on and power-off information, the encoder further controls the relay P1 according to the control signal to close the P1, and disconnect the P2, the P3, the P4, the P5, the P6, the P7 and the P8, at the moment, the DDR5 memory bank in the CPU channel 0 is powered on, a minimum memory booting system can be formed, and the memory tracing time is shortened.
When debugging is finished and full-function testing of the fully-matched DDR5 memory bank needs to be verified, P1, P2, P3, P4, P5, P6, P7 and P8 can be closed through preset power-on and power-off information, and power supplies of all DDR5 memory banks are conducted. Thereby reducing the operation of plugging and unplugging the memory bank.
In addition, in specific implementation, according to debug requirements, preset power-up and power-down information is set to control the corresponding relay to open or close the power supply of any DDR5 memory bank.
When the DDR5 memory bank stability test is carried out, the server mainboard is started, and P1, P2, P3, P4, P5, P6, P7 and P8 can be closed, so that all DDR5 memory banks are accessed into the server system to wait for normal starting. After the system is started, timing and setting preset power-on and power-off information of each DDR5 memory bank through an upper computer or a key device, and specifically setting a power-on sequence of each DDR memory bank. It can be understood that the power-down sequence can be set in a power-down mode such as common power-down, random power-down, sequential power-down or delayed power-down of each DDR5 memory bank.
Furthermore, after each DDR5 memory bank is powered off, the mainboard starts to be powered off, and the power-off times and the power-off mode can be further recorded through the upper computer. And repeatedly executing power-on and power-off of each DDR5 memory bank by setting preset power-on and power-off information until the times required by the stability test are met.
In summary, the power-on and power-off method of the DDR5 memory bank provided by the application can be used for conducting power-on and power-off control on the DDR channel of the server. And in the debug stage, links of plugging and unplugging the memory bank can be reduced. During the stability test phase, the DDR5DIMM can be powered down in various ways, and a more direct impact is formed on the DDR5 DIMM.
In the above embodiments, the power-on and power-off method of the DDR5 memory bank is described in detail, and the application also provides embodiments corresponding to the power-on and power-off device of the DDR5 memory bank.
Fig. 4 is a schematic diagram of a power on/off device of a DDR5 memory bank according to an embodiment of the present disclosure. The device is applied to a DDR5 memory bank power on and power off system; the DDR5 memory bank power on and power off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of the DDR5 memory banks and corresponds to that of the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and the power supply; as shown in fig. 4, the DDR5 memory bank power-on and power-off device includes:
the obtaining and receiving module 18 is used for obtaining preset power-on and power-off information of each DDR5 memory bank and receiving time information transmitted by the clock chip;
and the control signal transmission module 19 is configured to transmit a control signal to the encoder according to each preset power-on/power-off information and time information, so that the encoder controls the conduction condition of each relay according to the control signal, and controls the power-on or power-off of each DDR5 memory bank respectively.
In this embodiment, the DDR5 memory bank power on/off device includes an acquisition receiving module and a control signal transmission module. The DDR5 memory bank power-on and power-off device is applied to a DDR5 memory bank power-on and power-off system; the DDR5 memory bank power on and power off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; and each relay is respectively arranged between the corresponding DDR5 memory bank and the power supply. The method for realizing the DDR5 memory bank power-on and power-off device is the same as the DDR5 memory bank power-on and power-off method. Specifically, preset power-on and power-off information of each DDR5 memory bank is obtained, and time information transmitted by a clock chip is received; and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, wherein the encoder is used for controlling the conduction condition of each relay according to the control signal so as to control the power-on or power-off of each DDR5 memory bank respectively. Therefore, according to the scheme, direct power-on and power-off of the DDR5 memory bank can be achieved without plugging and unplugging the memory bank, multiple modes of power-on or power-off of the DDR5 memory bank can be achieved according to preset power-on and power-off information, and more direct impact on the DDR5 memory in the stability test stage is achieved.
Fig. 5 is a schematic diagram of a DDR5 memory bank power-on and power-off device according to an embodiment of the present application. As shown in fig. 5, the DDR5 memory bank power on/off device includes:
a memory 20 for storing a computer program;
the processor 21 is configured to implement the steps of the method for powering up and powering down the DDR5 memory bank as mentioned in the above embodiments when executing the computer program.
The DDR5 memory bank power-on and power-off device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The Processor 21 may be implemented in at least one hardware form of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, wherein after being loaded and executed by the processor 21, the computer program can implement the relevant steps of the DDR5 memory bank power-up and power-down method disclosed in any one of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among others, windows, unix, linux, and the like. Data 203 may include, but is not limited to, data involved in DDR5 memory bank power-up and power-down methods.
In some embodiments, the DDR5 memory bank power on/off device may further include a display screen 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the configuration shown in fig. 5 is not limiting to DDR5 memory bank power on and off devices, and may include more or fewer components than shown.
In this embodiment, the DDR5 memory bank power-on and power-off device includes a memory and a processor. The memory is used for storing a computer program; the processor, when executing the computer program, implements the steps of the method for powering up and down the DDR5 memory bank as mentioned in the above embodiments. The method comprises the steps that preset power-on and power-off information of each DDR5 memory bank is obtained, and time information transmitted by a clock chip is received; and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, wherein the encoder is used for controlling the conduction condition of each relay according to the control signal so as to control the power-on or power-off of each DDR5 memory bank respectively. Therefore, according to the scheme, direct power-on and power-off of the DDR5 memory bank can be achieved without plugging and unplugging the memory bank, multiple modes of power-on or power-off of the DDR5 memory bank can be achieved according to preset power-on and power-off information, and more direct impact on the DDR5 memory in the stability test stage is achieved.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is understood that, if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
In this embodiment, a computer program is stored on a computer-readable storage medium, and when executed by a processor, the computer program implements the steps described in the above method embodiments. The method comprises the steps that preset power-on and power-off information of each DDR5 memory bank is obtained, and time information transmitted by a clock chip is received; and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, wherein the encoder is used for controlling the conduction condition of each relay according to the control signal so as to control the power-on or power-off of each DDR5 memory bank respectively. Therefore, according to the scheme, direct power-on and power-off of the DDR5 memory bank can be achieved without plugging and unplugging the memory bank, multiple modes of power-on or power-off of the DDR5 memory bank can be achieved according to preset power-on and power-off information, and more direct impact on the DDR5 memory in the stability test stage is achieved.
The DDR5 memory bank power-up and power-down method, device, equipment and medium provided by the application are provided. A detailed description is given. The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part. It should be noted that, for those skilled in the art, without departing from the principle of the present application, the present application can also make several improvements and modifications, and those improvements and modifications also fall into the protection scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of ...does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A DDR5 memory bank power-on and power-off method is characterized by being applied to a DDR5 memory bank power-on and power-off system; the DDR5 memory bank power on and power off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and a power supply; the method comprises the following steps:
acquiring preset power-on and power-off information of each DDR5 memory bank, and receiving time information transmitted by the clock chip;
and transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information so that the encoder can respectively control the conduction condition of each relay according to the control signal to respectively control the power-on and power-off of each DDR5 memory bank.
2. The DDR5 memory bank power-on and power-off method as claimed in claim 1, wherein the DDR5 memory bank power-on and power-off system further comprises an upper computer;
the upper computer is connected with the main control chip and used for setting the preset power-on and power-off information and recording the power-on and power-off times and power-on and power-off modes of the DDR5 memory banks.
3. The DDR5 memory bank power on/off method as claimed in claim 1, wherein the DDR5 memory bank power on/off system further comprises a key device;
the key device is connected with the main control chip and used for setting the preset power-on and power-off information.
4. The method for powering on and off the DDR5 memory bank as claimed in claim 2, wherein the obtaining the preset powering on and off information of each DDR5 memory bank comprises:
and acquiring the preset power-on and power-off information of each DDR5 memory bank transmitted by the upper computer.
5. The DDR5 memory bank power-on and power-off method as claimed in claim 3, wherein the obtaining of the preset power-on and power-off information of each DDR5 memory bank comprises:
and acquiring the preset power-on and power-off information of each DDR5 memory bank set by the key device.
6. The DDR5 memory bank power on/off method as claimed in claim 1, wherein the DDR5 memory bank power on/off system further comprises a display device;
the display device is connected with the main control chip and used for displaying the power-up and power-down states of the DDR5 memory banks.
7. The DDR5 memory bank power-on and power-off method as claimed in any one of claims 1 to 6, wherein the relay is an electromagnetic relay.
8. A DDR5 memory bank power-on and power-off device is characterized by being applied to a DDR5 memory bank power-on and power-off system; the DDR5 memory bank power-on and power-off system comprises a main control chip provided with a crystal oscillator, a clock chip, an encoder and a plurality of relays; the number of the relays is the same as that of DDR5 memory banks and corresponds to the DDR5 memory banks one by one; the clock chip is connected with the main control chip; the encoder is connected with the main control chip and each relay; each relay is respectively arranged between the corresponding DDR5 memory bank and a power supply; the device comprises:
the obtaining and receiving module is used for obtaining preset power on and power off information of each DDR5 memory bank and receiving time information transmitted by the clock chip;
and the control signal transmission module is used for transmitting a control signal to the encoder according to the preset power-on and power-off information and the time information, so that the encoder respectively controls the conduction condition of each relay according to the control signal, and respectively controls the power-on and power-off of each DDR5 memory bank.
9. A DDR5 memory bank power-on and power-off device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the DDR5 memory bank power on/off method as claimed in any one of claims 1 to 7 when executing said computer program.
10. A computer readable storage medium, characterized in that a computer program is stored thereon, which computer program, when being executed by a processor, realizes the steps of the DDR5 memory bank power-on and power-off method as claimed in any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211625506.2A CN115981437A (en) | 2022-12-16 | 2022-12-16 | DDR5 memory bank power-on and power-off method, device, equipment and medium |
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| CN202211625506.2A CN115981437A (en) | 2022-12-16 | 2022-12-16 | DDR5 memory bank power-on and power-off method, device, equipment and medium |
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| CN (1) | CN115981437A (en) |
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