CN115980543A - Automatic test system and test method for complex high-integration digital-analog hybrid processing micro system - Google Patents

Abstract

The invention discloses an automatic test system and a test method for a complex high-integration digital-analog hybrid processing micro-system, which comprises the following steps: the portable upper computer control system is used for issuing a test instruction, configuring parameters and receiving a test result; the test board card comprises a plurality of power chips, an interface management CPLD chip EPM2210, a core logic and processing SoC chip XC7Z045 and a complex high-integration digital-analog hybrid processing micro-system to be tested; the portable upper computer control system sends the test instruction and the configuration parameters to the complex high-integration digital-analog hybrid processing micro-system through bus arbitration, and then uploads the test data returned by the micro-system to the portable upper computer control system. The invention has high automation degree and good universality, reduces the data processing time, improves the testing efficiency, and provides a solution idea and a method for improving the testability, the testing coverage and other capabilities of a complex high-integration digital-analog hybrid microsystem.

Description

Automatic test system and test method for complex high-integration digital-analog hybrid processing micro system

Technical Field

The invention relates to the technical field of chip testing, in particular to an automatic testing system and a testing method of a complex high-integration digital-analog hybrid processing micro-system.

Background

With the urgent demands of weaponry for high integration, high reliability and miniaturization, it is difficult for a system interconnected at a circuit board level by a plurality of independent packages to satisfy the miniaturization demand. Meanwhile, with the rapid development of electronic technology, the demands for miniaturization, high performance, light weight and low cost of semiconductor chips are also increasing. At present, a highly integrated digital-analog hybrid microsystem that integrates functions of a digital signal processing unit (DSP), a programmable logic unit (FPGA), a digital-analog conversion unit (DAC), an analog-digital conversion unit (ADC), and the like by a System In Package (SiP) technology has been an important development trend in the fields of aerospace, and the like.

With the increasingly complex and diversified requirements on the signal acquisition, signal processing, data interaction and other functional performances of the high-integration digital-analog hybrid micro-system, the number of chips, the packaging integration level and the number of pins in the micro-system are all remarkably improved. However, the size of the microsystem packaged by the SiP technology is almost the same as the conventional chip size, and the accessible path and resources are far inferior to those of the conventional board-level circuit, so the test coverage, test speed and test stability of the microsystem test system are the problems to be solved by the test system. The high-speed signal acquisition and the high-speed data interaction are important functional items of the micro-system, and the high-speed signal acquisition performance and the high-speed data interaction stability of the circuit have important determining functions on the overall performance of the circuit, so that the test of the functional items is necessary and important.

Disclosure of Invention

The invention aims to provide an automatic test system and a test method of a complex high-integration digital-analog mixed processing micro-system, which have good test coverage, test speed and test stability.

In order to achieve the above purpose, the invention is realized by the following technical scheme:

an automatic test system for complex high-integration digital-analog hybrid processing micro-system, comprising: the portable upper computer control system is used for issuing a test instruction, configuring parameters and receiving a test result; the test board card comprises a plurality of power chips, an interface management CPLD chip EPM2210, a core logic and processing SoC chip XC7Z045 and a complex high-integration digital-analog hybrid processing micro-system to be tested; after the portable upper computer control system powers on the power supply and interface management CPLD chip EPM2210, the power supply and interface management CPLD chip EPM2210 respectively powers on the core logic and processing SoC chip XC7Z045 and the complex high-integration digital-analog hybrid processing micro-system to be tested in sequence, and simultaneously monitors the temperature information and the voltage and current information of the test board card; if the JTAG connection exists, managing the JTAG link; the core logic and processing SoC chip XC7Z045 is controlled by a power supply and interface management CPLD chip EPM2210 to be powered on, and then sends a test instruction and configuration parameters to a complex high-integration digital-analog hybrid processing micro-system through bus arbitration, and then uploads test data returned by the micro-system to the portable upper computer control system.

Optionally, the complex high-integration digital-analog hybrid processing micro-system is composed of an analog-digital conversion and data processing module, an FPGA and a PSoC; the micro system is a chip to be tested and is mainly formed by a built-in test module for assisting the whole test according to the test requirement; the test items comprise a multi-channel high-speed ADC acquisition test, a memory DDR3/FLASH test, an on-chip/off-chip GPIO interface test, an on-chip/off-chip high-speed SRIO/PCIE interface test, an off-chip low-speed communication IIC/UART/SPI/CAN interface test and the like, an external gigabit Ethernet test, a signal preprocessing and AI algorithm function performance test.

Optionally, the test board further includes: the temperature monitoring chip and the voltage and current monitoring chip can monitor the temperature and the voltage of the test board card and the related chips in real time in the whole test process.

Optionally, the portable upper computer control system transmits the test instruction and data to the core logic and processing SoC chip XC7Z045 through the gigabit network port, and then transmits the test instruction and data to the complex high-integration digital-analog hybrid processing micro-system through the RS 422; and the portable upper computer control system directly transmits the configuration parameters to the complex high-integration digital-analog hybrid processing micro-system through the RS 422.

Optionally, the portable upper computer control system directly transmits the test instruction and the data to the complex high-integration digital-analog hybrid processing micro-system through an RS422 interface.

Optionally, the analog-to-digital conversion and data processing module in the complex high-integration digital-to-analog hybrid processing micro-system can select a high-speed transmission or common transmission mode for uploading the acquired data;

the high-speed transmission mode is that the FPGA in the micro system is transmitted to PSoC through LVDS, the PSoC is transmitted to a core logic and processing SoC chip XC7Z045 through a high-speed serial SRIO interface, and finally the PSoC is uploaded to the portable upper computer control system through a network port;

the common transmission mode is that the complex high-integration digital-analog hybrid processing micro system is directly transmitted to the portable upper computer control system by the RS 422.

In another aspect, the present invention further provides an automatic testing method for a complex high-integration digital-analog hybrid processing micro system, which uses the above-mentioned automatic testing system for a complex high-integration digital-analog hybrid processing micro system to perform testing, including: a test instruction sent by the portable upper computer control system is forwarded to the complex high-integration digital-analog hybrid processing micro-system by the core logic and processing SoC chip XC7Z 045;

the complex high-integration digital-analog hybrid processing micro-system respectively tests an internal analog-digital conversion and data processing module, the FPGA and the PSoC according to a test instruction; and the test result of each test item is transmitted back to the core logic and processing SoC chip XC7Z045 by the complex high-integration digital-analog hybrid processing micro-system and then transmitted to the portable upper computer control system so as to judge whether each component of the complex high-integration digital-analog hybrid processing micro-system is in a normal working state.

Optionally, the testing of the analog-to-digital conversion and data processing module includes: the system comprises an analog-to-digital conversion and data processing module ADC acquisition test, an LVDS interface test in the micro system and a high-speed serial SRIO interface test in the micro system. The FPGA test comprises a memory DDR3/FLASH test and an on-chip/off-chip GPIO interface test; the PSoC test comprises DDR3/FLASH test of a memory, on-chip/off-chip GPIO interface test, off-chip high-speed SRIO/PCIE interface test, off-chip low-speed communication IIC/UART/SPI/CAN interface test, external gigabit Ethernet test, signal preprocessing and AI algorithm function performance test.

Optionally, the ADC acquisition test for the analog-to-digital conversion and data processing module includes: after the data acquired by each channel is uploaded to the portable upper computer control system by the analog-to-digital conversion and data processing module, the portable upper computer control system analyzes the data and generates configuration parameters according to actual test results, and the configuration parameters are transmitted to the complex high-integration digital-to-analog hybrid processing micro-system while the actual test results are displayed on a measurement and control interface.

The DDR3/FLASH test for the memory comprises the following steps: and selecting one or more memories to test according to the test instruction, and after traversing the addresses of all the memories, transmitting the addresses to the portable upper computer control system by the complex high-integration digital-analog hybrid processing micro-system.

Wherein, to on-chip/off-chip GPIO interface test, include: and according to the test instruction, the input/output direction and the data value of the GPIO to be tested are designated, one BANK or a plurality of BANKs are selected for testing, and after the testing is finished, the test data are transmitted to the portable upper computer control system by the complex high-integration digital-analog hybrid processing micro-system.

The off-chip high-speed SRIO/PCIE interface is connected with the core logic and processing SoC chip XC7Z 045; for the off-chip high-speed SRIO/PCIE interface test, the method comprises the following steps: according to the test instruction, one or all high-speed channels can be selected for testing.

And the complex high-integration digital-analog hybrid processing micro-system judges whether the sent and received data are consistent or not, and transmits the test data after the test to the portable upper computer control system.

The off-chip low-speed communication IIC/UART/SPI/CAN interfaces are connected with the core logic and processing SoC chip XC7Z 045; during testing, one or more communication interfaces can be selected for testing according to the testing instruction.

And the complex high-integration digital-analog hybrid processing micro-system judges whether the sent and received data are consistent or not, and transmits the test data after the test to the portable upper computer control system.

The gigabit network port of the complex high-integration digital-analog hybrid processing micro system is directly connected with the prime number portable upper computer control system; during testing, a portable upper computer control system issues a test instruction according to the test instruction, the complex high-integration digital-analog hybrid processing micro-system transmits the received test instruction back to the portable upper computer control system, and the portable upper computer control system judges whether the sending data is consistent with the receiving data and tests the speed of the gigabit network port.

When the signal preprocessing and AI algorithm function performance test built in the PSoC is carried out, the PSoC carries out signal preprocessing function execution or AI algorithm execution test according to a test instruction, and a test result is transmitted to the core logic and processing SoC chip XC7Z045 through the SRIO interface and then is uploaded to the portable upper computer control system.

Optionally, the portable upper computer control system can respectively display the working states of the analog-to-digital conversion and data processing module, the FPGA and the PSoC of the complex high-integration digital-to-analog hybrid processing micro-system and the test results of the corresponding test item singles according to the returned test data, and if any component of the complex high-integration digital-to-analog hybrid processing micro-system is in an abnormal state, the complex high-integration digital-to-analog hybrid processing micro-system can be displayed and alarm on the measurement and control interface in time.

And the portable upper computer control system displays the temperature, voltage and current information of the test board card in real time on the measurement and control interface, and gives an alarm if the temperature, voltage and current information exceeds a normal range.

The invention has at least one of the following advantages:

aiming at a complex high-integration digital-analog hybrid processing micro system, according to the internal constitution and the practical application requirement of the micro system, an automatic test system and a test method of the complex high-integration digital-analog hybrid processing micro system are provided, the automatic test system consisting of a portable upper computer control system and a test board card realizes the automatic test of the micro system, and has the functions of test result display, test data storage and the like; and respectively realizing the module coverage input/output interface formed by the analog-to-digital conversion and data processing module in the micro system, the FPGA, the PSoC and the like and the functional performance test of the module according to the test method. Meanwhile, the micro system to be tested is fully utilized to construct the internal test universal test module, so that external test resources and software design period are saved, and unstable factors caused by external complicated circuits are avoided

The portable upper computer control system and the test board card in the invention can meet the voltage and current monitoring, various universal interfaces, high and low speed communication interfaces and one-key automatic test of functional performance of a complex high-integration digital-analog hybrid processing micro-system consisting of an analog-digital conversion and data processing module, an FPGA and a PSoC, can perform parameter configuration on the micro-system to be tested on line, effectively improves the flexibility and test efficiency of circuit test, and ensures the test coverage of complex circuits.

The test system has rich communication resources, fully covers the requirements of the micro system in practical application, can meet the requirements of various types of data transmission, and effectively ensures the real-time performance and reliability of the transmission of a large amount of test data. Meanwhile, the method has considerable expansibility and provides reference for testing the microsystems of the same type.

Drawings

FIG. 1 is a block diagram of an automatic testing system of a complex high-integration digital-analog hybrid processing micro-system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a complex high-integration digital-analog hybrid processing micro-system according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a test board card of an automatic test system of a complex high-integration digital-analog hybrid processing micro system according to an embodiment of the present invention;

fig. 4 is a flowchart illustrating a testing method of an automatic testing system of a complex high-integration digital-analog hybrid processing micro system according to an embodiment of the present invention.

Detailed Description

The following describes an automatic testing system and a testing method for a complex high-integration digital-analog hybrid processing micro-system according to the present invention in detail with reference to the accompanying drawings and the detailed description. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise scale for the purpose of facilitating and distinctly aiding in the description of the embodiments of the present invention. To make the objects, features and advantages of the present invention comprehensible, reference is made to the accompanying drawings. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the implementation conditions of the present invention, so that the present invention has no technical significance, and any structural modification, ratio relationship change or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention.

The invention provides an automatic test system of a complex high-integration digital-analog hybrid processing micro system, which consists of a portable upper computer control system and a test board card, wherein a power supply and an interface management CPLD chip EPM2210, a core logic and processing SoC chip XC7Z045 and the complex high-integration digital-analog hybrid processing micro system to be tested are integrated on the test board card, and a to-be-tested micro system is fully utilized to construct an internal test general test module so as to solve the problems of insufficient test coverage, insufficient test efficiency and the like of the complex high-integration digital-analog hybrid processing micro system.

As shown in fig. 1, the present embodiment provides an automatic testing system for a complex high-integration digital-analog hybrid processing micro system, which includes: the portable upper computer control system 100 is used for issuing a test instruction, configuring parameters and receiving a test result.

The test board 200 includes a plurality of power chips and interface management CPLD chips EPM2210, a core logic and processing SoC chip XC7Z045 (XC 7Z045 for short), and a complex high-integration digital-analog hybrid processing microsystem to be tested.

After a power supply in the portable upper computer control system (abbreviated as an upper computer) 100 powers on the power supply and interface management CPLD chip EPM2210 (abbreviated as a CPLD), the power supply and interface management CPLD chip EPM2210 respectively powers on the core logic and processing SoC chip XC7Z045 and the complex high-integrated digital-analog hybrid processing micro-system to be tested in sequence, and simultaneously monitors temperature information and voltage and current information of the test board 200.

If JTAG (JTAG is the short name of joint test operation group, and is the common name of standard 1149.1 of IEEE named as standard test access port and boundary scan structure) is connected, the JTAG link is managed.

The core logic and processing SoC chip XC7Z045 is controlled by the power supply and interface management CPLD chip EPM2210 to be powered on, and then issues a test instruction and configuration parameters to a complex high-integration digital-analog hybrid processing micro system (micro system for short) through bus arbitration, and then uploads test data returned by the complex high-integration digital-analog hybrid processing micro system to the portable upper computer control system 100.

That is, in this embodiment, the portable upper computer control system 100 (the test equipment in the portable upper computer control system 100) controls the test equipment such as the power supply and the signal source, generates the test instruction and the configuration parameter, collects the test result, stores and displays the interface, manages the power supply of the test system, manages the JTAG link and monitors the temperature by the power supply and the interface on the test board 200, issues and uploads the test instruction and the test data by the core logic and processing SoC chip XC7Z045, arbitrates and manages the bus and performs the micro-system cooperative test, responds to the test instruction by the complex high-integration digital-analog hybrid processing micro-system which constructs the general test module for the internal test, updates the configuration parameter as required, and returns the test data and the result.

In this embodiment, the portable upper computer control system transmits the test instruction and data to the core logic and processing SoC chip XC7Z045 through the gigabit network port, and then transparently transmits the test instruction and data to the complex high-integration digital-analog hybrid processing micro-system through RS422 (RS 422 bus); and the portable upper computer control system directly transmits the configuration parameters to the complex high-integration digital-analog hybrid processing micro-system through the RS 422.

In this embodiment, the portable upper computer control system directly transmits the test command and the data to the complex high-integration digital-analog hybrid processing micro-system through the RS422 interface.

In this embodiment, the analog-to-digital conversion and the uploading of the data acquired by the data processing module in the complex high-integration digital-to-analog hybrid processing micro-system may select a high-speed transmission mode or a normal transmission mode.

The high-speed transmission mode is that the high-speed transmission mode is transmitted to a PSoC (PSoC series single chip microcomputer) through an FPGA (field programmable gate array) in a micro system through LVDS (low voltage differential signaling), the PSoC is transmitted to a core logic and processing SoC chip XC7Z045 through a high-speed Serial SRIO (physical layer transmission technology similar to SRIO) interface, and finally the high-speed transmission mode is uploaded to the portable upper computer control system through a network interface.

The common transmission mode is that the complex high-integration digital-analog hybrid processing micro system is directly transmitted to the portable upper computer control system by the RS 422.

FIG. 2 is a block diagram of a complex high-integrated digital-analog hybrid processing micro system under test, which is suitable for the test system of the present invention, as shown in FIG. 2. The complex high-integration digital-analog hybrid processing micro-system consists of an analog-digital conversion and data processing module, an FPGA and a PSoC; the micro system is a chip to be tested and is mainly formed by a built-in test module for assisting the whole test according to the test requirement; the test items comprise multi-channel high-speed ADC acquisition test, memory DDR3/FLASH test, on-chip/off-chip GPIO (bus expander) interface test, on-chip/off-chip high-speed SRIO/PCIE (high-speed serial computer extended bus standard) interface test, off-chip low-speed communication IIC (multi-directional control bus)/UART (universal asynchronous receiver transmitter)/SPI (serial peripheral interface)/CAN (controller area network) interface test, external gigabit Ethernet test, signal preprocessing and AI algorithm function performance test.

FIG. 3 is a schematic diagram of a test board card of an automatic test system of a complex high-integration digital-analog hybrid processing micro system; the test board 200 further includes: the temperature monitoring chip and the voltage and current monitoring chip can monitor the temperature and the voltage of the test board card 200 and the complex high-integration digital-analog hybrid processing micro-system in real time in the whole test process.

The micro system to be tested is arranged on the test board 200, and according to the structural characteristics of the micro system, the test system developed by the embodiment respectively carries out ADC acquisition test and LVDS interface test in the micro system aiming at the analog-to-digital conversion and data processing module of the micro system to be tested; carrying out DDR3/FLASH testing and on-chip/off-chip GPIO interface testing on the memory aiming at the FPGA; the method is characterized by comprising the following steps of carrying out DDR3/FLASH testing of a memory, GPIO interface testing inside/outside a chip, SRIO/PCIE interface testing outside the chip, IIC/UART/SPI/CAN interface testing of low-speed communication outside the chip, ethernet testing outside the chip for thousands of mega, signal preprocessing, AI algorithm function performance testing and the like aiming at PSoC.

In this embodiment, the upper computer may send a test instruction to test the micro system, and as shown in fig. 4, a one-key test procedure of the complex high-integration digital-analog hybrid processing micro system is shown. The micro system to be tested is fixed on the test board card through the clamp, the portable upper computer control system is in initialization connection with the test board card through the network port, the portable upper computer control system issues a self-checking instruction, and the one-key test of the micro system is started after the self-checking of the test board card is successful.

S1: and in the test of the analog-to-digital conversion and data processing module, the portable upper computer control system sends an analog-to-digital conversion and data processing module test instruction to the core logic and processing SoC chip XC7Z045 through the network port and then transmits the instruction to the complex high-integration digital-to-analog hybrid processing micro-system through the RS 422. After the micro system receives the test instruction, the FPGA caches data acquired by the analog-to-digital conversion and data processing ADC, the data are forwarded to the PSoC through LVDS, the PSoC receives the data and then transmits the data to the XC7Z045 through the SRIO interface, and then the data are uploaded to the portable upper computer control system through the network interface for data analysis. After the portable upper computer control system finishes the analysis of the acquired data, configuration parameters of the analog-to-digital conversion and data processing module are generated and are directly transmitted to the analog-to-digital conversion and data processing module of the complex high-integration digital-to-analog hybrid processing micro-system through the RS422 by the portable upper computer control system.

S2: and in the test of the FPGA module, the portable upper computer control system sends an FPGA-memory test or on-chip/off-chip GPIO interface test instruction to XC7Z045 through a network port and then transmits the instruction to the complex high-integration digital-analog hybrid processing micro-system through RS 422. After receiving the memory test instruction, the FPGA respectively carries out address traversal test on the DDR3 and the FLASH and uploads a test result according to an original data path; when the FPGA receives the on-chip/off-chip GPIO interface test, the GPIO input/output direction indication, the data value indication and the BANK indication in the test instruction are extracted, each IO in each BANK indication is tested in sequence according to each indication, and the test result is uploaded according to the original data path.

S3: and in the test of the PSoC module, the portable upper computer control system sends PSoC-memory test, on-chip/off-chip GPIO interface test, off-chip high-speed SRIO/PCIE interface test, off-chip low-speed communication IIC/UART/SPI/CAN interface test, external gigabit Ethernet test, signal preprocessing, AI algorithm function performance test and other instructions to XC7Z045 through a network interface and then is transmitted to a complex high-integration digital-analog hybrid processing micro system through RS 422. After receiving the memory test instruction, the PSoC respectively performs address traversal test on the DDR3 and the FLASH and uploads a test result according to an original data path; when the PSoC receives an off-chip high-speed SRIO/PCIE interface test, data are sent through XC7Z045 of an opposite terminal of the SRIO/PCIE interface, whether the data sent back by the XC7Z045 are consistent or not is compared, and a test result is uploaded according to an original data path; when PSoC receives the interface test of the off-chip low-speed communication IIC/UART/SPI/CAN and the like, data are sent to XC7Z045 of an opposite end through the interfaces of IIC/UART/SPI/CAN and the like, whether the data sent back by XC7Z045 are consistent or not is compared, and a test result is uploaded according to an original data path; after receiving an external gigabit Ethernet test instruction, the PSoC periodically sends data to the micro-system by the upper computer, the micro-system transmits the received test data back to the upper computer, and the upper computer judges whether the sent data is consistent with the received data and tests the speed of the gigabit Ethernet port; when the PSoC receives a signal preprocessing test instruction, the FPGA carries out signal preprocessing on the signal acquired by the analog-digital conversion and data processing module, the processed data is transmitted to the PSoC through LVDS, then transmitted to XC7Z045 through SRIO and then transmitted to an upper computer to display a result; and when the PSoC receives an AI test instruction, an AI algorithm built in the PSoC identifies and processes the analog-to-digital converted signal, and transmits the processed data to XC7Z045 from SRIO and then to an upper computer to display the result.

In addition, the present embodiment further includes the following processes:

all function test items of modules such as an analog-digital conversion and processing module, an FPGA (field programmable gate array), a PSoC (programmable system on chip) and the like in the complex high-integration digital-analog hybrid processing micro system can be synchronously tested.

The portable upper computer control system can directly communicate with the micro system to be tested through the RS422 interface to issue the test instruction and return the test result.

The portable upper computer control system can display the test parameters of each channel of the analog-to-digital conversion and data processing module ADC; on-off test results of each GPIO inside and outside the micro-system chip; the test result of each memory of the FPGA or the PSoC; each SRIO/PCIE test result and the actual transmission rate of the PSoC are external; and the PSoC communicates the test result with the external IIC/UART/SPI/CAN interface.

The test modules or drivers used by the function test items of each module in the complex high-integration digital-analog hybrid processing micro-system are all universal test blocks or drivers, and the test modules or drivers are convenient to be transplanted to other micro-systems with similar functions for testing.

The portable upper computer control system can give an alarm under the conditions that the voltage and the current of the test board card are out of limit and the temperature is out of limit.

To sum up, the test system of the present embodiment is cooperated with an external automatic test board by a circuit built-in test, and includes: the portable upper computer control system is used for generating test instructions and configuration parameters, storing test results and displaying interfaces, controlling test equipment such as a power supply and a signal source and the like; the test board card comprises a power supply and interface management CPLD chip EPM2210, and is used for power supply management, JTAG link management, temperature monitoring and the like of a test system; the system comprises an SoC chip XC7Z045 for core logic and processing, a microprocessor and a microprocessor, wherein the SoC chip XC7Z045 is used for issuing and uploading test instructions and test data, arbitrating and managing a bus and carrying out cooperative test on a micro system; the complex high-integration digital-analog hybrid processing micro-system to be tested is used for constructing a circuit built-in test module, responding to a test instruction, updating configuration parameters as required and returning test data and results.

The embodiment details an automatic test system and a test method for a complex high-integration digital-analog hybrid processing micro-system, an internal general test module is constructed by utilizing the structure of the complex high-integration digital-analog hybrid processing micro-system through the main control of a portable upper computer control system, the cooperation of XC7Z045 of a core logic and processing SoC chip and an EPM2210 of a power supply and interface management CPLD chip, and the voltage and current test of the complex high-integration digital-analog hybrid processing micro-system is completed. By adopting the automatic test system, the number of test instruments, the overhead of additional data transmission and the interference among signals are reduced, the test efficiency is improved, and a solution is provided for the problems that the test coverage rate of chips in a complex hybrid high-integration circuit is low and the test is difficult to develop. The automatic test of the high-integration digital-analog mixed micro system is completed, the test requirement of high efficiency and high coverage is realized, the reference effect is taken for the test and batch production of other complex products, and the popularization significance is realized.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "...," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

It should be noted that the apparatuses and methods disclosed in the embodiments herein can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments herein. In this regard, each block in the flowchart or block diagrams may represent a module, a program, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments herein may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims (10)

1. An automatic test system for complex high-integration digital-analog hybrid processing micro-system, comprising:

the portable upper computer control system is used for issuing a test instruction, configuring parameters and receiving a test result;

the test board card comprises a plurality of power chips, an interface management CPLD chip EPM2210, a core logic and processing SoC chip XC7Z045 and a complex high-integration digital-analog hybrid processing micro-system to be tested;

after the portable upper computer control system powers on the power supply and interface management CPLD chip EPM2210,

the power supply and interface management CPLD chip EPM2210 is used for respectively electrifying the core logic and processing SoC chip XC7Z045 and the complex high-integration digital-analog hybrid processing micro-system to be tested in sequence and monitoring the temperature information and the voltage and current information of the test board card; if the JTAG connection exists, managing the JTAG link;

the core logic and processing SoC chip XC7Z045 is controlled by a power supply and interface management CPLD chip EPM2210 to be powered on, and then sends a test instruction and configuration parameters to a complex high-integration digital-analog hybrid processing micro-system, and uploads test data returned by the micro-system to the portable upper computer control system.

2. The automatic test system of the complex high-integration digital-analog hybrid processing micro-system according to claim 1, wherein the complex high-integration digital-analog hybrid processing micro-system is composed of an analog-digital conversion and data processing module, an FPGA and a PSoC; the micro system is a chip to be tested and is mainly formed by a built-in test module for assisting the whole test according to the test requirement; the test items comprise multi-channel high-speed ADC acquisition test, memory DDR3/FLASH test, on-chip/off-chip GPIO interface test, on-chip/off-chip high-speed SRIO/PCIE interface test, off-chip low-speed communication IIC/UART/SPI/CAN interface test, external gigabit Ethernet test, signal preprocessing and AI algorithm function performance test.

3. The automated test system for complex high-integrated digital-to-analog hybrid processing microsystems of claim 2, wherein the test board further comprises: the temperature monitoring chip and the voltage and current monitoring chip can monitor the temperature and the voltage of the test board card and the complex high-integration digital-analog hybrid processing micro-system in real time in the whole test process.

4. The automatic test system of claim 3, wherein the portable upper computer control system transmits test instructions and data to the core logic and processing SoC XC7Z045 through the gigabit network port, and then transmits the test instructions and data to the complex high-IC mixed-processing microsystem through RS 422; and the portable upper computer control system directly transmits the configuration parameters to the complex high-integration digital-analog hybrid processing micro-system through the RS 422.

5. The automatic test system of claim 3, wherein the portable host control system transmits the test commands and data directly to the HDDA hybrid processing micro system via the RS422 interface.

6. The automatic test system of complex high-integration digital-analog hybrid processing micro-system as claimed in claim 4 or 5,

the analog-to-digital conversion and data processing module in the complex high-integration digital-to-analog hybrid processing micro-system can select a high-speed transmission or common transmission mode for uploading the acquired data;

the high-speed transmission mode is that the FPGA in the micro system is transmitted to PSoC through LVDS, the PSoC is transmitted to a core logic and processing SoC chip XC7Z045 through a high-speed serial SRIO interface, and finally the PSoC is uploaded to the portable upper computer control system through a network port;

the common transmission mode is that the complex high-integration digital-analog hybrid processing micro system is directly transmitted to the portable upper computer control system by the RS 422.

7. An automatic testing method for a complex high-integration digital-analog hybrid processing micro-system, which is characterized in that the automatic testing system for the complex high-integration digital-analog hybrid processing micro-system according to claim 6 is used for testing, and comprises the following steps:

a test instruction sent by the portable upper computer control system is forwarded to the complex high-integration digital-analog hybrid processing micro-system by the core logic and processing SoC chip XC7Z 045;

the complex high-integration digital-analog hybrid processing micro-system respectively tests an internal analog-digital conversion and data processing module, the FPGA and the PSoC according to a test instruction;

and the test result of each test item is transmitted back to the core logic and processing SoC chip XC7Z045 by the complex high-integration digital-analog hybrid processing micro-system and then transmitted to the portable upper computer control system so as to judge whether each component of the complex high-integration digital-analog hybrid processing micro-system is in a normal working state.

8. The method of claim 7, wherein the testing device is a high-level integrated digital-analog hybrid processing micro system,

the test of the analog-to-digital conversion and data processing module comprises the following steps: an analog-to-digital conversion and data processing module ADC acquisition test, an LVDS interface test in a micro system and a high-speed serial SRIO interface test in the micro system;

the FPGA test comprises a memory DDR3/FLASH test and an on-chip/off-chip GPIO interface test;

the PSoC test comprises DDR3/FLASH test of a memory, on-chip/off-chip GPIO interface test, off-chip high-speed SRIO/PCIE interface test, off-chip low-speed communication IIC/UART/SPI/CAN interface test, external gigabit Ethernet test, signal preprocessing and AI algorithm function performance test.

9. The method for automatically testing the complex high-integration digital-analog hybrid processing micro-system according to claim 8,

the ADC acquisition test for the analog-to-digital conversion and data processing module comprises the following steps: after the analog-to-digital conversion and data processing module uploads the data acquired by each channel to the portable upper computer control system, the portable upper computer control system analyzes the data and generates configuration parameters according to an actual test result, and the configuration parameters are transmitted to the complex high-integration digital-to-analog hybrid processing micro-system while the actual test result is displayed on a measurement and control interface;

the DDR3/FLASH test for the memory comprises the following steps: one or more memories are selected to be tested according to the test instruction, and after addresses of all the memories are traversed, the addresses are transmitted to the portable upper computer control system by the complex high-integration digital-analog hybrid processing micro-system;

wherein, to on-chip/off-chip GPIO interface test, include: according to the test instruction, the input/output direction and the data value of the GPIO to be tested are designated, one BANK or a plurality of BANKs are selected for testing, and after the testing is finished, the test data are transmitted to the portable upper computer control system by the complex high-integration digital-analog hybrid processing micro-system;

the off-chip high-speed SRIO/PCIE interface is connected with the core logic and processing SoC chip XC7Z 045; for the off-chip high-speed SRIO/PCIE interface test, the method comprises the following steps: according to the test instruction, one or all high-speed channels can be selected for testing;

the complex high-integration digital-analog hybrid processing micro-system judges whether the sent and received data are consistent or not, and transmits the test data after the test to the portable upper computer control system;

the inter-chip low-speed communication IIC/UART/SPI/CAN interfaces are connected with a core logic and processing SoC chip XC7Z 045; during testing, one or more communication interfaces can be selected for testing according to the test instruction;

the complex high-integration digital-analog hybrid processing micro-system judges whether the sent and received data are consistent or not, and transmits the test data after the test to the portable upper computer control system;

the gigabit network port of the complex high-integration digital-analog hybrid processing micro system is directly connected with the prime number portable upper computer control system; during testing, a portable upper computer control system sends a test instruction according to the test instruction, the complex high-integration digital-analog hybrid processing micro-system returns the received test instruction to the portable upper computer control system, and the portable upper computer control system judges whether the sending data is consistent with the receiving data and tests the speed of the gigabit network port;

when the signal preprocessing and AI algorithm function performance test built in the PSoC is carried out, the PSoC carries out signal preprocessing function execution or AI algorithm execution test according to a test instruction, and a test result is transmitted to the core logic and processing SoC chip XC7Z045 through the SRIO interface and then is uploaded to the portable upper computer control system.

10. The method according to claim 9, wherein the portable upper computer control system is capable of displaying the working states of the adc and data processing module, the FPGA, and the PSoC of the complex high-integration digital-analog hybrid processing micro-system, and the test results corresponding to the test item items, respectively, according to the returned test data, and displaying and alarming on the measurement and control interface in time if any component of the complex high-integration digital-analog hybrid processing micro-system is in an abnormal state;

and the portable upper computer control system displays the temperature, voltage and current information of the test board card in real time on the measurement and control interface, and gives an alarm if the temperature, voltage and current information exceeds a normal range.

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