CN115966566A

CN115966566A - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: CN115966566A
Application number: CN202211463546.1A
Authority: CN
Inventors: 陈常; 严慧; 李思超
Original assignee: Innoscience Zhuhai Technology Co Ltd
Current assignee: Innoscience Zhuhai Technology Co Ltd
Priority date: 2022-11-21
Filing date: 2022-11-21
Publication date: 2023-04-14

Abstract

A nitride-based semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a transistor, a first diode, and a second diode. The second nitride semiconductor layer is provided on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is larger than that of the first nitride semiconductor layer. The transistor is provided on the second nitride semiconductor layer. A first diode is provided on the second nitride semiconductor layer, and a cathode of the first diode is connected to a gate of the transistor. The second diode is disposed on the second nitride semiconductor layer, a cathode of the second diode is connected to a drain of the transistor, and an anode of the first diode is connected to an anode of the second diode, wherein a breakdown voltage of the second diode is smaller than a breakdown voltage of the transistor.

Description

Nitride-based semiconductor device and method for manufacturing the same

Technical Field

The present disclosure generally relates to a nitride-based semiconductor device. More particularly, the present disclosure relates to a nitride-based semiconductor device with non-clamping inductive load switching (UIS) capability.

Background

In recent years, intensive research on High Electron Mobility Transistors (HEMTs) has become very widespread, especially for high power switching and high frequency applications. Group III nitride based HEMTs utilize a heterojunction interface between two materials with different band gaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region to meet the requirements of high power/frequency devices. Examples of devices having heterostructures further include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs), and modulation doped FETs (MODFETs) in addition to HEMTs. To meet more design requirements, HEMT devices need to become smaller. Therefore, in the case of miniaturization of HEMT devices, it is necessary to maintain the reliability of those HEMT devices.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a nitride-based semiconductor device characterized by including a first nitride semiconductor layer, a second nitride semiconductor layer, a transistor, a first diode, and a second diode. A second nitride semiconductor layer is provided on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer. A transistor is provided on the second nitride semiconductor layer. A first diode is disposed on the second nitride semiconductor layer, and a cathode of the first diode is connected to a gate of the transistor. A second diode is disposed on the second nitride semiconductor layer, a cathode of the second diode being connected to the drain of the transistor, and an anode of the first diode being connected to an anode of the second diode, wherein a breakdown voltage of the second diode is smaller than a breakdown voltage of the transistor.

According to an aspect of the present disclosure, there is provided a method for manufacturing a nitride-based semiconductor device, characterized by including the following flow. Forming a second nitride semiconductor layer on the first nitride semiconductor layer; forming a transistor, a first diode, and a second diode on the second nitride semiconductor layer, wherein a breakdown voltage of the second diode is smaller than a breakdown voltage of the transistor; and performing a metal interconnection process such that a cathode of the first diode is connected to a gate of the transistor, a cathode of the second diode is connected to a drain of the transistor, and an anode of the first diode is connected to an anode of the second diode.

According to an aspect of the present disclosure, there is provided a nitride-based semiconductor device characterized by including a first nitride semiconductor layer, a second nitride semiconductor layer, a transistor, a first diode, and a second diode. A second nitride semiconductor layer provided on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer. A transistor is provided on the second nitride semiconductor layer. A first diode is disposed on the second nitride semiconductor layer, and a cathode of the first diode is connected to a gate of the transistor. A second diode is disposed on the second nitride semiconductor layer, a cathode of the second diode being connected to a drain of the transistor, and an anode of the first diode being connected to an anode of the second diode, wherein a breakdown voltage of the first diode is greater than an operating voltage of the transistor.

With the above configuration, the arrangement of the diode can provide the capability of a transistor non-clamped inductive switching (UIS). Specifically, when the transistor is in an off state, if an overvoltage occurs between the drain and the source, clamping can be achieved by using a diode so that the transistor can be turned on again, and thus the voltage between the drain and the source is suppressed, so that the risk of overvoltage breakdown of the transistor can be reduced.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Embodiments of the present disclosure are described in more detail below with reference to the drawings, in which:

fig. 1 is a schematic diagram of an exemplary circuit of a nitride-based semiconductor device, according to some embodiments of the present disclosure.

Fig. 2A shows a schematic diagram of drain-source voltage versus time for a transistor, in accordance with some embodiments of the present disclosure.

Fig. 2B shows a schematic diagram of leakage current through a diode versus time, according to some embodiments of the present disclosure.

Fig. 2C shows a schematic diagram of gate-source voltage versus time for a transistor, according to some embodiments of the present disclosure.

Fig. 3 is a schematic perspective view of a structure of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Fig. 4 is a schematic top view of a structure of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. Embodiments of the present disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions are specified for the orientation of components shown in the associated figures, such as "upper," "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above," "below," and the like, relative to a component or group of components, or a plane of a component or group of components. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner provided that the advantages of the embodiments of the present disclosure are not offset by such arrangements.

Further, it should be noted that in an actual device, due to device manufacturing conditions, the actual shape of the various structures depicted as approximately rectangular may be curved, have rounded edges, have a slightly non-uniform thickness, and so forth. The use of straight lines and right angles is merely for convenience in representing layers and features.

In the following description, a semiconductor device/die/package, a method of manufacturing the same, and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the disclosure; however, the disclosure is written to enable one of ordinary skill in the art to practice the teachings herein without undue experimentation.

Fig. 1 is a schematic diagram of an exemplary circuit of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a transistor 10, a diode D1, a diode D2, an inductor L, and a resistor R. The transistor 10 may be a nitride transistor, for example, the channel and barrier layers may comprise a nitride material. In some embodiments, the transistor 10 may be a GaN-based High Electron Mobility Transistor (HEMT). In some embodiments, transistor 10 may have an enhancement mode and be a normally-off gallium nitride power device. The transistor 10 may include a gate G, a source S, and a drain D. The source S of transistor 10 may be electrically connected to a ground node such that the source S of transistor 10 is at ground potential.

The inductor L may be electrically connected to the drain D of the transistor 10. The inductor L may be electrically connected to a voltage source V1. The inductor L may be electrically coupled between the drain D of the transistor 10 and the voltage source V1. The resistor R may be electrically connected to the gate G of the transistor 10. The resistor R may be electrically connected to the voltage source V2. The inductor L may be electrically coupled between the gate G of the transistor 10 and the voltage source V2. In some embodiments, the voltage source V1 or V2 may be a pulsed voltage, a square wave voltage, or a sine wave voltage.

The cathode of the diode D1 may be connected to the gate G of the transistor 10. The cathode of the diode D1 and the resistor R may be commonly connected to the gate G of the transistor 10. The cathode of diode D2 may be connected to the drain D of transistor 10. The cathode of the diode D2 and the inductor L may be commonly connected to the drain D of the transistor 10. The anode of the diode D1 may be connected to the anode of the diode D2. The diode D1, the diode D2 and the transistor 10 may be integrated on the same epitaxial substrate.

By the arrangement of diodes D1 and D2, the ability of transistor 10 to clamp an inductive load switching (UIS) is provided. Specifically, when the transistor 10 is in an off state, if an overvoltage occurs between the drain D and the source S, clamping can be achieved by using the diode D1 and the diode D2, so that the transistor 10 can be turned on again, and thus the voltage between the drain D and the source S is suppressed, and the risk of overvoltage breakdown of the transistor 10 can be reduced.

The specifications of the diode D1, the diode D2, and the transistor 10 may be configured to achieve the clamping effect. The diode D1 and the diode D2 may be configured to have different specifications. The breakdown voltage of the diode D1 is greater than the operating voltage of the transistor 10, so that a conductive path from the gate G to the drain D through the diode D1 and the diode D2 can be avoided during the normal operation of the transistor 10. The operating voltage of diode D2 is greater than the operating voltage of transistor 10. The breakdown voltage of the diode D2 is smaller than the breakdown voltage of the transistor 10, so that when an overvoltage occurs between the drain D and the source S of the transistor 10, the diode D2 is broken down first, and the transistor 10 is turned on through a conductive path between the diode D1 and the diode D2.

Referring to fig. 2A, fig. 2B, and fig. 2C, the operation state timing sequence shows that an overvoltage occurs between the drain D and the source S when the transistor 10 is turned off. FIG. 2A shows the drain-source voltage V of transistor 10, according to some embodiments of the present disclosure _DS Schematic of the relationship with time. FIG. 2B shows leakage current I through diodes D1 and D2 according to some embodiments of the present disclosure _D1D2 Schematic of the relationship with time. FIG. 2C shows the gate-source voltage V of transistor 10, according to some embodiments of the present disclosure _GS Schematic diagram of time dependence.

Near the time point t1 and before the time point t1 is reached, the drain-source voltage V of the transistor 10 _DS Gradually lifted up. Near the time point t1 and not yet reached the time point t1, the gate-source voltage V of the transistor 10 _GS Gradually decreases and falls below the threshold voltage V of the transistor 10 _th The transistor 10 enters the off-state.

When the time point t1 is reachedDrain-source voltage V of transistor 10 _DS Raising to the reverse breakdown voltage V of diode D2 _{D2_BV} And thus the diode D2 is reverse-breakdown. After reverse breakdown of diode D2, leakage current I _D2D1 Can flow into ground through diode D2, diode D1, resistor R, voltage source V2 in sequence. At this time, due to the leakage current I _D2D1 A voltage drop is generated at the resistor R so that the gate-source voltage V of the transistor 10 _GS Can be raised to the threshold voltage V of the transistor 10 _th . Therefore, the transistor 10 can be turned on again and pull the drain-source voltage VDS low to realize the drain-source voltage V _DS Clamping of (3). Also, therefore, the operating state of the transistor 10 can be in a safe region.

Referring to fig. 3 and 4, fig. 3 is a schematic perspective view of the structure of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure, and fig. 4 is a schematic top view of the structure of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. As described above, the diode D1, the diode D2 and the transistor 10 may be integrated on the same epitaxial substrate. The nitride-based semiconductor device 1A may include a substrate 20, a buffer layer 22, and nitride semiconductor layers 24 and 26.

The substrate 20 may be a semiconductor substrate. Exemplary materials for substrate 20 may include, for example, but are not limited to, si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, a semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)), or other suitable substrate materials. In some embodiments, the substrate 20 may include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 20 may include, for example, but not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof. In some embodiments, the material of the substrate 20 may comprise a silicon substrate having a <111> orientation.

The buffer layer 22 may be disposed between the substrate 20 and the nitride semiconductor layer 24. The buffer layer 22 may be configured to reduce lattice and thermal mismatch between the substrate 20 and the nitride semiconductor layer 24, thereby solving defects caused by the mismatch/difference. Buffer layer 22 may comprise a III-V compound. The III-V compound may include, for example, but not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials of the buffer layer 22 may also include, for example, but not limited to, gaN, alN, alGaN, inAlGaN, or combinations thereof.

In some embodiments, the substrate 20 may further include a nucleation layer (not shown). A nucleation layer may be formed below the buffer layer. The nucleation layer may be configured to provide a transition to accommodate mismatch/differences between the substrate 20 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, for example, but not limited to, alN or any of its alloys.

The nitride semiconductor layer 24 is disposed on/over/above the buffer layer. The nitride semiconductor layer 26 is disposed on/over/above the nitride semiconductor layer 24. Exemplary materials for nitride semiconductor layer 24 may include, for example, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _x Al _y Ga _(1-x-y) N (wherein x + y is less than or equal to 1) and Al _x Ga _(1-x) N (wherein x is less than or equal to 1). Exemplary materials for nitride semiconductor layer 26 may include, for example, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _x Al _y Ga _(1-x-y) N (wherein x + y is less than or equal to 1) and Al _x Ga _(1-x) N (wherein x is less than or equal to 1).

Exemplary materials of the nitride semiconductor layers 24 and 26 are selected such that the bandgap (i.e., forbidden band width) of the nitride semiconductor layer 26 is larger/higher than that of the nitride semiconductor layer 24, which causes the electron affinities thereof to be different from each other and a heterojunction is formed therebetween. For example, when nitride semiconductor layer 24 is an undoped GaN layer having a band gap of about 3.4eV, nitride semiconductor layer 26 may be selected as an AlGaN layer having a band gap of about 4.0 eV. Thus, the nitride semiconductor layers 24 and 26 may function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction.

The diode D1, the diode D2, and the transistor 10 are provided on the nitride semiconductor layer 26. Diode D2 may be located between transistor 10 and diode D1. The further structural composition of the diode D1, the diode D2 and the transistor 10 can be seen in fig. 4. For convenience of description, the lateral direction of fig. 4 is denoted as direction DR1, and the longitudinal direction of fig. 4 is denoted as direction DR2, where direction DR1 is perpendicular to direction DR 2. Diode D1, diode D2, and transistor 10 may be configured along direction DIR 1.

Diode D1 includes electrode 30, electrode 32, and electrode 34. Electrode 30, electrode 32, and electrode 34 are arranged along direction DIR 1.

Electrodes

30, 32, 34 extend along direction DIR 2. Electrode 30 may be electrically connected to electrode 32 and collectively serve as the anode of diode D1. The electrode 34 serves as a cathode of the diode D1.

Diode D2 includes electrode 40, electrode 42, and electrode 44. Electrode 40, electrode 42, and electrode 44 are arranged along direction DIR 1.

Electrodes

40, 42, 44 extend along direction DIR 2. Electrode 40 may be electrically connected to electrode 42 and collectively serve as the anode of diode D2. Electrode 44 serves as the cathode of diode D2.

Transistor 10 includes electrode 102, electrode 104, and electrode 106. Electrode 102, electrode 104, and electrode 106 are arranged along direction DIR 1. Electrodes 102, 104, 106 extend along direction DIR 2. Electrode 102 may serve as the gate of transistor 10 and is connected to electrode 34 of diode D1. Electrode 104 may serve as the drain of transistor 10 and is connected to electrode 44 of diode D2. Electrode 106 may serve as the source of transistor 10.

The connection mode between the diode D1, the diode D2 and the transistor 10 can be realized by metal interconnection. For example, the nitride-based semiconductor device 1A further includes a conductive layer 50. The conductive layer 50 is disposed over the diode D1, the diode D2, and the transistor 10, and includes

sub-layers

502, 504, 506, and 508.

Sub-layers

502, 504, 506, 508 of conductive layer 50 may be directly connected to the underlying components by contact vias. The sub-layer 502 may extend laterally and connect the electrode 102 of the transistor 10 with the electrode 34 of the diode D1 by means of contact vias. The sub-layer 504 may extend laterally and connect the electrode 104 of the transistor 10 with the electrode 34 of the diode D2 by means of contact vias. Sublayer 506 may extend laterally and connect

electrodes

40 and 42 of diode D2 with

electrodes

30 and 32 of diode D1 through contact vias. The sub-layer 508 may extend laterally and connect the electrodes 106 of the transistor 10 by contact vias.

The positioning of the

sub-layers

502, 504, 506, 508 of the conductive layer 50 shown in fig. 4 enables the diodes D1, D2 and the transistor 10 to be configured using a smaller area, thereby increasing the density of components in the nitride-based semiconductor device 1A. For example, by overlapping

sub-layers

506 and 508 in direction DIR1, the area within nitride-based semiconductor device 1A may be efficiently used. Similarly, the diode D2 may be provided between the diode D1 and the transistor 10 so that the area in the nitride-based semiconductor device 1A can be effectively used in order to correspond to the conductive layer 50.

Since the diode D1, the diode D2 and the transistor 10 can be integrated on the same epitaxial substrate, their components can be formed simultaneously using the same process.

In some embodiments, electrode 30 of diode D1, electrode 40 of diode D2, and electrode 102 of transistor 10 may comprise the same material. In some embodiments, the electrode 30 of the diode D1, the electrode 40 of the diode D2, and the electrode 102 of the transistor 10 may be formed by the same conductive layer patterning process. In some embodiments, exemplary materials of the electrode 30 of the diode D1, the electrode 40 of the diode D2, and the electrode 102 of the transistor 10 may be metals or metal compounds including, but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, silicides, doped semiconductors, metal alloys, or combinations thereof.

In some embodiments,

electrodes

32 and 34 of diode D1,

electrodes

42 and 44 of diode D2, and electrodes 104 and 106 of transistor 10 may comprise the same material. In some embodiments, the

electrodes

32 and 34 of the diode D1, the

electrodes

42 and 44 of the diode D2, and the electrodes 104 and 106 of the transistor 10 may be formed by the same conductive layer patterning process in some embodiments. In some embodiments,

electrodes

32 and 34 of diode D1,

electrodes

42 and 44 of diode D2, electrodes 104 and 106 of transistor 10 may comprise, for example and without limitation, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for

electrodes

32 and 34 of diode D1,

electrodes

42 and 44 of diode D2, electrodes 104 and 106 of transistor 10 may include, for example, but are not limited to, ti, alSi, tiN, or combinations thereof. The

electrodes

32 and 34 of diode D1, the

electrodes

42 and 44 of diode D2, and the electrodes 104 and 106 of transistor 10 may be a single layer, or multiple layers of the same or different composition. In some embodiments,

electrodes

32 and 34 of diode D1,

electrodes

42 and 44 of diode D2, electrodes 104 and 106 of transistor 10 form ohmic contacts with nitride semiconductor layer 26. Ohmic contact may be achieved by applying Ti, al, or other suitable materials. In some embodiments, each of

electrodes

32 and 34 of diode D1,

electrodes

42 and 44 of diode D2, and electrodes 104 and 106 of transistor 10 are formed from at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer may include, for example, but not limited to, ti, ta, tiN, al, au, alSi, ni, pt, or combinations thereof. Exemplary materials for the conductive filler may include, for example, but not limited to, alSi, alCu, or combinations thereof.

In some embodiments, the materials of electrode 30 of diode D1, electrode 40 of diode D2, and electrode 102 of transistor 10 are different from the materials of

electrodes

32 and 34 of diode D1,

electrodes

42 and 44 of diode D2, and electrodes 104 and 106 of transistor 10.

In some embodiments, transistor 10 also includes a doped nitride semiconductor layer, which may be disposed between nitride semiconductor layer 26 and electrode 102. By doping the nitride semiconductor layer, the nitride-based semiconductor device 1A can realize an enhancement mode (enhancement mode) in which the enhancement mode device is in a normally-off (normal-off) state. Exemplary materials for the doped nitride semiconductor layer may include, for example, but are not limited to, p-type doped group III-V nitride semiconductor materials, such as p-type gallium nitride (GaN), p-type aluminum gallium nitride (AlGaN), p-type indium nitride (InN), p-type aluminum indium nitride (AlInN), p-type indium gallium nitride (InGaN), p-type aluminum indium gallium nitride (AlInGaN), or combinations thereof. In some embodiments, p-type doping materials can Be achieved by using p-type impurities, such as beryllium (Be), magnesium (Mg), zinc (Zn), cadmium (Cd).

In an aspect of the method of fabricating the nitride-based semiconductor device, the buffer layer 22, the nitride semiconductor layers 24 and 26 may be sequentially formed on the substrate 20. After the epitaxial process of nitride semiconductor layers 24 and 26 is completed, transistor 10, diode D1, and diode D2 are formed on nitride semiconductor layer 26. The transistor 10, the diode D1, and the diode D2 can be formed simultaneously, and their components can be formed through the same process as each other. After the transistor 10, the diode D1, and the diode D2 are formed, a metal interconnection process may be performed to complete the connection relationship among the transistor 10, the diode D1, and the diode D2.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to enable others of ordinary skill in the art to understand the disclosure for various embodiments and with various modifications as are suited to the particular use contemplated.

As used herein, and not otherwise defined, the terms "substantially," "approximately," and "about" are used to describe and contemplate minor variations. When used in conjunction with an event or circumstance, the terms can encompass the occurrence of the event or circumstance specifically and the occurrence of the event or circumstance in approximation. For example, when used in conjunction with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may refer to two surfaces located along the same plane within a few microns, such as two surfaces located along the same plane within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, an element provided "on" or "over" another element may encompass the case that the preceding element is directly on (e.g., in physical contact with) the succeeding element, as well as the case that one or more intervening elements are located between the preceding and succeeding elements.

While the disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be a difference between the process reproduction in this disclosure and the actual equipment. Furthermore, it should be understood that actual devices and layers may deviate from the rectangular layer depiction of the figures and may include corner surfaces or edges, rounded corners, etc. due to fabrication processes such as conformal deposition, etching, etc. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not limiting.

Claims

1. A nitride-based semiconductor device, characterized by comprising:

a first nitride semiconductor layer;

a second nitride semiconductor layer provided on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer;

a transistor provided on the second nitride semiconductor layer;

a first diode disposed on the second nitride semiconductor layer, a cathode of the first diode being connected to a gate of the transistor; and

a second diode disposed on the second nitride semiconductor layer, a cathode of the second diode being connected to the drain of the transistor, and an anode of the first diode being connected to an anode of the second diode, wherein a breakdown voltage of the second diode is smaller than a breakdown voltage of the transistor.

2. The nitride-based semiconductor device according to claim 1, wherein a breakdown voltage of the first diode is greater than an operating voltage of the transistor.

3. The nitride-based semiconductor device according to claim 1, wherein an operating voltage of the first diode is greater than an operating voltage of the transistor.

4. The nitride-based semiconductor device according to claim 3, further comprising a resistor connected to a gate of the transistor in common with a cathode of the first diode.

5. The nitride-based semiconductor device according to claim 1, wherein the first diode includes a first electrode, a second electrode, and a third electrode extending in a first direction, the first electrode serving as a cathode of the first diode, the second electrode being electrically connected to the third electrode and collectively serving as an anode of the first diode.

6. The nitride-based semiconductor device according to claim 5, wherein a material of the third electrode of the first diode is different from a material of the first electrode and the second electrode of the first diode.

7. The nitride-based semiconductor device according to claim 6, wherein a material of the third electrode of the first diode is the same as a material of a gate of the transistor.

8. The nitride-based semiconductor device according to claim 6, wherein a material of the first electrode and the second electrode of the first diode is the same as a material of a drain of the transistor.

9. The nitride-based semiconductor device according to claim 5, wherein a gate and a drain of the transistor extend in the first direction.

10. The nitride-based semiconductor device according to claim 5, wherein the second diode includes a first electrode, a second electrode, and a third electrode extending in the first direction, the first electrode serving as a cathode of the second diode, the second electrode being electrically connected to the third electrode and collectively serving as an anode of the second diode.

11. The nitride-based semiconductor device according to claim 10, wherein the transistor, the first diode, and the second diode are arranged along a second direction, and the first direction is perpendicular to the second direction.

12. The nitride-based semiconductor device according to claim 1, wherein the second diode is located between the transistor and the first diode.

13. The nitride-based semiconductor device according to claim 1, wherein the first diode and the second diode have different specifications.

14. The nitride-based semiconductor device of claim 13, further comprising a conductive layer disposed over the first diode and the second diode and extending laterally to connect the first diode and the second diode.

15. The nitride-based semiconductor device of claim 1, wherein the transistor is a normally-off gallium nitride power device.

16. A method of manufacturing a nitride-based semiconductor device, comprising:

forming a second nitride semiconductor layer on the first nitride semiconductor layer;

forming a transistor, a first diode, and a second diode on the second nitride semiconductor layer, wherein a breakdown voltage of the second diode is smaller than a breakdown voltage of the transistor; and

a metal interconnection process is performed such that a cathode of the first diode is connected to a gate of the transistor, a cathode of the second diode is connected to a drain of the transistor, and an anode of the first diode is connected to an anode of the second diode.

17. The method according to claim 16, wherein a breakdown voltage of the first diode is larger than an operating voltage of the transistor.

18. The method of manufacturing according to claim 16, wherein an operating voltage of the first diode is greater than an operating voltage of the transistor.

19. The method of manufacturing according to claim 18, wherein the transistor is a normally-off gallium nitride power device.

20. The method of claim 16, wherein performing a metal interconnect process comprises forming a conductive layer that extends laterally over the transistor, the first diode, and the second diode.

21. A nitride-based semiconductor device, comprising:

a first nitride semiconductor layer;

a transistor provided on the second nitride semiconductor layer;

and a second diode disposed on the second nitride semiconductor layer, a cathode of the second diode being connected to the drain of the transistor, and an anode of the first diode being connected to an anode of the second diode, wherein a breakdown voltage of the first diode is greater than an operating voltage of the transistor.

22. The nitride-based semiconductor device according to claim 21, wherein a breakdown voltage of the second diode is smaller than a breakdown voltage of the transistor.

23. The nitride-based semiconductor device according to claim 21, wherein an operating voltage of the first diode is greater than an operating voltage of the transistor.

24. The nitride-based semiconductor device according to claim 23, further comprising a resistor connected to a gate of the transistor in common with a cathode of the first diode.

25. The nitride-based semiconductor device according to claim 21, wherein the first diode and the second diode have different specifications.