CN115965048A - Data processing device, data processing method and electronic equipment - Google Patents

Abstract

The utility model provides a data processing device relates to artificial intelligence technical field, especially relates to technical fields such as deep learning, neural network and cloud calculate. The specific implementation scheme is as follows: the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is configured to acquire data to be processed, the data to be processed comprises a plurality of floating point numbers, and exponent bits of the floating point numbers are at least two; the dividing unit is configured to divide the data to be processed into a plurality of sub data to be processed; a quantization unit configured to: quantizing at least one floating point number respectively according to an extreme value in the at least one floating point number and an exponent number of the floating point number in the sub-data to be processed to obtain quantized data, wherein the quantized data comprises a first value and a second value of the floating point number; the processing unit is configured to perform operation processing by using a first value and a second value of a floating point number in the quantized data to obtain a processing result; and an output unit configured to output the processing result. The disclosure also provides a data processing method and electronic equipment.

Description

Data processing device, data processing method and electronic equipment

Technical Field

The disclosure relates to the technical field of artificial intelligence, in particular to the technical fields of deep learning, neural networks, cloud computing and the like, and can be applied to the scenes of image processing, natural language processing, voice recognition, automatic driving, product recommendation and the like. More specifically, the present disclosure provides a data processing apparatus, a data processing method, and an electronic device.

Background

With the development of artificial intelligence technology, deep learning models are widely applied to various scenes. The deep learning model includes a variety of Neural Network (Neural Network) models. A large number of operations involved in the neural network model can be implemented using various data processing devices.

Disclosure of Invention

The disclosure provides a data processing device, a data processing method and an electronic device.

According to an aspect of the present disclosure, there is provided a data processing apparatus including: the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is configured to acquire data to be processed, the data to be processed comprises a plurality of floating point numbers, and the exponent number of the floating point number is at least two; the dividing unit is configured to divide the data to be processed into a plurality of sub data to be processed, wherein the sub data to be processed comprises at least one floating point number; a quantization unit configured to: determining at least one numerical value interval according to an extreme value in at least one floating point number and an exponent number of the floating point number in the sub-data to be processed; the method comprises the steps of quantizing at least one floating point number according to a numerical value interval in which the at least one floating point number is located to obtain quantized data, wherein the quantized data comprise a first value and a second value of the floating point number; the processing unit is configured to perform operation processing by using a first value and a second value of a floating point number in the quantized data to obtain a processing result; and an output unit configured to output the processing result.

According to another aspect of the present disclosure, there is provided a data processing method applied to a data processing apparatus, the method including: acquiring data to be processed, wherein the data to be processed comprises a plurality of floating point numbers, and the exponent number of the floating point number is at least two; determining at least one numerical value interval according to an extreme value in at least one floating point number and an exponent number of the floating point number in the sub-data to be processed; quantizing the at least one floating point number respectively according to the numerical value interval of the at least one floating point number to obtain quantized data, wherein the quantized data comprises a first value and a second value of the floating point number; performing operation processing by using the first value and the second value of the floating point number in the quantized data to obtain a processing result; and outputting the processing result.

According to another aspect of the present disclosure, there is provided an electronic device comprising at least one data processor provided by the present disclosure.

According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method provided in accordance with the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform a method provided according to the present disclosure.

According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the method provided according to the present disclosure.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic illustration of encoding of a floating point number according to one embodiment of the present disclosure;

FIG. 2 is a block diagram of a data processing apparatus according to one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a data processor, according to one embodiment of the present disclosure;

FIG. 4 is a flow diagram of a data processing method according to one embodiment of the present disclosure; and

fig. 5 is a block diagram of an electronic device to which a data processing apparatus may be applied according to one embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of embodiments of the present disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Deep learning techniques may combine low-level features of objects into more abstract high-level features to represent classes or attributes of the objects. Based on deep learning techniques, distributed features of data related to an object can be discovered. The Neural Network model may include, for example, a deep Neural Network model (DNN), a Recurrent Neural Network (RNN), a Convolutional Neural Network (CNN), and the like.

Neural network models involve a large number of computationally intensive operations. These operations may include, for example: matrix multiplication operations, convolution operations, pooling (Pooling) operations, and so forth. In the case of implementing these operations by a Central Processing Unit (CPU), a high time cost is required. To improve the efficiency of applying the neural network model, the operation of the neural network model may be implemented with a neural network processor. The neural network processor may be implemented on the basis of a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or the like. The neural network processor is more computationally efficient. Compared with a general-purpose central processing unit, the computing performance of the neural network processor can be improved by at least one order of magnitude.

The data processed by the neural network processor may be floating point numbers. Floating-point numbers are a concept as opposed to fixed-point numbers. The fixed point number in the computer appoints the position of the decimal point to be unchanged, namely, the position of the decimal point of one number is manually set. For example, for fixed point pure integers, it may be agreed that the decimal point is at the end of the numerical bit. For fixed point pure decimals, for example, it is agreed that the highest order digit of the numerical digit is after the decimal point. Due to the limitation of the word size of a computer, when the data to be represented has a large numerical range, the data cannot be directly represented by fixed-point decimal numbers or fixed-point integers.

The floating-point number may consist of a mantissa M and a opcode E. The floating point number of the number F with base 2 is represented as:

F＝M*2 ^E (formula one)

Encoding rules of floating-point numbers: the mantissa M must be a decimal number, which is represented by an n + 1-bit signed fixed-point decimal number; the number of bits n +1 determines the precision of the floating-point number. The longer the mantissa, the higher the accuracy that can be represented. n is an integer greater than 0. The order code E must be an integer, represented by a k +1 bit signed fixed point integer; the number of bits k +1 determines the numerical range of the floating-point number representation, i.e. the data size or the real position of the decimal point in the data; the step symbol determines the sign of the step code. The longer the gradation code, the larger the range that can be expressed. k is an integer greater than 0

The number of bits m of the floating-point number code is:

m = (n + 1) + (k + 1) (formula two)

The processing of data by the neural network model may include two phases: a training phase and an inference phase. In the training phase, parameters of the neural network model are adjusted by using the known data set to obtain a trained neural network model. During the training phase, the data in the data set needs to have a high accuracy. Data of the type floating point number may be applied in a training phase of the neural network.

Floating Point numbers may include single precision floating Point numbers (Float Point 32, fp32), tensor single precision floating Point numbers (tensorbfloat 32, tf32), half precision floating Point numbers (Float Point 32, fp16), and Brain floating Point numbers (Brain Float Point 16, bf16).

The precision of the single-precision floating point number and the tensor single-precision floating point number is higher. The bit width of the two types of floating point numbers is 32 bits, so that the data amount of the two types of floating point numbers is about twice as large as that of the half-precision floating point numbers, and more computing resources are also needed. When the processing type is data of single-precision floating point number and tensor single-precision floating point number, the performance of the neural network processor is poor. For example, for single precision floating point numbers, the performance of a graphics processor may be 60 TOPS (Tera Operations Per Second, which may operate one trillion Operations Per Second). For tensor single precision floating point numbers, the performance of the graphics processor may be 500 TOPS. The performance of the graphics processor may be 1000 TOPS for half-precision floating point numbers or brain floating point numbers. It can be seen that in the training phase, higher performance can be obtained if half-precision floating point numbers or brain floating point numbers are used.

The fixed point number (for example, the fixed point number of 4 bits or the fixed point number of 8 bits) has a small bit width and a poor precision, and can be applied to an inference stage of a neural network model.

FIG. 1 is a schematic illustration of encoding of a floating point number according to one embodiment of the present disclosure.

Floating point numbers may be represented in a computer by way of encoding. The encoding of floating-point numbers includes a sign bit (sign) 101, an exponent bit (exponent) 102, and a mantissa (fraction) 103.

The sign bit is used to represent the sign of the floating point number. For example, a0 may indicate that the floating point number is a positive number and a1 may indicate that the floating point number is a negative number.

The exponent bits may represent a range of values for a floating point number. For example, the more exponent bits, the wider the range that can be represented.

From the mantissa and exponent bits, the precision of the floating point number can be determined, with the more mantissas, the higher the precision of the floating point number.

In some embodiments, exemplified by the floating point number being a half precision floating point number, the sign bit of the half precision floating point number is 1 bit, the exponent bit may be 5 bits, and the mantissa 10 bits.

If the exponent bits are all 0's and the mantissa is 0, this indicates that the half-precision floating-point number is 0.

If the exponent bits are all 0 and the mantissa is not 0, the half-precision floating-point number FP16 may be:

if the exponent bits are all 1 and the mantissa is 0, then infinity + -inf is indicated.

If the exponent bits are all 1 and the mantissa is Not 0, it is represented as a Not A Number (NAN).

In other cases, the half-precision floating-point number FP16 may be:

the sign bit of the single-precision floating point number is 1 bit, the exponent bit can be 8 bits, and the mantissa can be 23 bits.

The sign bit of the tensor single-precision floating point number is 1 bit, the exponent bit can be 8 bits, and the mantissa can be 10 bits. In some embodiments, some neural network processors may process data of the type single precision floating point or tensor single precision floating point. The exponent number of the single-precision floating point number or the tensor single-precision floating point number is 8 bits, and the range of the number that can be expressed is wide. In addition, the mantissa numbers of the two are more, and the precision is higher. The bit width of a single-precision floating point number or a tensor single-precision floating point number is 32 bits, and the bit width of a half-precision floating point number is 16 bits. The memory resources required for storing single-precision floating point numbers or tensor precision floating point numbers are about twice as much as half-precision floating point numbers, and the hardware resources required for processing single-precision floating point numbers or tensor single-precision floating point numbers are also more than half-precision floating point numbers.

The exponent number of a single-precision floating point number is 5 bits, and the range of numbers that can be represented is small. In the training phase, it may be difficult to converge the model if single precision floating point numbers are used.

The sign bit of the brain-precision floating point number is 1 bit, the exponent bit can be 8 bits, and the mantissa can be 7 bits. In some embodiments, a Tensor Processor (TPU) may process data for a type of brain precision floating point number. The exponent number of the brain-precision floating point number is 8 bits, and the range of representable numbers is wide. The mantissa of a brain precision floating point number is 7 bits, resulting in a brain precision floating point number that is less precise than a single precision floating point number. In the training phase, the use of floating point brain precision may make the model difficult to converge.

In some embodiments, multiple floating point numbers in the data to be processed may be globally quantized. For example, a maximum value may be determined from the plurality of floating point data, and the plurality of floating point data may be quantized according to the maximum value. However, in the case where the number of floating point numbers in the data to be processed is large and the distribution is not uniform, the precision of the global quantization is poor.

In other embodiments, quantization may be based on exponent bits of floating point numbers in order to improve the representation range of the model. The exponent bit of a floating point number is related to the bit width that the floating point number can represent. For example, the floating-point number FP may include 1 sign bit, 3 exponent bits, and 12 mantissa bits. The maximum value Max _0 may be determined from a plurality of floating point numbers FP and then based on the maximum value Max _0 and the first preset value 2 ¹² And 8 data intervals are determined. The 8 data intervals may be, for example: [ max/2 ] ¹² ，max]，(max/2 ²⁴ ，max/2 ¹² ]，(max/2 ³⁶ ，max/2 ²⁴ ]，(max/2 ⁴⁸ ，max/2 ³⁶ ]，(max/2 ⁶⁰ ，max/2 ⁴⁸ ]，(max/2 ⁷² ，max/2 ⁶⁰ ]，(max/2 ⁸⁴ ，max/2 ⁷² ]，(max2 ⁹⁶ ，max/2 ⁸⁴ ]. With 3 exponent bits included, the bit width that can be represented is up to 96. However, in most application scenarios, a floating point number of 3 exponent bits can represent a bit width much larger than the range required for model training or reasoning. In addition, too many bits can be represented, which may reduce the accuracy of the model.

In the case of a floating-point number comprising 2 exponent bits, the bit width that can be represented is moderate, and it is also applicable to most application scenarios. Based on this, the present disclosure provides a data processing apparatus for a floating-point number including 2 or more exponent bits, which will be described below.

Fig. 2 is a block diagram of a data processing apparatus according to one embodiment of the present disclosure.

As shown in fig. 2, the apparatus 200 may include an acquisition unit 210, a dividing unit 220, a quantization unit 230, a processing unit 240, and an output unit 250.

An obtaining unit 210 configured to obtain data to be processed.

In embodiments of the present disclosure, the data to be processed may include a plurality of floating point numbers.

For example, the data to be processed may include first data to be processed. The first data to be processed may be a matrix. The matrix includes a plurality of floating point numbers. For another example, the first data to be processed may be a 16 × 1 matrix, which may include 16 floating point numbers.

In embodiments of the present disclosure, the exponent bits of a floating point number may be at least two. For example, the sign bit of a floating point number may be 1 bit, the exponent bit of the floating point number may be greater than or equal to 2 bits, and the floating point number may be 16 bits. For another example, the sign bit of a floating-point number may be 1 bit, the exponent bit of a floating-point number may be 2 bits, and the mantissa of a floating-point number may be 13 bits.

The dividing unit 220 is configured to divide the data to be processed into a plurality of sub-data to be processed.

In an embodiment of the disclosure, the sub-data to be processed includes at least one floating point number. For example, the first data to be processed may be divided into two first sub-data to be processed. Each of the first to-be-processed sub-data may include 8 floating-point numbers.

A quantization unit 230 configured to: determining at least one numerical value interval according to an extreme value in at least one floating point number and an exponent number of the floating point number in the sub-data to be processed; and quantizing the floating point number according to the numerical value interval of each floating point number to obtain quantized data.

In an embodiment of the present disclosure, the extreme value may include a maximum value. For example, the first to-be-processed sub Data _ A1 may include a plurality of floating point numbers. If the exponent number of the floating-point number is 2, 2 can be determined ² A numerical interval. In these numerical intervals, the maximum value Max _ A1 of the floating-point number may be 2 ² A data threshold Max _0A1 for the first of the number intervals. First valueAnother data threshold value Max _1A1 in the interval may be scaled from the extremum. The first interval of values may be: max _1A1 to Max _0A1.

In the embodiment of the present disclosure, the number of quantized data may be consistent with the number of sub-data to be processed.

For example, the sub data to be processed is 2, and the quantization data may be 2.

In an embodiment of the disclosure, the quantized data comprises a first value and a second value of a floating point number.

For example, the quantized data may comprise a first value and a second value, respectively, of at least one floating point number.

For example, for the first to-be-processed sub-Data _ A1, taking the floating point number FP _ a11 and the floating point number FP _ a12 in the first numerical value interval as an example, scaling is performed according to the Data threshold value Max _0A1, and the obtained numerical value is used as the first value of the floating point number FP _ a11 and the floating point number FP _ a 12. The absolute value of the floating-point number may be used as a dividend, and the first value may be used as a divisor, and a division operation may be performed to obtain a second value of the floating-point number. In one example, the data threshold Max _0A1 may be scaled with a first preset value Pre _ 1. The first value FP _ A11F1 of the floating point number FP _ A11 may be Max _0A1/Pre _1, the second value FP _ A11F2 may be (FP _ A11v/Max _0A 1) × Pre _1, FP _A11v is the absolute value of the floating point number FP _ A11. The first value FP _ A1_2F1 of the floating point number FP _ a12 may be Max _0A1/Pre _1, the second value FP _ a12F2 may be (FP _ a12v/Max _ a 01) × Pre _1, FP _a12v is the absolute value of the floating point number FP _ a 12.

And the processing unit 240 is configured to perform operation processing by using the first value and the second value of the floating point number in the quantized data to obtain a processing result.

In the embodiments of the present disclosure, various operations may be performed using quantized data.

For example, the various operations may include: matrix multiplication, pooling, convolution, and the like. The processing unit 240 may perform an arithmetic operation using the first value and the second value of a part or all of the floating-point numbers to obtain a processing sub-result.

An output unit 250 configured to output the processing result.

For example, after a part of the processing sub-results of the floating-point number are obtained, these processing sub-results may be taken as the processing results, and the processing results may be output.

According to the embodiment of the disclosure, the data to be processed is divided, and the floating point number in the sub-data to be processed obtained after division is quantized, so that the precision of the processing device can be greatly improved. In addition, the quantized data is used for operation, so that the hardware resource overhead required by operation can be reduced, the operation efficiency is improved, and the performance of the processing device is improved. In addition, when the exponent number of the floating point number is 2, the precision of the processing device can be further improved, and the hardware resource overhead can be further reduced, which contributes to improvement of the processing efficiency.

It is understood that the processing apparatus provided in the present disclosure is described in detail above by taking 1 to-be-processed data as an example, but the present disclosure is not limited thereto. In the disclosed embodiments, the data to be processed may be at least one. For example, the 2 data to be processed may be 2 matrices having different dimensions.

It is to be understood that the processing apparatus provided in the present disclosure has been described in detail above by taking the first value and the second value of the quantized data including floating point numbers as an example, but the present disclosure is not limited thereto. In embodiments of the present disclosure, floating point numbers may be quantized to more than two numerical values.

It will be appreciated that the extremum may also include a minimum value.

It will be appreciated that in embodiments of the present disclosure, the square value of a floating point number may be determined using the first and second values of the floating point number in the quantized data.

For example, for the floating-point number FP _ a11, the processing sub-result FP _ a11sq may be determined by:

FP _ a11sq = FP _ a11F2 FP _ a11F1 (formula five)

It is understood that the type of floating point number may be various types of floating point numbers in embodiments of the present disclosure. For example, the quantization unit 230 may quantize various types of floating point numbers such as a single-precision floating point number, a tensor single-precision floating point number, a half-precision floating point number, a brain floating point number, and the like. And the processing unit 240 may perform an operation according to the first value and the second value of the corresponding floating point number to obtain a processing result. Through the embodiment of the disclosure, the processing device 200 of the disclosure can be used for processing various data with different precisions, and has extremely strong compatibility.

In some embodiments, the processing apparatus provided by the present disclosure may further include: and the storage unit is coupled with the quantization unit and the processing unit and is used for storing the quantized data from the quantization unit.

In the embodiment of the present disclosure, the storage unit may be a built-in cache unit.

For example, a memory cell may include a plurality of memory sub-cells. The first storage subunit is used for storing the quantized data.

For another example, the memory unit may also include different memory partitions, one for storing quantized data.

It is to be understood that the whole of the processing apparatus is described in detail above, and the dividing unit of the present disclosure will be described in detail below with reference to the related embodiments.

In some embodiments, the dividing unit may include: the first determining module may be configured to determine the number of floating point numbers in the sub-data to be processed according to data distribution information of a plurality of floating point numbers in the data to be processed. The dividing module may be configured to divide the to-be-processed data into a plurality of to-be-processed sub data according to the number of floating point numbers in the to-be-processed sub data.

In the embodiment of the disclosure, the data distribution information may indicate the distribution condition of a plurality of floating point numbers in the data to be processed. For example, the data distribution information may indicate that the plurality of floating point numbers are evenly distributed. For another example, the data distribution information may also indicate that the plurality of floating point numbers are unevenly distributed.

In an embodiment of the disclosure, the first determining module is further configured to: and determining the number of the floating point numbers in the sub-data to be processed as a first preset parameter value in response to the fact that the data distribution information indicates that the floating point numbers in the data to be processed are uniformly distributed.

In the embodiment of the disclosure, in response to determining that the data distribution information indicates that the plurality of floating point numbers in the to-be-processed data are unevenly distributed, determining that the number of floating point numbers in the to-be-processed sub-data is a second preset parameter value, wherein the first preset parameter value is larger than the second preset parameter value. Through the embodiment of the disclosure, when the data are uniformly distributed, the number of floating point numbers in the sub-data to be processed is large, so that the quantization processing efficiency can be improved, and the operating efficiency of the processing device is further improved. When the data distribution is not uniform, the number of floating point data in the sub-data to be processed is less, which is beneficial to improving the precision of the processing device.

It is to be understood that the above describes the partition unit of the present disclosure, and the quantization unit of the present disclosure is further described with reference to the related embodiments.

In some embodiments, the quantization unit 230 may include: the second determining module may be configured to determine an interval number of the numerical interval based on the exponent bit of the floating point number. The third determining module may be configured to determine at least one numerical value interval according to an extremum value of at least one floating point number in the sub data to be processed. And the quantization module can be configured to quantize the floating point number according to the numerical value interval of the floating point number to obtain quantized data. A writing module may be configured to write the quantized data to the storage unit.

The determination module of the quantization unit will be described in detail below with reference to related embodiments.

In an embodiment of the disclosure, the second determining module may be configured to determine the number of intervals of the numerical value interval according to an exponent bit of the floating point number. For example, if the exponent number of the floating point number is 2, the number of intervals of the data interval can be determined to be 2 ² And (4) respectively. For another example, if the exponent number of the floating point number is 3, the number of sections in the data section can be determined to be 2 ³ And (4) respectively.

In an embodiment of the present disclosure, the third determining module may be configured to: and determining at least one data threshold according to the first preset value, the extreme value and the number of the intervals.

For example, the number of intervals may be I. It will be appreciated that where the exponent number of a floating point number is 2, I may be 4 (2) ² )。

For example, the first preset value may be 2 ¹³ . For example, the extremum may be a maximum value.

In an embodiment of the present disclosure, the at least one data threshold is I +1 data thresholds. For example, the number of data thresholds may correspond to the number of intervals. For another example, when the number of intervals I is 4, the number of data thresholds may be 5.

In an embodiment of the present disclosure, the third determining module may be further configured to: an extremum may be determined as the 1 st data threshold.

For example, if the data to be processed is divided into K sub-data to be processed. For a plurality of floating point numbers in the kth to-be-processed sub-Data _ k, the maximum value may be taken as the 1 st Data threshold Max _0k. K is an integer greater than 1, and K is an integer greater than or equal to 1 and less than or equal to K.

In an embodiment of the present disclosure, the third determining module may be further configured to: the (i + 1) th data threshold can be determined according to the ith data threshold and the first preset value.

For example, I is an integer greater than or equal to 1, and I is an integer less than or equal to I. In one example, taking I =4 as an example, I may have a value range of 1, 2, 3, 4.

For example, the data threshold may be determined by the following equation:

it can be understood that Max _1k, max _2k, max _3k, and Max _4k are the 2 nd Data threshold, the 3 rd Data threshold, the 4 th Data threshold, and the 5 (I + 1) th Data threshold, respectively, for the kth to-be-processed sub Data _ k.

In an embodiment of the present disclosure, the third determining module may be further configured to: at least one value interval is determined based on at least one data threshold.

For example, the determination module may be further configured to: and determining an ith numerical value interval according to the ith data threshold and the (i + 1) th data threshold.

For example, corresponding to the kth to-be-processed sub Data _ k, the 1 st numerical value interval Max _1k to Max _0k may be determined according to the 1 st Data threshold Max _0k and the 2 nd Data threshold Max _1k. The 2 nd numerical range Max _2k to Max _1k may be determined according to the 2 nd data threshold Max _1k and the 3 rd data threshold Max _2k. The 3 rd numerical intervals Max _3k to Max _2k may be determined based on the 3 rd data threshold Max _2k and the 4 th data threshold Max _3k. The 4 th numerical intervals Max _4k to Max _3k may be determined according to the 4 th data threshold Max _3k and the 5 th data threshold Max _4 k.

It is to be understood that the determination module of the quantization unit is described in detail above. The quantization module of the quantization unit will be described in detail below with reference to related embodiments.

In embodiments of the present disclosure, the quantization module may be configured to: and obtaining a first value of the floating point number according to the target data threshold value and the first preset value. And obtaining a second value of the floating point number according to the first preset value, the floating point number and the target data threshold value.

For example, the target data threshold is the greater of the two data thresholds associated with the numerical interval in which the floating point number is located.

For example, for a floating point number FP _ k in the kth to-be-processed sub data, if an absolute value FP _ kv of the floating point number FP _ k is in the ith number interval (Max _ i +1k < FP _ kv < Max _ ik), the target data threshold of the floating point number FP _ k is: the larger ith data threshold value Max _ ik of the two data threshold values (Max _ ik and Max _ i +1 k) of the ith numerical interval.

The first preset value may be 2 ¹³ The first value FP _ kF1 of the floating-point number FP _ k may be：

The second value FP _ kF2 of the floating-point number FP _ k may be:

it is to be understood that the quantization module of the quantization unit is described in detail above, and the writing module of the quantization unit is described in detail below with reference to the related embodiments.

In an embodiment of the present disclosure, the writing module is configured to write the quantized data into the storage unit.

For example, the first value FP _ kF1 and the second value FP _ kF2 of the floating-point number FP _ k may be written to the storage unit.

It is understood that, as described above, taking I =4 as an example, the ith numerical value interval may be any one of the 1 st numerical value interval to the 4 th numerical value interval.

In some embodiments, the quantized data comprises function data associated with the target processing function and the first and second values of the target floating point number associated with the target processing function.

For example, a neural network model may be used to process floating point data. The neural network model may include a plurality of processing functions that themselves also have a large number of parameters, which may also be floating point numbers. The parameters of a processing function may be used as the data to be processed associated with the processing function. The data to be processed can also be represented by a matrix, and all or part of elements in the matrix are floating point numbers. The function data related to the processing function can be obtained by quantizing the data to be processed.

As another example, a processing function may process one or several input floating point numbers. The target floating-point number may be an input to the processing function.

For another example, the target floating point number and the pending data associated with the processing function may be from different pending data. In one example, the target processing function may be a convolution kernel. The parameters of the convolution kernel can be implemented as a matrix of 3*3. The 3*3 matrix includes 9 floating point numbers. And quantizing the 3*3 matrix serving as data to be processed to obtain function data of a target processing function. The function data includes a first value and a second value for each of the 9 floating point numbers.

It is to be understood that the quantization unit of the present disclosure is described in detail above. The processing unit of the present disclosure will be described in detail below with reference to related embodiments.

In some embodiments, the processing unit 240 may include: a read module may be configured to read a target processing function and first and second values of a target floating point number associated with the target processing function from a storage unit. And the processing module can be configured to process the first value and the second value of the target floating point number by using the target processing function to obtain a processing result.

For example, the read module may read the function data and the target floating point number of the target processing function.

For example, the target floating-point number may be at least one.

In the embodiment of the present disclosure, the data to be processed may include first data to be processed and second data to be processed. The plurality of sub-data to be processed includes: the data processing device comprises a plurality of first to-be-processed sub-data from first to-be-processed data and a plurality of second to-be-processed sub-data from second to-be-processed data. The target floating point number includes: a first target floating point number from the first to-be-processed sub-data and a second target floating point number from the second to-be-processed sub-data. For example, the target floating point numbers related to the target processing function Fun _ t1 are respectively from the first Data to be processed Data _ a and the second Data to be processed Data _ B. The first Data to be processed Data _ a may be divided into K first sub-Data to be processed. The second Data to be processed Data _ B may also be divided into K second sub Data to be processed. A first target floating point number from the kth first to-be-processed sub-Data _ Ak may be a floating point number FP _ A1k. One second target floating point number from the kth second to-be-processed sub Data _ Bk may be a floating point number FP _ B1k. The target processing function Fun _ t1 may be a multiplication function for calculating the product of two floating-point numbers.

In an embodiment of the present disclosure, the processing module may be further configured to: and determining the target sign bit according to the sign bit of the target floating point number.

For example, the sign bits of the first target floating point number and the second target floating point number may be bitwise xored, with the result being the target sign bit. In one example, the sign bit of the floating point number FP _ A1k and the sign bit of the floating point number FP _ B1k may be subjected to bitwise xor to obtain a target sign bit.

In an embodiment of the disclosure, the processing module is further configured to: and processing the first value and the second value of the target floating point number by using the target processing function to obtain the absolute value of the output floating point number.

For example, the processing module is further configured to: and multiplying the first value and the second value of the first target floating point number and the first value and the second value of the second target floating point number in sequence to obtain the absolute value of the output floating point number.

In one example, the absolute value of the output floating point number, FP _ AB1kv, may be determined by the following formula:

FP _ AB1kv = FP _ A1kF2 FP _ B1kF2 FP _ A1kF1 FP _ B1kF1 (formula twelve)

FP _ A1kF1 is the first value of the floating-point number FP _ A1k, and FP _ A1kF2 is the second value of the floating-point number FP _ A1k. FP _ B1kF1 is the first value of the floating-point number FP _ B1k, and FP _ B1kF2 is the second value of the floating-point number FP _ B1k.

In an embodiment of the disclosure, the processing module is further configured to: and obtaining the output floating point number according to the absolute value of the output floating point number and the target sign bit.

For example, the output floating point number FP _ AB1k may be determined from the absolute value FP _ AB1kv of the output floating point number and the target sign bit.

In an embodiment of the disclosure, the processing module is further configured to: and obtaining a processing result according to the output floating point number.

For example, in the case where the target processing function is related only to the floating-point number FP _ A1k and the floating-point number FP _ B1k, the floating-point number FP _ AB1k may be output as the processing result.

In an embodiment of the disclosure, the processing module is further configured to: and converting the processing result into a floating point number to obtain a converted processing result. Through the embodiment of the disclosure, the output result is also a floating point number, and the compatibility of the processing device can be further improved.

In an embodiment of the disclosure, the output module is further configured to: and outputting the converted processing result.

It will be appreciated that the above has described the processing device of the present disclosure in detail, and that the principles of the processing device of the present disclosure will be described in detail below with reference to fig. 3 and related embodiments.

Fig. 3 is a schematic diagram of a data processing apparatus according to one embodiment of the present disclosure.

As shown in fig. 3, the acquisition unit 310 may acquire the data to be processed from other devices and store the data to be processed in the off-chip storage unit 370. The obtaining unit 310 may be a Direct Memory Access (DMA) unit. For example, the data to be processed may include a plurality of floating point numbers. The exponent number of the floating point number may be 2.

After acquiring the data to be processed, the dividing unit 320 may read the corresponding data to be processed from the off-chip storage unit 370. The dividing unit 320 may divide the data to be processed into a plurality of sub data to be processed.

Next, the quantization unit 330 may quantize a plurality of floating point numbers of each of the plurality of to-be-processed sub-data. For example, at least one numerical value interval is determined according to an extreme value of a plurality of floating point numbers and an exponent number of the floating point number in the sub data to be processed; and quantizing the at least one floating point number of the sub-data to be processed respectively according to the numerical value interval of the at least one floating point number to obtain quantized data. In an embodiment of the present disclosure, quantizing the data includes: the method includes the steps of receiving function data associated with a target processing function and first and second values of a target floating point number associated with the target processing function.

The quantized data is written into the memory cell according to the type of the quantized data. The Memory unit may be an on-chip Static Random Access Memory (SRAM) Memory. In the embodiment of the present disclosure, the storage unit includes a first storage unit 361 and a second storage unit 362. The function data may be stored in the first storage unit 361 and the first and second values of the target floating point number may be stored in the second storage unit 362. The first storage unit 361 can also be called a model SRAM storage unit, and the second storage unit 362 can also be called an input SRAM storage unit.

The data to be processed may include a plurality of floating point numbers, and the quantized data may include first and second values of the plurality of floating point numbers.

The processing unit 340 may process the first value and the second value of the target floating point number by using the target processing function to obtain a processing sub-result. The processed sub-results may be converted to a floating point number format and cached in the output unit 350. After the processing unit 340 completes the processing, the output unit 350 may output a plurality of processing sub-results as a processing result to the off-chip storage unit 370. Output cell 350 may also be referred to as a resulting SRAM cell.

The processing apparatus of the present disclosure will be described in further detail with reference to the related embodiments.

In some embodiments, the acquisition unit is configured to acquire data to be processed. For example, the Data to be processed may include first Data to be processed Data _ a and second Data to be processed Data _ B.

The first Data to be processed, data _ a, may be represented by a matrix of 1 row and 16 columns, data _ a = [1.0,2.0,3.0,4.0,5.0,6.0,7.0,8.0,9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0].

The second Data to be processed, data _ B, can be represented by a matrix with 16 rows and 1 columns, and the transposed Data _ B = [0.004,4.0,6.0,8.0, 10.0, 12.0, 14.0, 16.0, 18.0, 20.0, 22.0, 24.0, 26.0, 28.0, 30.0, 32.0]. It is to be understood that, for ease of understanding, in the present embodiment, a plurality of floating point numbers in the first Data to be processed Data _ a and the second Data to be processed Data _ B are each expressed in decimal.

It is understood that the decimal number corresponding to the floating point number FP _ a11 of the first Data to be processed Data _ a described above may be 1.0. The decimal number corresponding to the floating point number FP _ a12 of the first Data to be processed may be 2.0. The decimal number corresponding to the floating point number FPB1k of the Data _ B to be processed may be 0.004.

In some embodiments, the dividing unit is configured to divide the data to be processed into a plurality of sub-data to be processed. For example, the first Data to be processed Data _ a may be divided into the first sub-Data to be processed Data _ A1 and the first sub-Data to be processed Data _ A2. The first to-be-processed sub Data _ A1= [1.0,2.0,3.0,4.0,5.0,6.0,7.0,8.0], the first to-be-processed sub Data _ A2= [9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0]. For another example, the second to-be-processed Data _ B may be divided into the second to-be-processed sub Data _ B1 and the second to-be-processed sub Data _ B2. The second to-be-processed sub Data _ B1= [0.004,4.0,6.0,8.0, 10.0, 12.0, 14.0, 16.0], the second to-be-processed sub Data _ B2= [18.0, 20.0, 22.0, 24.0, 26.0, 28.0, 30.0, 32.0].

In some embodiments, the quantization unit is configured to: determining at least one numerical value interval according to an extreme value of a plurality of floating point numbers and an exponent number of the floating point number in the sub data to be processed; and quantizing the at least one floating point number respectively according to the numerical value interval of the at least one floating point number to obtain quantized data. The quantized data includes a first value and a second value of the floating point number. For example, the maximum value Max _ A1 is 8.0 for the first to-be-processed sub Data _ A1. For the second to-be-processed sub Data _ B1, the maximum value Max _ B1 is 16.0.

For the first to-be-processed sub Data _ A1, the maximum value Max _ A1 may be taken as the 1 st Data threshold Max _0A1. For the second to-be-processed sub Data _ B1, the maximum value Max _ B1 may be the 1 st Data threshold Max _0B1. Next, a plurality of other Data threshold values of the first to-be-processed sub Data _ A1 and the second to-be-processed sub Data _ B1 may be determined using the above-described formulas six to nine, respectively.

For the first to-be-processed sub-Data _ A1, the 2 nd Data threshold Max _1A1 may be 0.000976563, and the 3 rd Data threshold Max _2A1 may be 1.19209 × 10 ^-7 . For the first to-be-processed sub-Data _ A1, the first 2 value intervals of the plurality of value intervals are: 0.000976563-8.0, 1.19209 x 10 ^-7 0.000976563. The floating point number FP _ a11 corresponding to the decimal Data "1.0" in the first to-be-processed sub-Data _ A1 may be in the 1 st numerical value section 0.000976563-8.0.

For the second to-be-processed sub-Data _ B1, the 2 nd Data threshold Max _1B1 may be 0.001953125, and the 3 rd Data threshold Max _2B1 may be 9.5367431640625 × 10 ^-7 . For the second to-be-processed subdata Data _ B1, the first 2 numerical value intervals of the plurality of numerical value intervals are respectively: 0.001953125-16.0, 2.38419 x 10 ^-7 0.001953125. The floating point number FP _ B11 corresponding to the decimal number 0.004 in the second to-be-processed sub-Data Data _ B1 is located in the 1 st numerical value interval 0.001953125-16.

In some embodiments, the processing unit is configured to perform arithmetic processing by using the first value and the second value of the floating point number in the quantized data, and obtain a processing result.

For example, the processing unit may multiply the quantized Data of the first sub-Data _ A1 to be processed and the quantized Data of the second sub-Data _ B1 to be processed. During this process, the following data may be multiplied: the first value and the second value of the 1 st floating point number FP _ a11 of the first to-be-processed sub Data _ A1, and the first value and the second value of the 1 st floating point number FP _ B11 of the second to-be-processed sub Data _ B1.

The decimal number corresponding to the 1 st floating point number FP _ a11 of the first to-be-processed sub-Data _ A1 is 1.0, and is located in the numerical value interval 0.000976563-8.0. According to the above-described formula ten and formula eleven, the first value FP _ a11F1 and the second value FP _ a11F2 of the floating-point number FP _ a11 can be determined. The decimal number corresponding to the first value FP _ a11F1 may be 1024 and the decimal number corresponding to the second value FP _ a11F2 may be 0.000976563.

The decimal number corresponding to the floating point number FP _ B11 of the second to-be-processed sub-Data Data _ B1 is 0.004, and is located in a numerical value interval 0.001953125-16. According to the above formula ten and formula eleven, the first value FP _ B11F1 and the second value FP _ B11F2 of the floating point number FP _ B11 can be determined. The first value FP _ B11F1 may correspond to a decimal number of 2.048 and the second value FP _ B11F2 may correspond to a decimal number of 0.001953125.

Multiplying the first value of the floating point number FP _ a11, the second value of the floating point number FP _ a11, the first value of the floating point number FP _ B11, and the second value of the floating point number FP _ B11 to obtain an absolute value FP _ AB11v of the output floating point number, which can be implemented by the following formula:

FP _ AB11v _10=1024 × 2.048 × 0.000976563 × 0.001953125=0.004000002 (thirteen formula)

The decimal FP _ AB11v _10 corresponding to FP _ AB11v may be 0.004000002.

By the embodiment of the disclosure, the calculation efficiency of the processing device can be effectively improved, and meanwhile, the calculation accuracy of the processing device can be kept at a higher level.

It can be understood that the calculation resources required for directly performing various operations between floating point numbers are high, and the calculation resources can be significantly reduced by converting the floating point numbers into the first value and the second value and then performing the operations. For example, taking floating-point number multiplication as an example, the floating-point number FP _ a11 and the floating-point number FP _ B11 are stored in an off-chip storage unit in an encoded form, and the multiplication between the two consumes a large amount of computing resources. And the operation is carried out by using the first value and the second value of the two floating point numbers, so that the operation resource can be remarkably reduced. The second value of the floating point number FP _ a11 is multiplied by the second value of the floating point number FP _ B11 (multiplication of binary number corresponding to 1024 and binary number corresponding to 2.048), and the simple shift operation is performed by the shift register corresponding to the processing unit.

It can be understood that, the above is to divide the first to-be-processed data into K first to-be-processed sub-data, and to divide the second to-be-processed data into K second to-be-processed sub-data. The present disclosure is not limited thereto, and in the embodiments of the present disclosure, the number of the to-be-processed sub-data divided according to different to-be-processed data may be different, which will be described below.

In some embodiments, the acquisition unit is configured to acquire data to be processed. For example, the Data to be processed may include first Data to be processed Data _ C and second Data to be processed Data _ D. The first Data _ C to be processed may be an M × J matrix. The second Data to be processed Data _ D may be a J × N matrix. M may be an integer greater than 1, J may be an integer greater than 1, and N may be an integer greater than 1.

In some embodiments, the dividing unit is configured to divide the data to be processed into a plurality of sub-data to be processed. The pending child data may include T floating point numbers. For example, T may be an integer greater than or equal to 1. For another example, the first Data to be processed Data _ C may be divided into a plurality of first sub-Data to be processed. Each first sub-data to be processed may include T floating-point numbers. The second to-be-processed data may also be divided into a plurality of second to-be-processed sub data, where each of the second to-be-processed sub data includes T floating point numbers. For another example, T may be smaller than M, smaller than J, or smaller than N. It is understood that T and M, J and N may have other relationships as well, and the present disclosure is not limited thereto.

In some embodiments, the quantization unit is configured to: determining at least one numerical value interval according to an extreme value of a plurality of floating point numbers and an exponent number of the floating point number in the subdata to be processed; and quantizing the at least one floating point number respectively according to the numerical value interval of the at least one floating point number to obtain quantized data. The quantized data includes a first value and a second value of the floating point number. For example, in the case where T is smaller than M, the first to-be-processed sub Data _ C1 may be from the first row of the first to-be-processed Data _ C. The maximum value Max _ C1 of the first to-be-processed sub Data _ C1 may be determined. The T floating point numbers in the first to-be-processed sub data may be quantized according to the maximum value Max _ C1, so as to obtain quantized data Q _ C1. The quantized Data Q _ C1 includes a first value and a second value of each floating point number in the first to-be-processed sub Data _ C1. For another example, in the case where T is less than J, the second to-be-processed sub Data _ D1 may be from the first column of the second to-be-processed Data _ D. A maximum value Max _ D1 of the second to-be-processed sub Data _ D1 may be determined. The T floating point numbers in the second to-be-processed sub data may be quantized according to the maximum value Max _ D1, so as to obtain quantized data Q _ D1. The quantized Data Q _ D1 includes a first value and a second value of each floating point number in the second to-be-processed sub Data _ D1.

In some embodiments, the processing unit is configured to perform an arithmetic operation using the first value and the second value of the floating point number in the quantized data, and obtain a processing result. For example, the processing unit may multiply the quantized data of the plurality of first sub-data to be processed and the quantized data of the plurality of second sub-data to be processed. In this operation process, the quantized data of the first sub-data to be processed and the quantized data of the second sub-data to be processed may be multiplied. For another example, the processing result may be an M × N matrix.

In some embodiments, the output unit is configured to output the processing result. For example, the M × N matrix may be output.

Fig. 4 is a flow diagram of a data processing method according to one embodiment of the present disclosure.

As shown in fig. 4, the method 400 includes operations S410 to S450.

It is to be appreciated that the method 400 may be applied to a data processing apparatus.

In operation S410, data to be processed is acquired. For example, the data to be processed includes a plurality of floating point numbers. The exponent bits of the floating point number are at least two.

In operation S420, data to be processed is divided into a plurality of sub data to be processed. For example, the sub-data to be processed includes at least one floating point number.

In operation S430, at least one numerical value interval is determined according to an extremum value of at least one floating point number and an exponent value of the floating point number in the data to be processed.

In operation S440, at least one floating point number is quantized according to the numerical value interval in which the floating point number is located, so as to obtain quantized data. For example, the quantized data comprises a first value and a second value of a floating point number.

In operation S450, an arithmetic process is performed using the first value and the second value of the floating point number in the quantized data, resulting in a processed result.

In operation S460, a processing result is output.

In the disclosed embodiment, the method 400 may be implemented with the processing device 200.

For example, operation S410 may be performed by the acquisition unit 210.

For example, operation S420 may be performed by the dividing unit 220.

For example, operations S430 and S440 may be performed by the quantization unit 240.

For example, operation S450 may be performed by the processing unit 240.

For example, operation S460 may be performed using the output unit 250.

In some embodiments, dividing the data to be processed into the plurality of sub-data to be processed comprises: and determining the number of floating point numbers in the sub data to be processed according to the data distribution information of the floating point numbers in the data to be processed. And dividing the data to be processed into a plurality of sub data to be processed according to the number of floating point numbers in the sub data to be processed. For example, the number of floating point numbers in the sub data to be processed may be determined by the first determining module of the dividing unit 220 according to data distribution information of a plurality of floating point numbers in the data to be processed. For another example, the dividing model of the dividing unit 220 may be utilized to divide the data to be processed into a plurality of sub-data to be processed according to the number of floating point numbers in the sub-data to be processed

In some embodiments, determining the number of floating point numbers in the sub-data to be processed includes at least one of: and in response to the fact that the data distribution information indicates that the plurality of floating point numbers in the to-be-processed data are uniformly distributed, determining the number of the floating point numbers in the to-be-processed sub data as a first preset parameter value. And determining the number of the floating point numbers in the sub-data to be processed as a second preset parameter value in response to the fact that the data distribution information indicates that the floating point numbers in the data to be processed are unevenly distributed. For example, the first preset parameter value is greater than the second preset parameter value. For example, the correlation operation may be performed using the first determination model of the division unit 220.

In some embodiments, determining the at least one numerical interval according to an extremum value of the at least one floating point number and an exponent value of the floating point number in the sub-data to be processed includes: and determining the interval number of the numerical value interval according to the exponent number of the floating point number. And determining at least one numerical value interval according to the extreme value and the interval number in at least one floating point number in the data to be processed.

In some embodiments, quantizing each of the at least one floating point number according to a numerical interval in which the floating point number is located, and obtaining quantized data includes: and quantizing the floating point number according to the numerical value interval of the floating point number to obtain quantized data. In the embodiment of the present disclosure, the number of intervals of the numerical value interval may be determined according to the exponent number of the floating point number using the second determination module of the quantization unit 230. The third determining module of the quantizing unit 230 may be utilized to determine at least one numerical value interval according to an extreme value and an interval number in at least one floating point number in the sub-data to be processed. In this embodiment of the present disclosure, the floating point number may be quantized by using a quantization module of the quantization unit 230 according to the numerical value interval where the floating point number is located, so as to obtain the first value and the second value of the floating point number.

In some embodiments, determining the at least one numerical interval according to the extremum value of the at least one floating point number in the sub-data to be processed and the number of intervals comprises: and determining at least one data threshold according to the first preset value, the extreme value and the number of intervals. At least one value interval is determined based on at least one data threshold. For example, the correlation operation may be performed using the third determination module of the quantization unit 230.

In some embodiments, the number of intervals is I, the at least one data threshold is I data thresholds, I being an integer greater than 1.

In some embodiments, determining the at least one data threshold based on the first preset value and the extremum comprises: the extreme value is determined as the 1 st data threshold. And determining the (i + 1) th data threshold according to the ith data threshold and the first preset value. For example, I is an integer greater than or equal to 1, and I is an integer less than or equal to I. For example, the correlation operation may be performed using the second determination module of the quantization unit 230.

In some embodiments, determining at least one interval of values based on at least one data threshold comprises: and determining an ith numerical interval according to the ith data threshold and the (i + 1) th data threshold. For example, the correlation operation may be performed using the third determination module of the quantization unit 230.

In some embodiments, quantizing the floating point number according to the numerical range in which the floating point number is located, and obtaining the first value and the second value of the floating point number includes: and obtaining a first value of the floating point number according to the target data threshold value and the first preset value. And obtaining a second value of the floating point number according to the first preset value, the floating point number and the target data threshold value. For example, the target data threshold is the larger of the two data thresholds associated with the numerical interval in which the floating point number is located. For example, the related operations may be performed using a quantization module of the quantization unit 230.

In some embodiments, the quantized data comprises function data associated with the target processing function and the first and second values of the target floating point number associated with the target processing function.

In some embodiments, performing the arithmetic processing using the first value and the second value of the floating point number in the quantized data, and obtaining the processing result includes: and reading the target processing function and the target floating point number related to the target processing function. And processing the first value and the second value of the target floating point number by using the target processing function to obtain a processing result. For example, a target processing function and a target floating point number associated with the target processing function may be read using a read module of processing unit 240. For example, the processing module of the processing unit 240 may be utilized to process the first and second values of the target floating-point number using the target processing function to obtain a processing result.

In some embodiments, processing the first and second values of the target floating-point number with the target processing function to obtain a processed result comprises: and determining a target sign bit according to the sign bit of the target floating point number. And processing the first value and the second value of the target floating point number by using the target processing function to obtain the absolute value of the output floating point number. And obtaining the output floating point number according to the absolute value of the output floating point number and the target sign bit. And obtaining a processing result according to the output floating point number. For example, the associated operations may be performed by processing modules of processing unit 230.

In some embodiments, the data to be processed includes first data to be processed and second data to be processed, and the plurality of sub-data to be processed includes: a plurality of first to-be-processed sub-data from the first to-be-processed data and a plurality of second to-be-processed sub-data from the second to-be-processed data, the target floating point number including: a first target floating point number from the first to-be-processed sub-data and a second target floating point number from the second to-be-processed sub-data.

In some embodiments, processing the first value and the second value of the target floating point number with the target processing function to obtain the absolute value of the output floating point number comprises: and sequentially multiplying the first values of the at least two target floating point numbers and the second values of the at least two target floating point numbers to obtain the absolute value of the output floating point number. For example, the relevant operations may be performed by processing modules of processing unit 240.

In the technical scheme of the disclosure, the collection, storage, use, processing, transmission, provision, disclosure and other processing of the personal information of the related user are all in accordance with the regulations of related laws and regulations and do not violate the good customs of the public order.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to embodiments of the present disclosure.

FIG. 5 illustrates a schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 5, the apparatus 500 comprises a computing unit 501 which may perform various appropriate actions and processes in accordance with a computer program stored in a Read Only Memory (ROM) 502 or a computer program loaded from a storage unit 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The calculation unit 501, the ROM 502, and the RAM 503 are connected to each other by a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.

A number of components in the device 500 are connected to the I/O interface 505, including: an input unit 506 such as a keyboard, a mouse, or the like; an output unit 507 such as various types of displays, speakers, and the like; a storage unit 508, such as a magnetic disk, optical disk, or the like; and a communication unit 509 such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The computing unit 501 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit, a graphics processor, various specialized Artificial Intelligence (AI) computing chips, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and the like. For example, various dedicated artificial intelligence computing chips may include the processing device 200 described above.

The calculation unit 501 executes the respective methods and processes described above, such as the data processing method. For example, in some embodiments the data processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 500 via ROM 502 and/or communications unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the data processing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field programmable gate arrays, application specific integrated circuits, application Specific Standard Products (ASSPs), system On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) display or an LCD (liquid crystal display)) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel or sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims (27)

1. A data processing apparatus comprising:

the processing device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is configured to acquire data to be processed, the data to be processed comprises a plurality of floating point numbers, and exponent bits of the floating point numbers are at least two;

the dividing unit is configured to divide the data to be processed into a plurality of sub data to be processed, wherein the sub data to be processed comprises at least one floating point number;

a quantization unit configured to: determining at least one numerical value interval according to an extreme value in at least one floating point number and an exponent bit of the floating point number in the sub-data to be processed; quantizing at least one floating point number respectively according to a numerical value interval in which the floating point number is located to obtain quantized data, wherein the quantized data comprises a first value and a second value of the floating point number;

the processing unit is configured to perform operation processing by using the first value and the second value of the floating point number in the quantized data to obtain a processing result; and

an output unit configured to output the processing result.

2. The apparatus of claim 1, wherein the dividing unit comprises:

the first determining module is configured to determine the number of the floating point numbers in the to-be-processed sub data according to data distribution information of a plurality of the floating point numbers in the to-be-processed data;

and the dividing module is configured to divide the to-be-processed data into a plurality of to-be-processed subdata according to the number of the floating point numbers in the to-be-processed subdata.

3. The apparatus of claim 2, wherein the first determining module is further configured to:

in response to determining that the data distribution information indicates that the floating point numbers in the to-be-processed data are uniformly distributed, determining the number of the floating point numbers in the to-be-processed subdata to be a first preset parameter value;

and in response to determining that the data distribution information indicates that the floating point numbers in the to-be-processed data are unevenly distributed, determining that the number of the floating point numbers in the to-be-processed sub-data is a second preset parameter value, wherein the first preset parameter value is larger than the second preset parameter value.

4. The apparatus of claim 1, further comprising:

a storage unit coupled to the quantization unit and the processing unit for storing the quantized data from the quantization unit.

5. The apparatus of claim 4, wherein the quantization unit comprises:

a second determining module configured to determine an interval number of a numerical interval according to the exponent bit of the floating point number;

a third determining module, configured to determine at least one numerical value interval according to an extreme value in at least one floating point number in the to-be-processed sub data and the number of intervals;

the quantization module is configured to quantize the floating point number according to the numerical value interval of the floating point number to obtain the first value and the second value of the floating point number; and

a writing module configured to write the quantized data into the storage unit.

6. The apparatus of claim 5, wherein the third determination module is further configured to:

determining at least one data threshold according to a first preset value, the extreme value and the interval number; and

at least one of the value intervals is determined based on at least one of the data thresholds.

7. The apparatus of claim 6, wherein the number of intervals is I, the at least one data threshold is I +1 data thresholds, I is an integer greater than 1,

the third determination module is further configured to:

determining the extreme value as a1 st data threshold value; and

determining the (i + 1) th data threshold according to the ith data threshold and the first preset value,

wherein I is an integer greater than or equal to 1, and I is an integer less than or equal to I.

8. The apparatus of claim 7, wherein the third determination module is further configured to:

and determining an ith numerical interval according to the ith data threshold and the (i + 1) th data threshold.

9. The apparatus of claim 6, wherein the quantization module is configured to:

obtaining the first value of the floating point number according to a target data threshold value and the first preset value, wherein the target data threshold value is a larger value between two data threshold values related to the numerical value interval where the floating point number is located; and

and obtaining the second value of the floating point number according to the first preset value, the floating point number and the target data threshold value.

10. The apparatus of claim 4, wherein the quantized data comprises: function data related to a target processing function and first and second values of a target floating point number related to the target processing function; the processing unit includes:

a read module configured to read a target processing function and a target floating point number associated with the target processing function from the storage unit; and

and the processing module is configured to process the first value and the second value of the target floating point number by using the target processing function to obtain the processing result.

11. The apparatus of claim 10, wherein the processing module is further configured to:

determining a target sign bit according to the sign bit of the target floating point number;

processing the first value and the second value of the target floating point number by using the target processing function to obtain an absolute value of an output floating point number;

obtaining an output floating point number according to the absolute value of the output floating point number and the target sign bit; and

and obtaining the processing result according to the output floating point number.

12. The apparatus of claim 11, wherein the data to be processed comprises first data to be processed and second data to be processed, and the plurality of sub-data to be processed comprises: a plurality of first to-be-processed sub-data from the first to-be-processed data, and a plurality of second to-be-processed sub-data from the second to-be-processed data, the target floating point number including: a first target floating point number from the first to-be-processed sub-data and a second target floating point number from the second to-be-processed sub-data;

the processing module is further configured to:

and multiplying the first value and the second value of the first target floating point number and the first value and the second value of the second target floating point number in sequence to obtain the absolute value of the output floating point number.

13. A data processing method is applied to a data processing device, and the method comprises the following steps:

acquiring data to be processed, wherein the data to be processed comprises a plurality of floating point numbers, and the exponent number of the floating point number is at least two;

dividing the data to be processed into a plurality of sub data to be processed, wherein the sub data to be processed comprises at least one floating point number;

determining at least one numerical value interval according to an extreme value in at least one floating point number and an exponent bit of the floating point number in the sub-data to be processed;

quantizing at least one floating point number respectively according to a numerical value interval in which the floating point number is located to obtain quantized data, wherein the quantized data comprises a first value and a second value of the floating point number;

performing operation processing by using the first value and the second value of the floating point number in the quantized data to obtain a processing result; and

and outputting the processing result.

14. The method of claim 13, wherein the dividing the data to be processed into a plurality of sub-data to be processed comprises:

determining the number of the floating point numbers in the to-be-processed subdata according to data distribution information of the floating point numbers in the to-be-processed data;

and dividing the data to be processed into a plurality of sub data to be processed according to the number of the floating point numbers in the sub data to be processed.

15. The method of claim 14, wherein the determining the number of floating point numbers in the to-be-processed child data comprises at least one of:

in response to the fact that the data distribution information indicates that the floating point numbers in the to-be-processed data are uniformly distributed, determining the number of the floating point numbers in the to-be-processed sub-data to be a first preset parameter value;

in response to determining that the data distribution information indicates that the floating point numbers in the to-be-processed data are unevenly distributed, determining the number of the floating point numbers in the to-be-processed sub-data to be a second preset parameter value;

wherein the first preset parameter value is greater than the second preset parameter value.

16. The method of claim 13, wherein the determining at least one numerical interval based on an extremum value of the at least one floating point number and an exponent value of the floating point number in the to-be-processed child data comprises:

determining the interval number of the numerical value interval according to the exponent number of the floating point number; and

determining at least one numerical value interval according to an extreme value in at least one floating point number in the to-be-processed subdata and the interval number;

the quantizing the at least one floating point number according to the numerical value interval in which the at least one floating point number is located, to obtain quantized data includes:

and quantizing the floating point number according to the numerical value interval of the floating point number to obtain the first value and the second value of the floating point number.

17. The method of claim 16, wherein the determining at least one of the numerical intervals based on the extremum in the at least one of the floating point numbers in the to-be-processed child data and the number of intervals comprises:

determining at least one data threshold according to a first preset value, the extreme value and the interval number; and

determining at least one of the value intervals based on at least one of the data thresholds.

18. The method of claim 17, wherein the number of intervals is I, the at least one data threshold is I +1 data thresholds, I is an integer greater than 1,

determining at least one data threshold according to the first preset value and the extreme value comprises:

determining the extreme value as a1 st data threshold value; and

determining the (i + 1) th data threshold according to the ith data threshold and the first preset value,

wherein I is an integer greater than or equal to 1, and I is an integer less than or equal to I.

19. The method of claim 18, wherein said at least one data threshold, determining at least one of said intervals of values comprises:

and determining an ith numerical interval according to the ith data threshold and the (i + 1) th data threshold.

20. The method of claim 17, wherein the quantizing the floating point number according to the numerical range in which the floating point number is located, resulting in the first and second values of the floating point number comprises:

obtaining the first value of the floating point number according to a target data threshold value and the first preset value, wherein the target data threshold value is a larger value between two data threshold values related to the numerical value interval where the floating point number is located; and

and obtaining the second value of the floating point number according to the first preset value, the floating point number and the target data threshold value.

21. The method of claim 17, wherein the quantizing data comprises: a first value and a second value of function data associated with a target processing function and a target floating point number associated with the target processing function;

the performing operation processing by using the first value and the second value of the floating point number in the quantized data to obtain a processing result includes:

reading a target processing function and a target floating point number related to the target processing function; and

and processing the first value and the second value of the target floating point number by using the target processing function to obtain the processing result.

22. The method of claim 21, wherein said processing the first and second values of the target floating point number with the target processing function to obtain the processed result comprises:

determining a target sign bit according to the sign bit of the target floating point number;

processing the first value and the second value of the target floating point number by using the target processing function to obtain an absolute value of an output floating point number;

obtaining an output floating point number according to the absolute value of the output floating point number and the target sign bit; and

and obtaining the processing result according to the output floating point number.

23. The method of claim 22, wherein the data to be processed comprises first data to be processed and second data to be processed, and the plurality of sub-data to be processed comprises: a plurality of first to-be-processed sub-data from the first to-be-processed data, and a plurality of second to-be-processed sub-data from the second to-be-processed data, the target floating point number including: a first target floating point number from the first to-be-processed sub-data and a second target floating point number from the second to-be-processed sub-data;

the processing the first value and the second value of the target floating point number by using the target processing function to obtain the absolute value of the output floating point number includes:

and multiplying the first value and the second value of the first target floating point number and the first value and the second value of the second target floating point number in sequence to obtain the absolute value of the output floating point number.

24. An electronic device comprising at least one data processing apparatus as claimed in any one of claims 1 to 12.

25. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 13 to 23.

26. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 13 to 23.

27. A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 13 to 23.

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