CN115937157A

CN115937157A - Method and device for identifying test chip in wafer, electronic equipment and storage medium

Info

Publication number: CN115937157A
Application number: CN202211619915.1A
Authority: CN
Inventors: 熊俊剑
Original assignee: Hangzhou Fuxin Semiconductor Co Ltd
Current assignee: Hangzhou Fuxin Semiconductor Co Ltd
Priority date: 2022-12-16
Filing date: 2022-12-16
Publication date: 2023-04-07

Abstract

The application discloses a method for identifying a test chip in a wafer, a device for identifying a test chip in a wafer, an electronic device and a storage medium, wherein the method comprises the following steps: obtaining a scanning image, wherein the scanning image comprises a test chip of a wafer and a functional chip of the wafer; based on the attribute of an exposure unit of the wafer, carrying out area division on the scanned image to obtain a plurality of image areas; determining the position of the test chip in the scanned image according to the marking information of the exposure unit and the plurality of image areas; wherein the marking information characterizes a position of the test chip in the exposure unit. By using the method and the device, the problem that the test chip is scanned out as the defect of the wafer can be avoided.

Description

Method and device for identifying test chip in wafer, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for identifying a test chip in a wafer, an electronic device, and a storage medium.

Background

In the semiconductor field, a test chip is a chip provided on a wafer for performing electrical and functional tests on the wafer. In the current defect scanning scheme, a wafer including a test chip is subjected to image scanning, and a defect of the wafer is identified based on analysis of the scanned image. Since the scan image includes the test chip, the test chip is scanned as a defect of the wafer in the defect recognition. How to avoid the test chip being scanned out as the defect of the wafer in the defect scanning process becomes a problem to be solved urgently.

Disclosure of Invention

The application provides a method, a device, an electronic device and a storage medium for identifying a test chip in a wafer, which are used for at least solving the technical problems in the prior art.

According to a first aspect of the present application, there is provided a method for identifying test chips in a wafer, comprising:

obtaining a scanning image, wherein the scanning image comprises a test chip of a wafer and a functional chip of the wafer;

based on the attribute of an exposure unit of the wafer, carrying out area division on the scanned image to obtain a plurality of image areas;

determining the position of the test chip in the scanned image according to the marking information of the exposure unit and the plurality of image areas; wherein the marking information characterizes a position of the test chip in the exposure unit.

In one embodiment, the method further comprises:

and obtaining a target image based on the positions of the scanning image and the test chip in the scanning image, wherein the target image is an image capable of distinguishing the test chip and the functional chip of the wafer.

In an implementation manner, the determining the position of the test chip in the scanned image according to the labeling information of the exposure unit and the plurality of image areas includes:

determining the position of the test chip in each image area according to the marking information of the exposure unit;

and determining the position of the test chip in the scanned image based on the position of the test chip in each image area and the position of each image area in the scanned image.

In one embodiment, the size of each image area is the same as the size of the exposure unit;

the determining the position of the test chip in each image area according to the labeling information of the exposure unit includes:

according to the marking information of the exposure unit, determining a position corresponding to the position of the test chip in the exposure unit in each image area;

and taking the position corresponding to the position of the test chip in the exposure unit determined in each image area as the position of the test chip in each image area.

In one embodiment, the obtaining the target image based on the scanned image and the position of the test chip in the scanned image includes:

in the scanned image, different identification information is adopted to respectively identify the position of the test chip and the position of the functional chip;

and taking the scanned image marked with the different identification information as a target image.

In one possible embodiment, the target image is used for defect scanning of the wafer.

In one embodiment, the obtaining the scan image includes:

constructing a scanning image based on the initial scanning result of the wafer; the preliminary scanning result comprises positions of a test chip, a functional chip and each chip in the wafer.

According to a second aspect of the present application, there is provided an apparatus for identifying test chips in a wafer, comprising:

the device comprises a first obtaining unit, a second obtaining unit and a third obtaining unit, wherein the first obtaining unit is used for obtaining a scanning image, and the scanning image comprises a test chip of a wafer and a functional chip of the wafer;

the dividing unit is used for carrying out area division on the scanning image based on the attribute of the exposure unit of the wafer to obtain a plurality of image areas;

the determining unit is used for determining the position of the test chip in the scanning image according to the marking information of the exposure unit and the image areas; wherein the marking information characterizes a position of the test chip in the exposure unit.

According to a third aspect of the present application, there is provided an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein, the first and the second end of the pipe are connected with each other,

the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method described herein.

According to a fourth aspect of the present application, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method described herein.

By using the technical scheme, the scheme of identifying the positions of the test chips in the scanning image according to the marking information of the exposure unit and the plurality of image areas divided by the scanning image can avoid the problem that the test chips are scanned as the defects of the wafer by not scanning the positions of the test chips identified in the wafer when the wafer is scanned with the defects.

It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present application, nor are they intended to limit the scope of the present application. Other features of the present application will become apparent from the following description.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

FIG. 1 is a first flowchart illustrating an implementation of a method for identifying a test chip in a wafer according to an embodiment of the present disclosure;

FIG. 2 is a schematic view showing an exposure unit in the embodiment of the present application;

FIG. 3 is a schematic diagram of an exposure unit with a coordinate system according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating a second implementation of the method for identifying a test chip in a wafer according to the embodiment of the present application;

FIG. 5 shows a first application diagram in the embodiment of the present application;

FIG. 6 shows a second example of application in an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating an exemplary structure of a device for identifying test chips in a wafer according to an embodiment of the present disclosure;

fig. 8 shows a schematic structural diagram of the electronic device in the embodiment of the present application.

Detailed Description

In order to make the objects, features and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without making creative efforts fall within the protection scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

In the following description, references to the terms "first", "second", and the like, are only to distinguish similar objects and do not denote a particular order, but rather the terms "first", "second", and the like may be used interchangeably with the order specified, where permissible, to enable embodiments of the present application described herein to be practiced otherwise than as specifically illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

It should be understood that, in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In the technical scheme of the application, the scan image is an image of a functional chip including both a test chip and a wafer, and according to the marking information of the exposure unit and the plurality of image areas divided by the scan image, the position of the test chip in the scan image can be identified, that is, the area where the test chip is located in the scan image is identified. The identification of the position of the test chip can avoid the problem that the test chip is scanned out as the defect of the wafer by not scanning the position of the identified test chip in the wafer when the wafer is scanned for the defect. The problem that the defects need to be processed due to the fact that the test chip is scanned out as the defects can be effectively solved, processing links are saved, and unnecessary processing procedures are avoided.

The method for identifying the test chips in the wafer is applied to a device for identifying the test chips in the wafer (referred to as an identification device for short). The recognition device can be used as a stand-alone device, and can also be integrated into a wafer defect scanning machine (simply referred to as a scanning machine) for use. The scanner is a device that can identify defects in the wafer.

Fig. 1 is a first flowchart illustrating an implementation of a method for identifying a test chip in a wafer according to an embodiment of the present disclosure. As shown in fig. 1, the method includes:

s101: obtaining a scanning image, wherein the scanning image comprises a test chip of a wafer and a functional chip of the wafer;

in this step, the wafer includes a functional chip manufactured in a chip manufacturing process and a test chip for performing electrical and functional tests on the functional chip. The function or function of the functional chip can be designed or manufactured according to actual requirements. The number of test chips and functional chips in a wafer is usually multiple.

In this step, a scan image including the test chip and the functional chip may be obtained by scanning the wafer. Or, the other equipment or device scans the wafer to obtain a scanned image, and sends the scanned image to the identification device. The recognition device obtains a scanned image by receiving the scanned image transmitted by other apparatuses or devices.

In the step, a scanning image can be constructed based on the initial scanning result of the wafer; the preliminary scanning result comprises a test chip and a functional chip in the wafer and the position of each chip in the wafer. It is understood that the functional chips are chips fabricated in a wafer by a chip fabrication process. The test chip is a chip provided in a wafer for electrical and functional tests of a manufactured functional chip. The chips in the wafer include both functional chips and test chips. The number of chips of each type scanned is typically multiple. Through the initial scanning of the wafer, two types of chips, namely functional chips and test chips, can be scanned, and the positions of the chips (the test chips and the functional chips) in the wafer can also be scanned.

In the foregoing solution, the preliminary scanning result is obtained by performing a preliminary scanning on the wafer. In implementation, the image may be constructed according to the positions of the chips in the preliminary scanning result. And taking the constructed image as a scanning image. The positions of the chips in the scanned image can be consistent with the positions of the chips in the preliminary scanning result. In some embodiments, the position of each chip in the scanned image, the size of each chip, and the number of chips in the wafer may be consistent with the position of each chip in the preliminary scan result, the size of each chip, and the number of chips in the wafer.

S102: based on the attribute of an exposure unit of the wafer, carrying out area division on the scanned image to obtain a plurality of image areas;

the exposure unit refers to a shot used in an exposure link in a chip manufacturing process. The specification or size of the exposure unit needs to be specified before exposure. Typically, the exposure unit is a shot of M rows by N columns gauge. That is, the shot size is the size of M rows by N columns of Die (grains). The exposure unit comprises M rows and N columns of exposure subunits, and each exposure subunit has the same size as Die.

As shown in fig. 2, the exposure unit is 3 rows by 2 columns (M =3, n = 2). In one exposure unit of 3 rows by 2 columns, there are M × N =6 exposure subunits for subunit 11, subunit 12, subunit 21, subunit 22, subunit 21, and subunit 32. Each exposure subunit is the same size as a single Die of the wafer.

Fig. 2 shows a specific example of the exposure unit. Any reasonable size or dimension is within the scope of the present application.

In this step, the attribute of the exposure unit includes the specification or size of the exposure unit. In practice, the scan image is divided into a plurality of image areas according to the specification or size of the exposure unit specified in advance. For example, the scanned image is divided into L image areas, and the size of each image area is the same as the size of the exposure unit. Wherein L is a positive integer greater than or equal to 2.

S103: determining the position of the test chip in the scanned image according to the marking information of the exposure unit and the plurality of image areas; wherein the marking information characterizes a position of the test chip in the exposure unit.

In this step, the position of the test chip in the exposure unit is marked in advance to form marking information.

In implementation, the position of the test chip in the exposure unit can be marked by two-dimensional coordinates (x, y). The coordinate system of the two-dimensional coordinates is shown as an XOY coordinate system in fig. 3. In a rough labeling manner, the position of which exposure subunit or subunits the test chip is located in can be identified as the position of the test chip in the exposure unit. For example, the test chip is in the area where the exposure subunit 11 is located, and the position identifier (x =1, y = 1) of the exposure subunit 11 in the exposure unit is used as the marking information. The test chip is located in the area where the exposing subunit 32 is located, and the position identification (x =3, y = 2) of the exposing subunit 32 in the exposing unit is used as the marking information.

In the application, a fine labeling mode is also provided. And taking the actual position of the test chip in the XOY coordinate system as marking information. Based on this, the area of the test chip represented by the marking information in the exposure unit may be the position of a certain subunit in the exposure unit, and may also be the actual position of the test chip in the XOY coordinate system as shown in fig. 3.

In practical applications, the number of test chips in the exposure unit may not only be one, but also be two or more. Thus, the position of each test chip in the exposure unit can be marked in advance by adopting one of the two manners. And taking the two-dimensional coordinates marked for each test chip as marking information of the exposure unit.

In this step, in implementation, the position of the test chip in each image area can be determined by referring to the label information of the exposure unit, so as to obtain the position of the test chip in the scanned image.

In S101 to S103, the position of the test chip in the scan image can be recognized based on the label information of the exposure unit and the plurality of image areas into which the scan image is divided. The identification of the position of the test chip can avoid the problem that the test chip is scanned out as the defect of the wafer by not scanning the position of the identified test chip in the wafer when the wafer is scanned for the defect. The problem that the defects need to be processed due to the fact that the test chip is scanned out as the defects can be effectively solved, processing links are saved, and unnecessary processing procedures are avoided.

In the related art, when the test chip is scanned as a defect, the test chip scanned as a defect needs to be manually removed from the wafer. By the technical scheme, automatic identification of the test chip in the scanned image is achieved, so that the position of the test chip in the wafer can be identified, and the problems of increased workload and the like caused by manual removal can be avoided.

In short, the technical scheme of the application can identify the position of the test chip in the scanning image so as to avoid the problem that the test chip is scanned out as the defect of the wafer.

In some embodiments, the aforementioned scheme of determining the position of the test chip in the scanned image according to the labeling information of the exposure unit and the plurality of image areas can be implemented in the manner shown in fig. 4.

S401: and determining the position of the test chip in each image area according to the marking information of the exposure unit.

It is understood that, since the scanned image is divided into regions, each of the divided regions is divided according to the size or specification of the exposure unit. The size of each divided image area and the size of the exposure unit are the same in terms of size or specification. Therefore, in implementation, according to the marking information of the exposure unit, the position corresponding to the position of the test chip in the exposure unit is determined in each image area. And taking the position corresponding to the position of the test chip in the exposure unit determined in each image area as the position of the test chip in each image area.

Illustratively, taking any one of L areas into which the scan image is divided as an example, the size of the image area is the same as the size of the exposure unit, and if the label information of the exposure unit indicates that the position of the test chip in the exposure unit is (x =2,y = 1), in the image area having the same size as the exposure unit, the position corresponding to the position of the test chip in the exposure unit is the position of the coordinate (x =2,y = 1) in the image area. That is, in the case where the divided image areas are the same size as the exposure unit, the position of the test chip in the image area and the position in the exposure unit are identical.

Therefore, the position of the test chip in each image area can be accurately positioned. Therefore, the position of the test chip in the scanned image can be accurately identified.

S402: and determining the position of the test chip in the scanning image based on the position of the test chip in each image area and the position of each image area in the scanning image.

When the scanned image can be divided, the positions of the divided image areas in the scanned image can be recorded. In this step, the positions of the recorded image areas in the scanned image are read. When the position of each image area in the scanned image and the position of the test chip in each image area are known, the position of the test chip in the scanned image is easily known.

The solutions shown in S401 to S402 determine the position of the test chip in each image area according to the label information of the exposure unit, so as to ensure the accuracy of determining the test chip in each image area. Based on the position of the test chip in each image area and the position of each image area in the scanned image, the accuracy of determining the position of the test chip in the scanned image can be ensured.

In the case where the position of the test chip in the scan image is identified by the above scheme, the position of the test chip in the scan image also needs to be used. For example, based on the position of the test chip in the scanning image, the defect scanning of the wafer is realized. Therefore, in practical application, under the condition that the position of the test chip in the scanning image is determined, the target image is obtained based on the scanning image and the position of the test chip in the scanning image, and the target image is an image which can distinguish the test chip and the functional chip of the wafer and can be used for carrying out defect scanning on the wafer.

It is understood that, since the scan image is an image of the test chips and the functional chips including the wafer, positions of the functional chips in the scan image except for the positions of the test chips can be regarded as positions of the functional chips in the scan image when the positions of the test chips in the scan image are known. That is, for the scanned image, the position of the functional chip in the scanned image is easily known by knowing the two types of chips including the functional chip and the test chip thereon and the position of the test chip in the scanned image. During implementation, a new image can be constructed based on the known two types of chips, the positions of the test chips in the scanned image and the positions of the functional chips in the scanned image, and the constructed new image can be regarded as a target image.

In some embodiments, the new image being built may be an image of the same size or an equal proportional size as the scanned image. And in the built new image, the types of the chips appearing in the new image are the same as the positions of the chips appearing in the scanned image. The position where the test chip appears in the new image is kept the same as the position where the test chip appears in the scanned image. The position where the functional chip appears in the new image is kept the same as the position where the functional chip appears in the scanned image.

Compared with the test chip and the functional chip which cannot be distinguished in the scanned image, in the constructed new image, namely the target image, the target image is constructed based on the known positions of the test chip and the functional chip, so that the test chip and the functional chip can be easily distinguished in the target image.

In the technical aspect, the test chip and the functional chip are easily distinguished in the target image. And in the scanned image, different identification information can be adopted to respectively identify the position of the test chip and the position of the functional chip. And the scanned image identified with the different identification information is taken as a target image.

Illustratively, two different kinds of digital information are employed as two different kinds of identifiers. For example, the number 1 indicates the location of the test chip, and the number 0 indicates the location of the functional chip. And identifying the position of the test chip in the scanned image by using the number 1. And identifying the position of the functional chip in the scanned image by adopting a number 0. The scanned image identified with the number 1 and the number 0 is taken as a target image.

As different digital information is marked in the target image and represents different types of chips and the like, the test chip and the functional chip can be easily distinguished in the target image.

In the foregoing, different identification information is adopted to respectively identify the position of the test chip and the position of the functional chip, and a scheme that the scan image identified with the different identification information is used as the target image can also be regarded as a scheme how to obtain the target image.

It can be understood that, since the positions of the test chips and the functional chips are identified in the target image, the target image can be used to scan the wafer for defects. During scanning, the position of the test chip can be avoided, and only the functional chip is subjected to defect scanning. Therefore, the problem that the test chip is scanned out as the defect of the wafer is avoided. The problem that the defects need to be processed due to the fact that the test chip is scanned out as the defects can be effectively solved, processing links are saved, and unnecessary processing procedures are avoided.

The following describes the present application in detail with reference to fig. 5 and 6, taking the identification device as an independent device as an example.

As shown in fig. 5, the defect scanner station performs (preliminary) scanning on the wafer to obtain a scan pattern. The scanning image is used as the original scanning image of the defect scanning machine. The original scan is scanned out a plurality of Die (dies) of the wafer. Each pane in fig. 5 may be considered a Die. Each Die corresponds to a chip. Generally, the types of chips in a wafer include functional chips (normal chips) and test chips. In this way, in the Die of the wafer, the chips corresponding to part of the Die are functional chips, and the chips corresponding to part of the Die are test chips. The defect scanner uses the position and size of each Die in the wafer corresponding to each Die in the original scan as the recording information. A text (TXT) file is generated according to the recording information. To distinguish the subsequent TXT file 2, the TXT file generated by the defect scanner is regarded as TXT file 1. The TXT file 1 records the number of chips in the original scan, the position of each chip in the wafer, and the size.

The information such as the number of chips, the position and the size of each chip in the wafer in the original scan image scanned by the defect scanner can be used as the preliminary scan result in the present application. The defect scanning machine sends the TXT file 1 to the identification device of the application.

As shown in fig. 6, the recognition device analyzes the information recorded in the TXT file 1, and constructs a scan image based on the result of analyzing the recorded information. In some embodiments, the identification device may construct a scan image according to the information recorded in the TXT file 1, where the scan image may be the same as the original scan image of the defect scanner in terms of attributes such as chip size, chip number, and chip positions. That is, the scanned image constructed by the identification device may be the same image as the original scanned image scanned by the defect scanner. It can be understood that, in the chip manufacturing process, the scanogram scanned by the defect scanner is a repetition of the images of the multiple exposure units. In this way, the scanned image constructed by the recognition device is also a repeat of the plurality of exposure unit images.

Assume that M =2 and N =3 of exposure units preset for the wafer. The recognition device divides the scanned image according to the size of the M rows and N columns of the exposure units to obtain a plurality of image areas of the scanned image. The size of each image area is the same as the size of the M rows by N columns of exposure units. The position of each image area in the scanned image is recorded.

When recording the position of each image area in the scanned image, the position of each image area can be recorded in the image coordinate system established for the scanned image. The origin of the image coordinate system may coincide with a point at the lower left corner of the scanned image shown in fig. 5, and a direction parallel to the scanned image from the origin is a positive direction of the X axis, and a direction perpendicular to the scanned image is a positive direction of the Y axis. The position of each image area in the image coordinate system is used as the position of each image coordinate system in the scanned image.

Taking the number of the test chips as an example, if the coordinates of the test chips in the exposure unit are (x =2, y = 1), the marking information marked for the exposure unit of the wafer may be information of the position of the test chip in the exposure unit with the coordinates of (x =2, y = 1). In each image area having the same size as the exposure unit, the position of the test chip in each image area corresponding to the position of the exposure unit, for example, the position of the test chip in each image area having coordinates (x =2, y = 1) is the position of the test chip in each image area. The recognition device thus achieves a precise positioning of the position of the test chip in the respective image region.

In the case where the position of each image area in the scanned image and the position of the test chip in each image area are known, the recognition device can easily locate the position of the test chip in the image coordinate system. The position of the test chip in the image coordinate system is the position of the test chip in the scanned image. Since the scan image is a repetition of a plurality of exposure unit images, the position of the test chip in the scan image is also a repetition of the position in units of exposure units. As shown in fig. 6, in blocks 1 and 2, the contents shown in blocks 1 and 2 are each a repetition of the exposure unit. Thus, the scanned image is considered to be L repetitions of the exposure unit. I.e. each image area is a repetition of an exposure unit. If M =2,n =3, the subunit in the 2 nd row and the 2 nd column in the exposure unit is the area where the test chip is located, the location where the test chip is located in the L image areas is the location where the 2 nd row and the 2 nd column in each image area are located. The position of the 2 nd row and 2 nd column of each image area in the image coordinate system is the position of the test chip in the scanned image. This enables the position of the test chip in the scanned image to be identified.

In the technical scheme of the application, when the position of the test chip in the scanned image is identified, the position of the test chip in the scanned image is identified by the identification device with a number 1, and the position of other chips (such as functional chips) except the position of the test chip in the scanned image is identified by a number 0. The scanned image identified with the number 1 and the number 0 is taken as a target image, as shown in fig. 6 in which each chip identification is performed with a number identification.

It is to be understood that in the target image, the chip identified as the number 0 is a functional chip. The chip identified as the number 1 is a test chip. Therefore, the functional chip and the test chip can be easily distinguished by adopting different identification information in the target image.

The recognition device generates a TXT file 2 in which information such as the size of each chip, the type of each chip, and the position of each chip in the target image is recorded. The identification device sends the TXT file 2 to the defect scanner.

The defect scanner identifies the types of the chips in the original scan according to the TXT file 1, for example, as shown in fig. 6, the number 0 is used as the identification of the functional chip, or as shown in fig. 5, the letter a is used as the identification of the functional chip. And taking the original scanning image subjected to the chip type identification as a new scanning image so as to facilitate defect scanning. When defect scanning is carried out according to the TXT file 1, the defect scanning machine does not carry out defect scanning on the test chip marked as 1 on the new scanning image, and only carries out defect scanning on the normal chip marked as 0 on the wafer. The problem that the test chip needs to be manually removed due to the fact that the test chip is scanned out as a defect can be effectively avoided, workload is saved, and unnecessary processing links are avoided.

Therefore, according to the technical scheme, the scanned image is constructed through the identification device; dividing the scanning image based on the attribute of the exposure unit of the wafer; and according to the marking information of the exposure unit and the plurality of image areas divided by the scanning image, the position of the test chip in the scanning image can be identified. The identification of the position of the test chip can avoid the problem of manual removal caused by the fact that the test chip is scanned as the defect of the wafer by not scanning the test chip identified in the wafer when the defect scanning machine scans the defect of the wafer.

The present application further provides an embodiment of an apparatus for identifying a test chip in a wafer, as shown in fig. 7, the apparatus includes:

a first obtaining unit 701, configured to obtain a scan image, where the scan image includes a test chip of a wafer and a functional chip of the wafer;

a dividing unit 702, configured to perform area division on the scanned image based on an attribute of an exposure unit of the wafer, so as to obtain a plurality of image areas;

a determining unit 703, configured to determine, according to the labeling information of the exposure unit and the multiple image areas, a position of the test chip in the scanned image; wherein the marking information characterizes a position of the test chip in the exposure unit.

In some embodiments, a second obtaining unit is further included for:

In some embodiments, the determining unit 703 is configured to:

In some embodiments, the size of each image area is the same as the size of the exposure unit; the determining unit 703 is configured to:

In some embodiments, the second obtaining unit is further configured to:

In some embodiments, the target image is used for defect scanning of the wafer.

In some embodiments, the first obtaining unit 701 is configured to:

constructing a scanning image based on the preliminary scanning result of the wafer; the initial scanning result comprises positions of a test chip, a functional chip and each chip in the wafer.

It should be noted that, in the apparatus for identifying a test chip in a wafer according to the embodiment of the present application, since the principle of solving the problem of the apparatus for identifying a test chip in a wafer is similar to the method for identifying a test chip in a wafer, the implementation process and the implementation principle of the apparatus for identifying a test chip in a wafer can be described by referring to the implementation process and the implementation principle of the method, and repeated details are not repeated.

According to an embodiment of the present application, an electronic device and a readable storage medium are also provided.

FIG. 8 shows a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.

As shown in fig. 8, the apparatus 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The calculation unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to bus 804.

A number of components in the device 800 are connected to the I/O interface 805, including: an input unit 806, such as a keyboard, a mouse, or the like; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, or the like; and a communication unit 809 such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

Computing unit 801 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and the like. The computing unit 801 performs the various methods and processes described above, such as the identify in-wafer test chip method. For example, in some embodiments, the identify in-wafer test chips method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and/or installed onto device 800 via ROM 802 and/or communications unit 809. When loaded into RAM 803 and executed by computing unit 801, a computer program may perform one or more of the steps of the method for identifying test chips in a wafer described above. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the identify in-wafer test chip method by any other suitable means (e.g., by way of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application specific labeling products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present disclosure may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for identifying test chips in a wafer, comprising:

2. The method of claim 1, further comprising:

3. The method according to claim 1 or 2, wherein the determining the position of the test chip in the scanned image according to the labeling information of the exposure unit and the plurality of image areas comprises:

4. A method according to claim 3, wherein the size of each image area is the same as the size of the exposure unit;

5. The method of claim 2, wherein obtaining the target image based on the scan image and the position of the test chip in the scan image comprises:

6. A method according to claim 2 or 5, wherein the target image is used for defect scanning of the wafer.

7. The method of claim 1, 2 or 5, wherein the obtaining a scan image comprises:

8. An apparatus for identifying test chips in a wafer, comprising:

the device comprises a first obtaining unit, a second obtaining unit and a control unit, wherein the first obtaining unit is used for obtaining a scanning image, and the scanning image comprises a test chip of a wafer and a functional chip of the wafer;

the dividing unit is used for carrying out area division on the scanned image based on the attribute of the exposure unit of the wafer to obtain a plurality of image areas;

the determining unit is used for determining the position of the test chip in the scanned image according to the marking information of the exposure unit and the plurality of image areas; wherein the marking information characterizes a position of the test chip in the exposure unit.

9. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-7.