CN115935866A - Verification method for integrated circuit time sequence constraint function - Google Patents

Verification method for integrated circuit time sequence constraint function Download PDF

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CN115935866A
CN115935866A CN202211683354.1A CN202211683354A CN115935866A CN 115935866 A CN115935866 A CN 115935866A CN 202211683354 A CN202211683354 A CN 202211683354A CN 115935866 A CN115935866 A CN 115935866A
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CN115935866B (en
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Abstract

The application discloses a verification method for a timing constraint function of an integrated circuit, which relates to the field of integrated circuits and comprises the steps of obtaining a timing constraint file of a chip to be tested, and analyzing constraint mark point information and timing constraint target information; determining the file type of an original description file and a time sequence file modification tool thereof, and modifying the target logic behavior of the original description file according to the circuit hierarchical structure information, the constraint mark point information and the time sequence constraint target information to obtain a time sequence constraint verification file; and performing logic function simulation and regression test on the time sequence constraint verification file based on a random function in the test case to verify the constraint effect. According to the scheme, the sequential constraint problem which cannot be checked by a rear end EDA tool can be checked by advancing the sequential verification from the subsequent gate-level netlist to the preorder RTL stage, the sequential anti-standard simulation of the sequential gate-level netlist watchband sequential is cancelled, the checking coverage rate of a test case is improved, and the speed, the detection precision and the efficiency of chip sequential constraint verification are greatly improved.

Description

Verification method for integrated circuit time sequence constraint function
Technical Field
The embodiment of the application relates to the field of integrated circuits, in particular to a verification method for a timing constraint function of an integrated circuit.
Background
Besides the logic design implementation in the field of the design of large-scale integrated circuits with high performance and low power consumption (including FPGA/IP/SOC/AISC), timing constraints are also needed to ensure that the delay time of the final real circuit after silicon wafer production meets the requirements. The purpose is to ensure that no errors occur in the logic and to implement the target function. Timing information of most circuits is usually identified and checked automatically by the back-end EDA implementation tool, but whether these timing constraints are accurate or correct is not checked or verified by the EDA tool, and usually only depends on manual inspection by an engineer, so that the following problems occur:
1. the inspection relies on the individual knowledge and abilities of the engineer and does not guarantee quality;
2. the checking result cannot be verified, and the correctness cannot be ensured;
3. the time and the times of checking are only a few times of critical research and development nodes, and some changes can be missed.
In view of the above problems, the existing mainstream design scheme does not care about the RTL stage, and even does not verify any timing constraints, mainly because:
1. no time delay behavior on the logic RTL, or the micro-delays (delta _ delay) that are both not observable by humans and visible to the simulated EDA tool;
2. timing constraints cannot be checked on the RTL, and the EDA simulation tool only performs logic function checks and does not perform timing checks. In fact, timing checks are the function of back-end implementation of EDA tools.
In a common industry project, the checking of these timing constraints typically implements a gate-level netlist (netlist) in a back-end EDA tool, and after the timing (timing) substantially converges, a timing-inversion (back-inversion) is added on the gate-level netlist, and then whether the timing is accurate is verified through a functional test. However, this solution has several problems that result in very low efficiency or even failure:
1. the simulation speed of the gate-level netlist is tens of times or even hundreds of times slower than that of the RTL;
2. the simulation speed of the gate-level netlist after the time sequence counter-scaling is lower than that of the gate-level netlist without the time sequence by tens of times or even hundreds of times;
3. the timing inversion of the gate-level netlist needs to be started when the circuit timing is basically clean, but the time is often in the very late stage of the project and even approaches the final tape-out time, and the timing simulation cannot be completed before tape-out due to the 2 reasons (low speed), so that the verification fails;
4. the timing sequence anti-standard function simulation on the gate-level netlist cannot run out all test cases (perhaps only 1% -5%), so that the completeness of timing sequence constraint verification cannot be guaranteed, and verification failure is caused.
Disclosure of Invention
The embodiment of the application provides a method for verifying a timing constraint function of an integrated circuit, which comprises the following steps:
acquiring a time sequence constraint file of a chip to be tested, analyzing circuit hierarchical structure information and constraint mark point information in the time sequence constraint file, and extracting time sequence constraint target information in the time sequence constraint file;
determining the file type of an original description file and a time sequence file modification tool thereof, and modifying the target logic behavior of the original description file according to the circuit hierarchical structure information, the constraint marking point information and the time sequence constraint target information to obtain a time sequence constraint verification file with time sequence constraint delay information;
performing logic function simulation and regression testing on the time sequence constraint verification file based on a random function in a test case to verify the constraint effect;
when the simulation or test result is wrong, modifying the time sequence constraint file or the time sequence constraint verification file according to the wrong project; and when the simulation and test result meets the requirement of the target logic behavior, ending the test and executing the subsequent chip tape-out process.
Specifically, the circuit hierarchical structure information, the constraint mark point information and the time sequence constraint target information are automatically extracted or manually extracted and confirmed by a time sequence constraint analysis tool; the types of the time sequence constraint files at least comprise TCL, excel, YAML, JSON and HASH arrays; the original description file comprises an original RTL file and an original TB design file.
Specifically, the constraint mark information is a signal start point and/or end point of constraint realization and labeling, and at least includes multicycle timing constraint multi _ cycle _ path information in a synchronous circuit, false path timing constraint false _ path information in an asynchronous circuit, minimum delay constraint min _ delay information and maximum delay constraint max _ delay information in a synchronous or asynchronous circuit, clock jitter information in a synchronous and asynchronous circuit, clock skew information in a synchronous and asynchronous circuit, clock creation clock information in a synchronous and asynchronous circuit, and data alignment data check information in a synchronous and asynchronous circuit;
and the time sequence constraint target information is the logic function behavior corresponding to the marking signal.
Specifically, the modifying the target logic behavior of the original description file according to the circuit hierarchy structure information, the constraint marking point information, and the time sequence constraint destination information to obtain the time sequence constraint verification file with time sequence constraint delay information includes:
converting the time sequence constraint information into target delay simulation behavior information based on an incorporable simulation logic statement behavior logic;
configuring a time sequence constraint logic device based on the target delay simulation behavior information, inserting the configured time sequence constraint logic device into an original RTL file, modifying the target logic behavior in the original RTL file, and generating a time sequence constraint verification file;
or;
configuring the time sequence constraint logic device based on the target delay simulation behavior information, and inserting the configured time sequence constraint logic device into an original TB design file to generate a TB verification file; binding the TB verification file with the starting point and/or the end point marked by the constraint statement in the original RTL file through the force and/or bind and/or instance statement of the HDL to generate the time sequence constraint verification file;
or;
configuring the time sequence constraint logic device based on the target delay simulation behavior information, and generating an independent TB verification file packet based on all the time sequence constraint logic devices; binding the independent TB verification file packet with a starting point and/or an end point marked by a constraint statement in an original RTL file through a force statement and/or a bind statement and/or an instance statement of an HDL (hardware description language), and generating the time sequence constraint verification file;
wherein the timing constraint delay information at least includes delay information of multi _ cycle, false _ path, min _ delay, max _ delay, clock _ jitter, clock _ skew, create _ clock, and data _ check.
Specifically, the timing constraint logic at least includes a delay buffer, a delay module, and a behavior logic;
and inserting the configured sequential constraint logic device between the starting point and/or the end point of the constraint statement label in the original description file, replacing the delay information of the original circuit simulation, and not changing the assignment transmission of the original circuit logic.
Specifically, configuring the timing constraint logic comprises:
adding delay information to the timing constraint logic when the timing constraint information comprises a multi _ cycle and the target delay simulation behavior information is a multi _ cycle _ path between two selected target data; and the delay information is randomly selected within 0 and the time upper limit through a $ random function of the original description file, and delay corresponding to target time length is generated between each bit between the data input data _ in and the data output data _ out of the time sequence constraint logic device according to different seed values of the $ random function.
When the timing constraint information comprises a false _ path and the target delay simulation behavior information is the false _ path of the selected two target data; adding delay information randomly selected from 0 and the time upper limit between the data _ in and the data _ out;
when the timing constraint information includes max _ delay, and the target delay simulation behavior information is max _ delay _ path max _ delay _ val between the selected two target data; adding delay information randomly selected from 0 to max _ delay _ val between data _ in and data _ out; wherein max _ delay _ val represents the delay upper limit duration;
when the timing constraint information includes min _ delay, and the target delay simulation behavior information is min _ delay _ path min _ delay _ val between the selected two target data; adding delay information randomly selected from min _ delay _ val and a time upper limit between the data _ in and the data _ out; wherein min _ delay _ val represents a delay lower limit duration; when the timing constraint delay information simultaneously comprises min _ delay and max _ delay, adding delay information randomly selected from the range between min _ delay and max _ delay between data _ in and data _ out;
when the timing constraint information includes clock _ jitter and the target delay emulation behavior information is clock _ jitter jitter _ val of the target data; adding delay information randomly selected from 0 to jitter val between data _ in and data _ out; where jitter _ val represents the upper limit duration of clock jitter.
Specifically, when the timing constraint information includes clock _ skew and the target delay simulation behavior information is clock _ skew _ val of the target clock; adding the configured timing constraint logic device on a clock signal of a target clock, and adding delay information randomly selected between 0 and skew _ val through a $ random function of the original description file between data _ in and data _ out of the timing constraint logic device; wherein, skew _ val represents the upper limit duration of clock deviation;
when the timing constraint information includes a create _ clock and the target delay emulation behavior information is a create _ clock period _ val of a new clock domain; adding the configured time sequence constraint logic device on a specified clock signal, and adding delay information randomly selected from 0 to period _ val between data _ in and data _ out; wherein period _ val represents a clock cycle duration;
when the timing constraint information comprises data _ check and when the target delay emulation behavior information is data _ check data _ check _ val between two target data signals; adding the two target data signals into the configured time sequence constraint logic respectively, and adding delay information randomly selected from 0 and data check val between data _ in and data _ out; wherein data _ check _ val represents a data alignment upper limit duration.
Specifically, when the timing constraint information includes a false _ path, and the target delay simulation behavior information is a multi _ false _ path between at least two clock _ domain clock domains selected, or an async relationship between at least two clock _ group clock groups; the delay information with timing constraint delay information of clock _ jitter is inserted into the set source corresponding to the clock domain or clock _ group.
Specifically, the logic function simulation and regression test of the time sequence constraint verification file based on the random function in the test case includes:
based on random function enabling, carrying out logic function simulation and regression testing on the time sequence constraint verification file and the original TB design file added into the time sequence constraint logic device, and determining the validity of delay information according to the delay time of an output signal;
or;
based on random function enabling, performing logic function simulation and regression testing on an original RTL file and the time sequence constraint verification file formed by binding the TB verification file packet and an original TB design file, and determining the validity of delay information according to the delay time of an output signal;
or;
and based on random function enabling, carrying out logic function simulation and regression testing on a timing constraint verification file formed by binding the independent TB verification file packet and the original TB design file and the original RTL file, and determining the validity of delay information according to the delay time of an output signal.
Specifically, when the delay time of the logic function simulation or regression test process is not matched with the delay information, determining an internal logic error;
when the error item indicates that the RTL file or the TB file is inserted into the error, modifying the modified timing constraint verification file again according to the original RTL file or the original TB design file, and performing simulation test again;
and when the error item indicates that the timing constraint delay information is in error, modifying the timing constraint file of the chip to be tested and executing again.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:
the time sequence constraint can be verified by using functional simulation, and the consistency and the correctness of the design and the constraint can be ensured; the sequential verification is advanced from the subsequent gate-level netlist to the preorder RTL stage, so that the sequential verification speed and efficiency are greatly improved;
the timing constraint (false _ path) that could not be checked (ignored) by even the back-end EDA tool can be checked, so that the timing constraint checked by the EDA tool can be checked by the front-end logic function simulation for correctness. Namely, what is called "shift left" in the industry, the original follow-up task is greatly advanced (at least 3 months ahead, and in fact, 6 to 12 months ahead);
after the functional verification method is adopted, the simulation of the time sequence reverse standard of the subsequent door-level network watchband can be cancelled, so that the testing precision and efficiency of the chip can be accelerated, and the construction period can be shortened;
the occupied resources and the occupied time of the simulation server and the gate-level server are greatly reduced (the requirement of gate-level belt time sequence simulation on a CPU and a memory is increased by times or even tens of times, and the occupied time of the server is between 1 month and 3 months); thus, the server can be released to other critical tasks;
the traditional door-level network watchband time sequence denotation simulation can only select few test cases (only 1 to 5 percent of the test cases are selected possibly) because of the simulation speed and the resource requirement of a server, but the invention can be used in all (100 percent of the test cases are selected) functional tests, the random function of each simulation is combined, the inspection coverage rate of the time sequence constraints is greatly improved, and the total coverage rate can reach or approach 100 percent through different time periods and the accumulation of a test set.
Drawings
FIG. 1 is a flow chart of a method of verifying timing constraint functionality of an integrated circuit;
FIG. 2 is an algorithmic flow diagram of a method of verifying timing constraint functionality of an integrated circuit;
FIG. 3 is a schematic diagram of the structure of the timing constraint logic before and after configuration of the multi _ cycle;
FIG. 4 is a signal diagram of the output of the timing constraint logic after insertion of a multi _ cycle;
FIG. 5 is a schematic diagram of the timing constraint logic after configuring the false _ path;
FIG. 6 is a signal diagram of the output of the timing constraint logic after inserting false _ path;
FIG. 7 is a schematic diagram of the configuration of the max _ delay post-timing constraint logic;
FIG. 8 is a signal diagram of the output of the timing constraint logic after insertion of max _ delay;
FIG. 9 is a schematic diagram of the configuration of the post-min _ delay timing constraint logic;
FIG. 10 is a signal diagram of the output of the timing constraint logic after the insertion of a min _ delay;
FIG. 11 is a schematic diagram of the configuration of the post-configuration min _ delay and max _ delay timing constraint logic;
FIG. 12 is a signal diagram of the output of the timing constraint logic after the insertion of min _ delay and max _ delay;
FIG. 13 is a schematic diagram of the timing constraint logic after clock _ jitter is configured;
FIG. 14 is a signal diagram of the output of the timing constraint logic after insertion of clock _ jitter;
FIG. 15 is a schematic diagram of the structure of the timing constraint logic after the create _ clock is configured;
FIG. 16 is a signal schematic of the output of the timing constraint logic after the insertion of a create _ clock;
FIG. 17 is a schematic diagram of the structure of the timing constraint logic after data _ check is configured;
FIG. 18 is a signal diagram of the output of the timing constraint logic after insertion of a data _ check;
FIG. 19 is a diagram of RTL simulation behavior before and after insertion of a multi _ cycle _ path timing constraint;
FIG. 20 is RTL simulation behavior before and after inserting a flush _ path timing constraint;
FIG. 21 is a diagram of RTL simulation behavior before and after insertion of a max _ delay timing constraint;
FIG. 22 is a diagram of RTL simulation behavior before and after insertion of clock _ jitter timing constraints;
FIG. 23 is a schematic diagram of RTL simulation behavior before and after insertion of a create _ clock timing constraint;
FIG. 24 is a diagram of RTL simulation behavior before and after insertion of data _ check timing constraints.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
Reference herein to "RTL" is to a "Register Transfer Level", i.e., a "Register Transfer Level".
As used herein, "HDL" refers to "Hardware Description Language," i.e., "Hardware Description Language," and includes Verilog, system Verilog, VHDL.
Reference herein to "TB" is to "Testbench", i.e., "test environment and System", and specifically includes RTL or HDL (including Verilog, system Verilog, VHDL) based test environments, test stimulus generation and input, test result collection and observation.
Fig. 1 is a flowchart of a method for verifying timing constraint function of an integrated circuit according to an embodiment of the present application, including the following steps:
step 101, acquiring a time sequence constraint file of a chip to be tested, analyzing circuit hierarchical structure information and constraint marking point information in the time sequence constraint file, and extracting time sequence constraint target information in the time sequence constraint file.
The timing constraint file is text data used for verification, and the types of the timing constraint file at least comprise TCL, excel, YAML, JSON, HASH arrays and the like; the content can be automatically extracted or manually extracted through a time sequence constraint analysis tool, and the extracted information comprises circuit hierarchical structure information, constraint mark point information and time sequence constraint purpose information. These two types of information are extracted automatically or manually and converted into RTL files or TB design files. The RTL file and the TB design file are hardware description files in the field of integrated circuits and are files for logic verification in the scheme.
The constraint mark information is the signal start and/or end of the constraint realization and labeling, and at least comprises multi-cycle timing constraint multi _ cycle _ path information in a synchronous circuit, false path timing constraint false _ path information in an asynchronous circuit, minimum delay constraint min _ delay information and maximum delay constraint max _ delay information in a synchronous or asynchronous circuit, clock jitter clock _ jitter information in the synchronous and asynchronous circuit, clock deviation clock _ skew information in the synchronous and asynchronous circuit, clock creation clock information in the synchronous and asynchronous circuit, and data alignment data _ check information in the synchronous and asynchronous circuit. And the timing constraint purpose information is used for explaining the corresponding logic function of the label signal, namely various delay types and delay times.
The method mainly advances the timing verification from the subsequent gate-level netlist to the pre-ordered RTL or TB stage, and simultaneously verifies the consistency and the correctness of the timing constraints and the logic design of the types. The insertion or binding timing constraint delay information, that is, the insertion or binding of the delay type time of the above types, is used for simulation. These timing constraints are all to ensure that the delay of the circuit on the final silicon does not exceed the design goals, which would otherwise result in a mismatch with the logic design and a failure of the circuit function. Specifically, the algorithm flow chart of the verification method for the integrated circuit timing constraint function in fig. 2 may be used.
And 102, determining the file type of the original description file and a time sequence file modification tool thereof, and modifying the target logic behavior of the original description file according to the circuit hierarchical structure information, the constraint mark point information and the time sequence constraint target information to obtain a time sequence constraint verification file with time sequence constraint delay information.
As described above, the original file type includes an RTL file and a TB design file, the timing file modification tool is an editing tool for modifying the RTL file and the TB design file, and the main principle is to modify the target logic behavior of the original description file, and the target logic behavior is for a specific logic function of specific constraint information, and the timing constraint delay information, that is, the delay information of multi _ cycle, false _ path, min _ delay, max _ delay, clock _ jitter, clock _ skew, create _ clock, and data _ check, etc. described above, is inserted into the position where the corresponding constraint needs to be generated.
The scheme provides a plurality of generated timing constraint verification files, and the following description respectively takes an original RTL file and a TB design file as examples.
The method for generating the timing constraint verification file based on the original RTL file specifically includes the following steps:
and A, converting the time sequence constraint information into target delay simulation behavior information based on an incorporable simulation logic statement behavior logic.
And B, configuring a time sequence constraint logic device based on the target delay simulation behavior information, inserting the configured time sequence constraint logic device into the original RTL file, modifying the target logic behavior in the original RTL file, and generating a time sequence constraint verification file.
Before the target logic behavior of the file is modified, the time sequence constraint information to be inserted needs to be converted, the time sequence constraint information is converted into target delay simulation behavior information according to the language form of the non-comprehensive simulation logic statement, and then the time sequence constraint logic device is configured according to the target delay simulation behavior information. The timing constraint logic may include various forms, such as a delay buffer, a delay module, or a behaviorlogic.
2. Generating a timing constraint verification file based on the original TB design file may specifically include the following steps:
and A, configuring a time sequence constraint logic device based on the target delay simulation behavior information, inserting the configured time sequence constraint logic device into an original TB design file, and generating a TB verification file.
And B, binding the TB verification file with the starting point and/or the end point marked by the constraint statement in the original RTL file through the force and/or bind and/or the instance statement of the HDL to generate a time sequence constraint verification file.
The method is a generation mode different from that of modifying RTL, and has the main principle that a new TB verification file is regenerated on the basis of an original TB design file, time sequence constraint delay information is added and configured in the generation process, and then a TB verification file packet and the original RTL file are bound (essentially, a binding relation is established between two files and a synthesized file is not generated) through a force statement and/or a bind statement and serve as the time sequence constraint verification file.
Besides, the scheme for separately generating the TB design file comprises the following steps:
and A, configuring a time sequence constraint logic device based on target delay simulation behavior information, and generating an independent TB verification file packet based on all the time sequence constraint logic devices.
And B, binding the independent TB verification file packet with the starting point and/or the end point marked by the constraint statement in the original RTL file through the force statement and/or the bind statement and/or the instance of the HDL to generate a time sequence constraint verification file.
The method is that on the premise of not changing the original TB design file, the information to be inserted is separately generated into an independent TB verification file (package), and then the independent TB verification file (package) is forcibly generated by being bound with the original RTL file.
The timing constraint logic comprises at least a delay buffer delay _ buffer, a delay module delay _ module and a behavior logic. And a configured delay buffer or a delay module is inserted between the starting point and/or the end point of the constraint statement label to replace the delay information of the original circuit simulation without changing the logic assignment transmission of the original circuit.
Regardless of the timing constraint logic employed, the configuration process may include the following:
multi _ cycle: when the timing constraint information includes a multi _ cycle and the target delay emulation behavior information is a multi _ cycle _ path between two selected target data, delay information is added to the timing constraint logic. And the delay information is randomly selected within 0 and time upper limit through a $ random function of the original description file, and delay corresponding to target time length is generated between each bit between the data input data _ in and the data output data _ out of the time sequence constraint logic device according to different seed values of the $ random function.
For example, in one possible implementation, the constraint is set multi _ cycle _ path 3-from xxx. The present invention inserts timing constraint logic between xxx, yyy, zzz, data _ out and aaa. This delay behavior is randomly chosen within 0 and an upper time limit (16 clock cycles h or other value) by the $ random function of RTL. The delay between each bit is determined by the different seed values of the $ random function, but the maximum delay of all bits does not exceed an upper limit (16 clock cycles or other values), specifically from 0 to clock cycles x multi _ cycle number. Aaa, bbb, ccc, data _ in t and xxx, yyy, zzz, data _ out respectively represent the selected target data input and the target data output, and the inserted timing constraint logic is positioned between the selected target data input and the target data output.
Fig. 3 is a schematic diagram of the structure of the timing constraint logic before and after the multi _ cycle is configured, and fig. 4 is a schematic diagram of the signals output after the timing constraint logic is inserted after the multi _ cycle. As can be seen from fig. 4, the delay of each data _ out outputting a plurality of bits after configuration is different, and all of them do not exceed 2 × period.
false _ path: when the timing constraint information comprises a false _ path and the target delay simulation behavior information is a false _ path between two selected target data; delay information randomly selected from between 0 and the upper time limit is added between data _ in and data _ out.
For example, in one possible implementation, the constraint is set false _ path-from xxx.yyy.zzz.data _ out-to aaa.bbb.ccc.data _ in. The present invention inserts timing constraint logic between xxx, yyy, zzz, data _ out and aaa.bbb.ccc.data _ in, this buffer adds signal delay, this delay behavior is chosen randomly within 0 and the upper time limit (16 clock cycles or other values) by the $ random function of RTL, and by configuring different seed values of the $ random function to keep the delay between each bit from data _ out to data _ in different, but the maximum delay of all bits will not exceed the upper time limit (16 clock cycles or other values).
FIG. 5 is a schematic diagram of a configuration of the post-false _ path timing constraint logic, and FIG. 6 is a schematic diagram of signals inserted into the output of the post-false _ path timing constraint logic. As can be seen from the figure, the delay of each data _ out after configuration for outputting a plurality of bits is different, and all of them do not exceed 16 × period ((1) represents the maximum 16 × period).
The upper limit of the delay time is 16 clock cycles mainly to reduce the influence on the overall simulation time and prevent the possibility that the simulation cannot be normally ended in some cases. Other numbers may be selected as appropriate, but should not be less than 3.
It should be noted here that, when the timing constraint information includes a false _ path, and the target delay simulation behavior information is a multi _ false _ path between at least two clock _ domain clock domains or an async relationship between at least two clock _ group clock groups; the delay information with the timing constraint delay information being clock _ jitter is inserted at the set source of the corresponding domain or clock _ group. For example, when the constraint is set multi _ false _ path-from clock _ domain na (or clock _ group a) -to clock _ domain b (or clock _ group b), the timing constraint logic is not inserted into the path between all domains na (group pa) and domain b (group pb) in the present solution, but the constraint logic is implemented by inserting a jitter into the clock, which is described in detail later.
max _ delay: when the timing constraint information includes max _ delay and the target delay simulation behavior information is max _ delay _ path min _ delay _ val between the selected two target data; adding delay information randomly selected from 0 to max _ delay _ val between the data _ in and the data _ out; wherein max _ delay _ val represents the delay upper limit duration;
for example, the constraint is set max _ delay _ path # max _ delay _ val (say 3 ns) -from xxx.yyy.zzz.data _ out-to aaa.bbb.ccc.data _ in. The present invention inserts timing constraint logic between xxx, yyy, zzz, data _ out and aaa.bbb.ccc.data _ in, which adds signal delay that is randomly selected within 0 and max _ delay _ val (3 ns) by the $ random function of RTL, and by configuring different seed values of the $ random function to keep the delay between each bit from data _ out to data _ in different, but to ensure that the maximum delay of all bits is no greater than # max _ delay _ val.
Fig. 7 is a schematic diagram of a configuration of the post-max _ delay timing constraint logic, and fig. 8 is a schematic diagram of signals inserted into the output of the post-max _ delay timing constraint logic. As can be seen from the figure, the delays of the respective data _ out outputting a plurality of bits after configuration are different and do not exceed max _ delay.
min _ delay: when the timing constraint information includes min _ delay, and the target delay simulation behavior information is min _ delay _ path min _ delay _ val between the selected two target data; adding delay information randomly selected from min _ delay _ val and a time upper limit between the data _ in and the data _ out; where min _ delay _ val represents a delay lower limit duration.
For example, in one possible implementation, the constraint is set min _ delay _ path # min _ delay _ val (say 0.3 ns) -from xxx.yyy.zzz.data _ out-to aaa.bbb.ccc.data _ in. The present invention inserts timing constraint logic between xxx, yyy, zzz, data _ out and aaa.bbb.ccc.data _ in, this buffer adds signal delay, this delay behavior makes random selection within # min _ delay _ val (0.3 ns) and time ceiling through the $ random function of RTL, and keeps the delay between each bit from data _ out to data _ in different by configuring different seed values of $ random function, but guarantees that the minimum delay of all bits is not less than min _ delay _ val, and the maximum delay does not exceed the time ceiling.
Fig. 9 is a schematic diagram of a configuration of the post-min _ delay timing constraint logic, and fig. 10 is a schematic diagram of signals inserted into the output of the post-min _ delay timing constraint logic. As can be seen from the figure, the delays of the respective data _ out outputting a plurality of bits after configuration are different and are all larger than min _ delay.
As can be known from the above-mentioned min _ delay and max _ delay, when the timing constraint information includes both min _ delay and max _ delay, delay information randomly selected from between min _ delay and max _ delay _ val is added between data _ in and data _ out, instead of taking 16 cycles as an upper limit.
Fig. 11 is a schematic diagram of a configuration of the post-min _ delay and post-max _ delay timing constraint logic, and fig. 12 is a schematic diagram of signals inserted into outputs of the post-min _ delay and post-max _ delay timing constraint logic. As can be seen from the figure, the data _ out outputs a plurality of bits with different delays after configuration, but all the delays are located between min _ delay and max _ delay ((1) represents the minimum delay, and (2) represents the maximum delay).
clock _ jitter: when the timing constraint information includes clock _ jitter and when the target delay emulation behavior information is clock _ jitter jitter _ val of the target data output; adding delay information randomly selected from 0 to jitter val between data _ in and data _ out; wherein jitter _ val represents the clock jitter upper limit duration.
For example, the constraint is set clock _ jitter # jitter _ val (say 0.03 ns) xx. The present invention adds a timing constraint logic to the xx.yy.zz _ clk _ out signal (target data out) of the RTL, which adds a signal delay that is randomly selected within 0 and jitter _ val (0.03 ns) by the $ random function of the RTL.
FIG. 13 is a schematic diagram of a configuration of post-clock _ jitter timing constraint logic, and FIG. 14 is a schematic diagram of signals output by post-clock _ jitter timing constraint logic. The Clk _ out and Clk _ out _ dly correspond to data _ in and data _ out, and it can be seen that there is a random delay between the phases of each clock, and there is also a corresponding random delay between the data of each clock ((1) denotes phase difference, (2) denotes random delay corresponding to data).
clock _ skew: when the timing constraint information comprises clock _ skew and the target delay simulation behavior information is clock _ skew _ val of the target clock; adding a configured time sequence constraint logic device on a clock signal of a target clock, and adding delay information randomly selected between 0 and skew _ val through a $ random function of an original description file between data _ in and data _ out of the time sequence constraint logic device; wherein skew _ val represents a clock skew upper limit duration.
For example, with a constraint set _ clock _ skew # skew _ val (e.g., 0.5 ns) [ get _ clock # clock _ name ], the present invention adds a timing constraint logic (delay _ buffer) to the RTL's # clock _ name signal, which adds a signal delay that is randomly selected within 0 and skew _ val (0.5 ns) by the RTL's $ random function. The scheme performs delay verification on all clock _ skew by default.
create _ clock: when the timing constraint information includes a create _ clock and the target delay emulation behavior information is a create _ clock period _ val of the new clock domain; adding a configured time sequence constraint logic device on a specified clock signal, and adding delay information randomly selected from 0 to period _ val between data _ in and data _ out; where period _ val represents the clock cycle duration.
If the clock constraint defines a new clock domain, for example, the constraint is create _ clock-add-name # new _ clock-period # period _ val (e.g., 2 ns) [ get _ pin xx. The present invention adds a timing constraint logic (delay buffer) to the xx, yy, zz out signal (clock signal) of the RTL, which adds a signal delay that is randomly selected within 0 and period val (2 ns) by the $ random function of the RTL. The scheme verifies all create _ clocks by default.
Fig. 15 is a schematic diagram showing the configuration of the timing constraint logic after the create _ clock is configured, and fig. 16 is a schematic diagram showing the signals output by the timing constraint logic after the create _ clock is inserted. Clk _ out and Clk _ out _ dly correspond to data _ in and data _ out, and as can be seen from the figure, random delay exists between different clocks, and neither does not exceed a set period.
data _ check: when the timing constraint information includes data _ check, and when the target delay emulation behavior information is data _ check data _ check _ val between two target data; respectively adding the configured time sequence constraint logic devices into the two target data, and adding delay information randomly selected from 0 and data check val between the data _ in and the data _ out; wherein, data _ check _ val represents the upper limit duration of data alignment.
For example, the constraint is set _ data _ check # data _ check _ val (say 1 ns) -from [ get _ pinxx.yy.zz.data _ out [ m ] ] -to [ get _ pin xx.yy.zz.data _ out [ n ] ]. The present invention adds a timing constraint logic to each of the xx.yy.zz.data _ out [ m ] and xx.yy.zz.data _ out [ n ] signals (two target data signals) of the RTL, and the buffer adds a signal delay that is randomly selected within 0 and data _ check _ val (1 ns) by the $ random function of the RTL.
Fig. 17 is a schematic diagram of a structure of a timing constraint logic device after data _ check is configured, and fig. 18 is a schematic diagram of signals output by the timing constraint logic device after data _ check is inserted. The data _ out and the data _ out _ dly correspond to the data _ in and the data _ out, and as can be seen from the figure, the delays of the bits are not the same but are not more than the data alignment period.
It should be noted that what is described above is a possible configuration, and other override means may be used to add the timing constraint delay information, which is not described herein again.
And obtaining the time sequence constraint verification file inserted with the time sequence constraint delay information after the configuration is completed.
And 103, performing logic function simulation and regression testing on the time sequence constraint verification file based on a random function in the test case, and verifying the constraint effect.
In the logic function simulation and regression test, the effectiveness of delay information is determined according to the delay time of an output signal when the logic function simulation and regression test are carried out on the timing constraint verification file through random function enabling.
For the form of generating the time sequence constraint verification file, the verification process is divided into the following cases:
1. and based on random function enabling, carrying out logic function simulation and regression testing on the time sequence constraint verification file and the original TB design file added into the time sequence constraint logic device, and determining the validity of delay information according to the delay time of an output signal.
2. And based on random function enabling, carrying out logic function simulation and regression testing on a time sequence constraint verification file generated by binding the TB verification file and the original RTL file, and determining the validity of delay information according to the delay time of an output signal.
3. And based on random function enabling, carrying out logic function simulation and regression testing on a timing constraint verification file formed by binding the independent TB verification file packet and the original TB design file and the original RTL file, and determining the validity of delay information according to the delay time of an output signal.
Because RTL behavior at timing constraints models delays on real circuits, there is a high probability that functional simulation errors will result if the logic design is wrong or the timing constraints are wrong. Even though no logic function error is caused in most cases, the delay time of the timing constraint logic device in each function simulation or regression test is different from that between the logic function simulation and regression test of different batches because of the existence of the random function. If the logic design or the timing constraint is not accurate, functional errors are necessarily caused under certain delay conditions, so that whether the logic errors or the timing constraint errors exist can be checked.
104, when the simulation or test result has an error, modifying the time sequence constraint verification file or the time sequence constraint verification file according to the error item; and when the simulation and test result meets the requirement of the target logic behavior, ending the test and executing the subsequent chip tape-out process.
When the delay time of the logic function simulation or regression test process and the delay information logic function result is inaccurate due to the addition of the delay information, it can be determined that the internal logic design and the timing constraint are not matched.
And when the error item indicates that the RTL or TB design file has an error, modifying the modified timing constraint verification file according to the original RTL or TB design file again, and performing the simulation test again.
And when the error item indicates that the timing constraint delay information is in error, modifying the timing constraint file of the chip to be tested, and performing the simulation test after the steps are executed again until the conditions are met.
And if the functional simulation and the regression test are completely free from errors, entering a subsequent implementation process, and carrying out traditional design implementation and time sequence inspection.
The final simulation behavior is described below in a specific embodiment, and the results of all different implementation forms are consistent with the following behavior; and the following examples include only part of the circuit behavior and do not cover all possibilities (due to the presence of random functions).
multi _ cycle: referring to fig. 19, a schematic diagram of RTL simulation behavior before and after inserting a multi _ cycle timing constraint is shown.
RTL simulation behavior without delay (upper part), (1) illustrates no delay of the sampling control circuit; (2) the process shows that the sampling control circuit is correct and the data is correct; (3) the sampling control circuit is wrong, but the data still shows correct. So the RTL simulation behavior without delay does not cause simulation function errors even if circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower), (1) bit random delay; (2) the captured data is correct; (3) a fetch data error. It can be seen that, in the RTL simulation behavior after the timing constraint destination behavior is added, a simulation functional error may occur due to a circuit or timing constraint error.
multi _ cycle: referring to fig. 20, a schematic diagram of RTL simulation behavior before and after inserting the flase _ path timing constraint is shown.
RTL simulation behavior without delay (top), (1) no bit delay is illustrated; (2) the process shows that the sampling control circuit is correct and the data is correct; (3) the sampling control circuit is wrong, but the data still shows correct. So the RTL simulation behavior without delay does not cause simulation function errors even if circuit or timing constraints are wrong.
RTL with delay emulates behavior (lower), (1) bit random delay; (2) the captured data is correct; (3) a fetch data error. Therefore, the simulation function error can occur due to circuit or timing constraint error of RTL simulation behavior after the timing constraint target behavior is added.
max _ delay: referring to fig. 21, a schematic diagram of RTL simulation behavior before and after inserting max _ delay timing constraints is shown.
RTL simulation behavior without delay (top), (1) no bit delay is illustrated; (2) the process shows that the sampling control circuit is correct and the data is correct; (3) the sampling control circuit is wrong, but the data still shows correct. So the RTL simulation behavior without delay will not cause simulation function errors even if circuit or timing constraints are wrong.
RTL with delay emulates behavior (lower), (1) bit random delay; (2) the captured data is correct; (3) a fetch data error. It can be seen that, in the RTL simulation behavior after the timing constraint destination behavior is added, a simulation functional error may occur due to a circuit or timing constraint error.
clock _ jitter: referring to FIG. 22, a diagram of RTL simulation behavior before and after insertion of clock _ jitter timing constraints is shown.
RTL simulation behavior without delay (top), (1) no jitter constraint; (2) the data capture is correct; (3) the sampling control circuit is wrong, but the data still shows correct. So the RTL simulation behavior without delay does not cause simulation function errors even if circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower), (1) insert clock _ jitter timing constraint; (2) the captured data is correct; (3) a fetch data error. It can be seen that, in the RTL simulation behavior after the timing constraint destination behavior is added, a simulation functional error may occur due to a circuit or timing constraint error.
create _ clock: referring to FIG. 23, the RTL simulation behavior before and after insertion of the create _ clock timing constraint is shown.
RTL simulation behavior without delay (upper), (1) no time delay is indicated; (2) the data capture is correct; (3) the sampling control circuit is wrong, but the data still shows correct. So the RTL simulation behavior without delay will not cause simulation function errors even if circuit or timing constraints are wrong.
RTL simulation with delay behavior (lower), (1) indicates random delays between different clocks, both less than clock _ period; (2) the captured data is correct; (3) a fetch data error. It can be seen that, in the RTL simulation behavior after the timing constraint destination behavior is added, a simulation functional error may occur due to a circuit or timing constraint error.
data _ check: referring to FIG. 24, the RTL simulation behavior before and after inserting the data _ check timing constraint is shown.
RTL simulation behavior without delay (upper), (1) indicates no time delay between multiple bits; (2) the data capture is correct; (3) the sampling control circuit is wrong, but the data still shows correct. So the RTL simulation behavior without delay will not cause simulation function errors even if circuit or timing constraints are wrong.
RTL simulation behavior with delay (lower), (1) indicates that there is random delay between different clocks, and all are less than clock _ period; (2) the captured data is correct; (3) a fetch data error. Therefore, the simulation function error can occur due to circuit or timing constraint error of RTL simulation behavior after the timing constraint target behavior is added.
In summary, the present application can achieve the following technical effects:
the timing constraint can be verified by functional simulation, and the consistency and correctness of design and constraint can be ensured; the sequential verification is advanced from the subsequent gate-level netlist to the preorder RTL stage, so that the sequential verification speed and efficiency are greatly improved;
the timing constraint (false _ path) that could not be checked (ignored) by even the back-end EDA tool can be checked, so that the timing constraint checked by the EDA tool can be checked by the front-end logic function simulation for correctness. Namely, what is called "shift left" in the industry, the original follow-up task is greatly advanced (at least 3 months ahead, and in fact, 6 to 12 months ahead);
after the functional verification method is adopted, the simulation of the time sequence reverse standard of the subsequent door-level network watchband can be cancelled, so that the testing precision and efficiency of the chip can be accelerated, and the construction period can be shortened;
greatly reducing the occupied resources and the occupied time of the simulation server and the gate-level server (the requirement of gate-level belt time sequence simulation on a CPU and a memory is increased by times or even tens of times, and the occupied time of the server is between 1 month and 3 months); thus, the server can be released to other critical tasks;
the traditional gate-level network watchband time sequence anti-standard simulation can only select few test cases (only 1 to 5 percent of the test cases are selected possibly) because of the simulation speed and the resource requirement of a server, but the invention can be used in all (100 percent of the test cases are selected) functional tests, the random function of each simulation is combined, the inspection coverage rate of the time sequence constraints is greatly improved, and the total coverage rate can reach or approach 100 percent through different time periods and the accumulation of a test set.
The above description is that of the preferred embodiment of the present invention; it is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; any person skilled in the art can make many possible variations and modifications, or modify equivalent embodiments, without departing from the technical solution of the invention, without affecting the essence of the invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A method for verifying timing constraint functions of an integrated circuit, the method comprising:
acquiring a time sequence constraint file of a chip to be tested, analyzing circuit hierarchical structure information and constraint mark point information in the time sequence constraint file, and extracting time sequence constraint target information in the time sequence constraint file;
determining the file type of an original description file and a time sequence file modification tool thereof, and modifying the target logic behavior of the original description file according to the circuit hierarchical structure information, the constraint marking point information and the time sequence constraint target information to obtain a time sequence constraint verification file with time sequence constraint delay information;
performing logic function simulation and regression test on the time sequence constraint verification file based on a random function in the test case to verify the constraint effect;
when the simulation or test result is wrong, modifying the time sequence constraint file or the time sequence constraint verification file according to the wrong project; and when the simulation and test results meet the requirements of the target logic behaviors, ending the test and executing the subsequent chip flow process.
2. The method of claim 1, wherein the circuit hierarchy information, the constraint token information, and the timing constraint objective information are automatically extracted and confirmed by a timing constraint analysis tool or manually extracted and confirmed by a human; the types of the time sequence constraint files at least comprise TCL, excel, YAML, JSON and HASH arrays; the original description file includes an original RTL file and an original TB design file.
3. The method of claim 2, wherein the constraint flag information is a constraint realization and marked signal start and/or end point, and includes at least multi-cycle _ path information in synchronous circuits, "false path" timing constraint false _ path information in asynchronous circuits, "minimum delay constraint min _ delay information and maximum delay constraint max _ delay information in synchronous or asynchronous circuits," clock jitter _ jitter information in synchronous and asynchronous circuits, "clock skew" clock _ skew information in synchronous and asynchronous circuits, "clock creation" create _ clock information in synchronous and asynchronous circuits, "data alignment data _ check information in synchronous and asynchronous circuits;
and the time sequence constraint target information is the logic function behavior corresponding to the marking signal.
4. The method according to claim 3, wherein the modifying the target logic behavior of the original description file according to the circuit hierarchy information, the constraint marker point information, and the timing constraint destination information to obtain a timing constraint verification file with timing constraint delay information comprises:
converting the time sequence constraint information into target delay simulation behavior information based on an incorporable simulation logic statement behavior logic;
configuring a time sequence constraint logic device based on the target delay simulation behavior information, inserting the configured time sequence constraint logic device into an original RTL file, and modifying the target logic behavior therein to generate a time sequence constraint verification file;
or;
configuring the time sequence constraint logic device based on the target delay simulation behavior information, and inserting the configured time sequence constraint logic device into an original TB design file to generate a TB verification file; binding the TB verification file with the starting point and/or the end point marked by the constraint statement in the original RTL file through the force and/or bind and/or instance statement of the HDL to generate the time sequence constraint verification file;
or;
configuring the time sequence constraint logic device based on the target delay simulation behavior information, and generating an independent TB verification file packet based on all the time sequence constraint logic devices; binding the independent TB verification file packet with the starting point and/or the end point marked by the constraint statement in the original RTL file through the force statement and/or the bind statement and/or the instance statement of the HDL to generate the time sequence constraint verification file;
wherein the timing constraint delay information at least includes delay information of multi _ cycle, false _ path, min _ delay, max _ delay, clock _ jitter, clock _ skew, create _ clock, and data _ check.
5. The method of claim 4, wherein the timing constraint logic comprises at least a delay buffer, a delay module, and a behavior logic;
and inserting the configured sequential constraint logic device between the starting point and/or the end point of the constraint statement label in the original description file, replacing the delay information of the original circuit simulation, and not changing the assignment transmission of the original circuit logic.
6. The method of claim 5, wherein configuring the timing constraint logic comprises:
adding delay information to the timing constraint logic when the timing constraint information comprises a multi _ cycle and the target delay simulation behavior information is a multi _ cycle _ path between two selected target data; and the delay information is randomly selected within 0 and the time upper limit through the $ random function of the original description file, and delay corresponding to target duration is generated between each bit from the data input data _ in to the data output data _ out of the time sequence constraint logic device according to different seed values of the $ random function.
When the timing constraint information comprises a false _ path and the target delay simulation behavior information is the false _ path of the selected two target data; adding delay information randomly selected from 0 and the time upper limit between the data _ in and the data _ out;
when the timing constraint information includes max _ delay, and the target delay simulation behavior information is max _ delay _ path max _ delay _ val between the selected two target data; adding delay information randomly selected from 0 to max _ delay _ val between the data _ in and the data _ out; wherein max _ delay _ val represents the delay upper limit duration;
when the timing constraint information includes min _ delay and the target delay simulation behavior information is min _ delay _ path min _ delay _ val between the selected two target data; adding delay information randomly selected from min _ delay _ val and a time upper limit between the data _ in and the data _ out; wherein min _ delay _ val represents a delay lower limit duration; when the timing constraint delay information simultaneously comprises min _ delay and max _ delay, adding delay information randomly selected from the range between min _ delay and max _ delay between data _ in and data _ out;
when the timing constraint information includes clock _ jitter and the target delay emulation behavior information is clock _ jitter jitter _ val of the target data; adding delay information randomly selected from 0 to jitter val between data _ in and data _ out; wherein jitter _ val represents the clock jitter upper limit duration.
7. The method of claim 1, wherein when the timing constraint information includes clock _ skew and the target delay simulation behavior information is clock _ skew _ val of a target clock; adding the configured time sequence constraint logic device on a clock signal of a target clock, and adding delay information randomly selected between 0 and skew _ val through a $ random function of the original description file between data _ in and data _ out of the time sequence constraint logic device; wherein the skew _ val represents the upper limit duration of the clock deviation;
when the timing constraint information comprises create _ clock and the target delay emulation behavior information is create _ clock period _ val of a new clock domain; adding the configured time sequence constraint logic device on a specified clock signal, and adding delay information randomly selected from 0 to period _ val between data _ in and data _ out; wherein period _ val represents a clock cycle duration;
when the timing constraint information comprises data _ check and when the target delay emulation behavior information is data _ check data _ check _ val between two target data signals; adding the two target data signals into the configured time sequence constraint logic respectively, and adding delay information randomly selected from 0 and data check val between data _ in and data _ out; wherein, data _ check _ val represents the upper limit duration of data alignment.
8. The method of claim 6, wherein when the timing constraint information comprises false _ path and the target delay simulation behavior information is a multi _ false _ path between at least two clock _ domain clock domains or an async relationship between at least two clock _ group clock groups; the delay information with timing constraint delay information of clock _ jitter is inserted into the set source corresponding to the clock domain or clock _ group.
9. The method of claim 4, wherein performing logic function simulation and regression testing on the timing constraint verification file based on a random function in a test case comprises:
based on random function enabling, carrying out logic function simulation and regression testing on the time sequence constraint verification file and the original TB design file added into the time sequence constraint logic device, and determining the validity of delay information according to the delay time of an output signal;
or;
based on random function enabling, performing logic function simulation and regression testing on an original RTL file and the time sequence constraint verification file formed by binding the TB verification file packet and an original TB design file, and determining the validity of delay information according to the delay time of an output signal;
or;
and based on random function enabling, carrying out logic function simulation and regression testing on a timing constraint verification file formed by binding the independent TB verification file packet and the original TB design file and the original RTL file, and determining the validity of delay information according to the delay time of an output signal.
10. The method of claim 9, wherein when the delay time of the logic function simulation or the regression test process does not match the delay information, determining an internal logic error;
when the error item indicates that the RTL file or the TB file is inserted in error, modifying the modified time sequence constraint verification file again according to the original RTL file or the original TB design file, and carrying out simulation test again;
and when the error item indicates that the timing constraint delay information is in error, modifying the timing constraint file of the chip to be tested and executing again.
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