CN115934031B - Computing engine, data processing method, device and storage medium - Google Patents
Computing engine, data processing method, device and storage medium Download PDFInfo
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Abstract
The application provides a computing engine, a data processing method, a device and a storage medium, wherein the computing engine comprises: the system comprises at least one advanced operation unit, a state query unit and at least one logic operation unit, wherein the at least one advanced operation unit is connected with the state query unit, and the state query unit is connected with the at least one logic operation unit; at least one advanced arithmetic unit for acquiring data to be processed; the state inquiry unit is used for inquiring the state of at least one logic operation unit and obtaining the logic operation unit in an idle state; the logic operation unit is in an idle state and is used for receiving and processing data to be processed to obtain a data processing result; at least one advanced arithmetic unit is also used for receiving the data processing result. The calculation engine can effectively reduce the number of the logic operation units, realize the common and flexible distribution of the logic operation units required by the advanced operation units, reduce the area of the calculation engine, further reduce the cost and be easy to design.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a computing engine, a data processing method, an electronic device, and a computer readable storage medium.
Background
Data encryption refers to encrypting data by using an encryption algorithm, so that the data security is protected. The encryption algorithm may include a symmetric encryption algorithm and an asymmetric encryption algorithm, among others.
In the asymmetric encryption algorithm, two keys, a public key (abbreviated as a public key) and a private key (abbreviated as a private key), are required. The keys used for data encryption and the keys used for data decryption are different keys, so that the encryption strength of the asymmetric encryption algorithm is high.
However, the high complexity of asymmetric encryption algorithms results in their computational inefficiency. In order to improve the computing efficiency of the asymmetric encryption algorithm, a computing engine is generally formed by using a plurality of identical algorithm circuits to complete the computation. However, the above method results in a relatively high logic operation unit in the computing engine, thereby increasing the manufacturing cost.
Disclosure of Invention
The application provides a computing engine which can realize the sharing of logic operation units required by different high-level operation units, thereby reducing the area of the computing engine. The application also provides a data processing method, electronic equipment, a computer readable storage medium and a computer program product corresponding to the calculation engine.
In a first aspect, the present application provides a computing engine. The computing engine includes: the system comprises at least one advanced operation unit, a state query unit and at least one logic operation unit, wherein the at least one advanced operation unit is connected with the state query unit, and the state query unit is connected with the at least one logic operation unit;
the at least one advanced operation unit is used for acquiring data to be processed;
the state query unit is used for querying the state of the at least one logic operation unit to obtain the logic operation unit in an idle state;
the logic operation unit in the idle state is used for receiving and processing the data to be processed to obtain a data processing result;
the at least one advanced arithmetic unit is further configured to receive the data processing result.
In some possible implementations, the state query unit is further configured to:
feeding back the logic operation unit in the idle state to the at least one advanced operation unit and communicating with the logic operation unit in the idle state;
the at least one advanced arithmetic unit is specifically configured to:
and sending the data to be processed to the logic operation unit in the idle state through the state query unit.
In some possible implementations, the data processing result includes a plurality of sub-processing results, and the at least one advanced arithmetic unit is further configured to:
and outputting the data processing result after receiving all the sub-processing results.
In some possible implementations, the at least one advanced arithmetic unit includes: at least one of Montgomery multiplication operation unit, point addition operation unit, multiple point operation unit, point multiplication operation unit and hash algorithm operation unit.
In some possible implementations, the logic operation unit includes at least one sub operation unit, where the at least one sub operation unit includes: at least one of an addition unit, a subtraction unit, a multiplication unit, a modular addition unit, a modular subtraction unit, a modular multiplication unit, and an exclusive or operation unit.
In a second aspect, the present application provides a data processing method. The method is applied to a computing engine, the computing engine comprises at least one advanced operation unit, a state query unit and at least one logic operation unit, the at least one advanced operation unit is connected with the state query unit, the state query unit is connected with the at least one logic operation unit, and the method comprises the following steps:
the at least one advanced operation unit acquires data to be processed;
the state inquiry unit inquires the state of the at least one logic operation unit to obtain a logic operation unit in an idle state;
the logic operation unit in the idle state receives and processes the data to be processed to obtain a data processing result;
the at least one advanced arithmetic unit receives the data processing result.
In some possible implementations, the method further includes:
determining a high-level operation unit corresponding to the data to be processed from the at least one high-level operation unit;
the at least one advanced arithmetic unit obtains data to be processed, including:
and the advanced operation unit corresponding to the data to be processed acquires the data to be processed.
In some possible implementations, the data processing result includes a plurality of sub-processing results, the method further including:
and after the at least one advanced operation unit receives all the sub-processing results, outputting the data processing results.
In a third aspect, the present application provides an electronic device. The electronic device comprises a processor and a memory, the memory having instructions stored therein, the processor executing the instructions to cause the electronic device to perform the method of the second aspect or any implementation of the second aspect.
In a fourth aspect, the present application provides a computer-readable storage medium. The computer readable storage medium comprises computer readable instructions which, when run on an electronic device, cause the electronic device to perform the method of the second aspect or any implementation of the second aspect.
In a fifth aspect, the present application provides a computer program product. The computer program product comprises computer readable instructions which, when run on an electronic device, cause the electronic device to perform the method of the second aspect or any implementation of the second aspect described above.
Further combinations of the present application may be made to provide further implementations based on the implementations provided in the above aspects.
Based on the above description, the technical scheme of the application has the following beneficial effects:
specifically, the computing engine comprises at least one advanced operation unit, a state query unit and at least one logic operation unit, wherein the at least one advanced operation unit is connected with the state query unit, and the state query unit is connected with the at least one logic operation unit. The state query unit is used for querying the state of the at least one logic operation unit and obtaining the logic operation unit in an idle state, the logic operation unit in the idle state is used for receiving and processing the data to be processed so as to obtain a data processing result, and the at least one advanced operation unit is also used for receiving the data processing result.
When the high-level operation unit has data to be processed, the computing engine sends the data to be processed to the idle logic operation unit for processing by adding the state query unit, so that the function of flexibly scheduling the data to be processed is realized. Compared with the structure that each advanced operation unit in the traditional calculation engine independently uses the logic operation units, the calculation engine can effectively reduce the number of the logic operation units, realize common and flexible distribution of the logic operation units required by the advanced operation units, thereby reducing the area of the calculation engine, further reducing the cost and being easy to design.
Drawings
The above and other features, advantages and aspects of embodiments of the present application will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale.
FIG. 1 is a schematic diagram of a conventional computing engine according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a computing engine according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a logic operation unit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a status query unit according to an embodiment of the present application;
FIG. 5 is a schematic flow chart of a data processing method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device for implementing data processing according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, or units and not for limiting the order or interdependence of the functions performed by such devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.
In order to facilitate understanding of the technical scheme of the present application, specific technical terms and application scenarios in the present application are described below.
Data encryption (data encryption) is a method of protecting data. The data encryption is to encrypt the data by using an encryption algorithm (encryption algorithm), thereby playing a role in protecting the data security. In data encryption, original and unencrypted data are called plaintext, data encrypted by an encryption algorithm are called ciphertext, a process of converting the plaintext into the ciphertext is called encryption, a process of converting the ciphertext into the plaintext is called decryption, and a character string composed of numbers, letters or special symbols is called a key, which controls the data encryption and decryption processes.
The encryption algorithms include a symmetric encryption algorithm (symmetric encryption algorithm) and an asymmetric encryption algorithm (asymmetric cryptographic algorithm). Symmetric encryption algorithm refers to an encryption algorithm that uses the same key in both encryption and decryption processes. During data exchange, the sender and the receiver generate a key by using a symmetric encryption algorithm, and encrypt and decrypt data by using the key.
An asymmetric encryption algorithm refers to an encryption algorithm that uses two different keys in the encryption and decryption process. Wherein the two different keys include a public key and a private key. During data exchange, a receiver can generate a pair of public key and private key by using an asymmetric encryption algorithm, the public key is disclosed, a sender encrypts data by using the public key and sends the encrypted data, and a receiver decrypts by using the private key. Further, when signing and signing, one party can utilize an asymmetric encryption algorithm to generate a pair of public key and private key, and use the private key to sign encrypted data, and the other party uses the public key to sign the signature.
By comparing the symmetric encryption algorithm and the asymmetric encryption algorithm, the symmetric encryption algorithm has the advantages of small calculated amount, high encryption speed and high encryption efficiency, but the same secret key is used, so that the security is lower. The asymmetric encryption algorithm has high encryption strength and higher security and reliability than the symmetric encryption algorithm. However, the asymmetric encryption algorithm is computationally inefficient due to its high complexity.
In order to solve the problem of low calculation efficiency of the asymmetric encryption algorithm, a plurality of identical algorithm circuits are generally utilized to form a calculation engine to complete the calculation of the asymmetric encryption algorithm.
Referring to FIG. 1, a schematic diagram of a conventional computing engine is shown. The calculation engine 100 includes a plurality of arithmetic circuits 101, and each arithmetic circuit 101 includes a plurality of advanced arithmetic units and a plurality of logical arithmetic units. The advanced arithmetic units are in one-to-one correspondence with the logic arithmetic units, namely, each advanced arithmetic unit independently uses one logic arithmetic unit. The logic operation unit may process the data such that each advanced operation unit generates a different data processing result.
It will be appreciated that the need to deploy multiple identical algorithm circuits 101 in the computing engine 100 is to meet the processing requirements of multiple identical advanced arithmetic units within the same time frame. For example, if only one algorithm circuit 101 is disposed in the computing engine 100, the processing requirements of a plurality of montgomery multiplication units within the same time range cannot be satisfied, and only after the processing of the previous montgomery multiplication unit is completed, the processing of the next montgomery multiplication unit can be performed, thereby reducing the computing efficiency of the computing engine.
However, the structure of the conventional computing engine doubles the number of circuits, and the logic operation unit occupies a relatively high amount in the whole circuit, thereby increasing the design and manufacturing costs.
Based on this, an embodiment of the present application provides a computing engine. Specifically, the computing engine comprises at least one advanced operation unit, a state query unit and at least one logic operation unit, wherein the at least one advanced operation unit is connected with the state query unit, and the state query unit is connected with the at least one logic operation unit. The state query unit is used for querying the state of the at least one logic operation unit and obtaining the logic operation unit in an idle state, the logic operation unit in the idle state is used for receiving and processing the data to be processed so as to obtain a data processing result, and the at least one advanced operation unit is also used for receiving the data processing result.
When the high-level operation unit has data to be processed, the computing engine sends the data to be processed to the idle logic operation unit for processing by adding the state query unit, so that the function of flexibly scheduling the data to be processed is realized. Compared with the structure that each advanced operation unit in the traditional calculation engine independently uses the logic operation units, the calculation engine can effectively reduce the number of the logic operation units, realize common and flexible distribution of the logic operation units required by the advanced operation units, thereby reducing the area of the calculation engine, further reducing the cost and being easy to design.
Next, a detailed description of the computing engine according to an embodiment of the present application will be given with reference to the accompanying drawings.
Referring to a schematic diagram of a computing engine shown in fig. 2, the computing engine 200 may include at least one advanced arithmetic unit 201, a state query unit 202, and at least one logical arithmetic unit 203. Specifically, at least one advanced arithmetic unit 201 may be used to acquire data to be processed; the state query unit 202 may be configured to query the state of at least one logic operation unit 203 to obtain a logic operation unit in an idle state; the logic operation unit 203 in the idle state may be configured to receive and process data to be processed, obtain a data processing result, and the at least one advanced operation unit 201 is further configured to receive the data processing result.
In particular, the calculation engine may be used to implement an asymmetric encryption algorithm, i.e. the calculation engine may be used for data processing, thereby obtaining the calculation result of the asymmetric encryption algorithm. The calculation result may be an intermediate result of the asymmetric encryption algorithm, or may be a final result of the asymmetric encryption algorithm. For example, the calculation may be used to generate a key and a signature verification.
In some possible implementations, the at least one advanced arithmetic unit 201 may include: at least one of Montgomery multiplication operation unit, point addition operation unit, multiple point operation unit, point multiplication operation unit and hash algorithm operation unit.
It will be appreciated that complex algorithms may be implemented using the advanced arithmetic unit 201. For example, a Montgomery multiplication unit is an algorithm that accelerates a modular multiplication operation in the process of generating a public key; the point adding operation unit, the multiple point operation unit and the point multiplying operation unit are algorithms required in an elliptic encryption algorithm (ECC); the hash algorithm operation unit is an algorithm for generating a hash value.
Further, referring to fig. 3, a schematic diagram of a logic operation unit is shown.
In some possible implementations, the logic operation unit 203 may include at least one sub-operation unit, and the at least one sub-operation unit may include: at least one of an addition unit, a subtraction unit, a multiplication unit, a modular addition unit, a modular subtraction unit, a modular multiplication unit, and an exclusive or operation unit.
It is understood that the logic operation unit 203 is an operation unit for logic operation, and the logic operation unit 203 can implement various logic operations, thereby implementing a complex algorithm in an advanced operation unit based on the various logic operations.
In the embodiment of the present application, when at least one advanced operation unit 201 obtains data to be processed and data processing by using a logic operation unit 203 is required, the state query unit 202 may perform state query on at least one logic operation unit 203, so that the logic operation unit 203 in an idle state processes the data to be processed.
Specifically, referring to fig. 4, a schematic diagram of a state query unit is shown. The status query unit 202 may include a query module 2021, a feedback module 2022, a data issuing module 2023, and a data uploading module 2024.
The query module 2021 may query the state of the at least one logical operation unit 203. For example, the query module 2021 may query the status of the at least one logical operation unit 203 in a polling manner. Further, the feedback module 2022 may feed back the queried logic operation unit 203 in the idle state to at least one advanced operation unit 201, and communicate with the idle logic operation unit 203, so that the advanced operation unit 201 sends the data to be processed to the idle logic operation unit 203 through the data issuing module 2023. For example, it may be in communication with the logic operation unit 203 in the idle state by means of signal selection.
Further, the logic operation unit 203 in the idle state receives and processes the data to be processed, thereby obtaining a data processing result, and transmits the data processing result to the at least one advanced operation unit 201 through the data uploading module 2024.
In the embodiment of the application, the advanced operation unit does not need to independently use the logic operation unit, and the idle logic operation unit is called to the advanced operation unit through the state query unit, so that the data processing is realized. Therefore, logic operation units required by different high-level operation units in the calculation engine can be shared, so that the circuit area is reduced, and the circuit design is easy.
In some possible implementations, the data processing result may include a plurality of sub-processing results, and the at least one advanced arithmetic unit 201 may output the data processing result after receiving all of the sub-processing results.
It will be appreciated that since the advanced arithmetic unit 201 may be used to implement complex algorithms, the execution of the advanced arithmetic unit 201 may include the execution of multiple arithmetic steps. For example, the advanced arithmetic unit 201 includes 7 steps, and the logic arithmetic unit 203 can sequentially perform data processing for the 7 steps. Further, in the case where the logic operation unit 203 sequentially sends the sub-processing results of the 7 steps to the advanced operation unit 201, when the advanced operation unit 201 receives all the sub-processing results, it indicates that the logic operation unit 203 has completed all the data processing steps, and at this time, the advanced operation unit 201 may output the data processing results.
In the embodiment of the present application, the number of the logic operation units 203 may be set according to actual requirements. For example, if it is found that there are at most two advanced arithmetic units in the same time frame during the actual processing of the asymmetric encryption algorithm using the computing engine, two logical arithmetic units 203 may be provided in the computing engine 200.
Further, with the advancement and development of technology, if there are three advanced computing units in the same time frame, a logic computing unit 203 may be added to the computing engine 200 to meet the requirements.
In the embodiment of the application, the state query unit is added into the computing engine, so that the logic operation unit can be flexibly distributed to the advanced operation units, the computing efficiency is not reduced on the basis of meeting the operation requirement of the computing engine, and the number of the logic operation units is reduced.
The computing engine comprises at least one advanced computing unit, a state query unit and at least one logic computing unit, wherein the at least one advanced computing unit is connected with the state query unit, and the state query unit is connected with the at least one logic computing unit. The state query unit is used for querying the state of the at least one logic operation unit and obtaining the logic operation unit in an idle state, the logic operation unit in the idle state is used for receiving and processing the data to be processed so as to obtain a data processing result, and the at least one advanced operation unit is also used for receiving the data processing result.
When the high-level operation unit has data to be processed, the computing engine sends the data to be processed to the idle logic operation unit for processing by adding the state query unit, so that the function of flexibly scheduling the data to be processed is realized. Compared with the structure that each advanced operation unit in the traditional calculation engine independently uses the logic operation units, the calculation engine can effectively reduce the number of the logic operation units, realize common and flexible distribution of the logic operation units required by the advanced operation units, thereby reducing the area of the calculation engine, further reducing the cost and being easy to design.
Based on the computing engine provided by the embodiment of the application, the embodiment of the application also provides a data processing method corresponding to the computing engine, and the method can be applied to the computing engine.
Referring to a flow chart of a data processing method shown in fig. 5, the method includes:
s501: at least one advanced operation unit acquires data to be processed;
s502: the state inquiry unit inquires the state of at least one logic operation unit to obtain the logic operation unit in an idle state;
s503: the logic operation unit in an idle state receives and processes the data to be processed to obtain a data processing result;
s504: at least one advanced arithmetic unit receives the data processing result.
In some possible implementations, the method further includes:
determining a high-level operation unit corresponding to data to be processed from at least one high-level operation unit;
at least one advanced arithmetic unit acquires data to be processed, including:
and the advanced operation unit corresponding to the data to be processed acquires the data to be processed.
In some possible implementations, the data processing results include a plurality of sub-processing results, the method further comprising:
and outputting a data processing result after at least one advanced operation unit receives all the sub-processing results.
The functions described above herein may be performed, at least in part, by one or more hardware logic components. Referring to the schematic structural diagram of the electronic device 600 for implementing data processing shown in fig. 6, it should be noted that the electronic device shown in fig. 6 is merely an example, and should not impose any limitation on the functions and application scope of the embodiments of the present application.
As shown in fig. 6, the electronic device 600 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 601, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603. In the RAM603, various programs and data required for the operation of the electronic apparatus 600 are also stored. The processing device 601, the ROM 602, and the RAM603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
In general, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, magnetic tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. While fig. 6 shows an electronic device 600 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
The present application also provides a computer-readable storage medium, also referred to as a machine-readable medium. In the context of the present application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable medium of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: at least one advanced operation unit is made to acquire data to be processed; the order state inquiry unit inquires the state of at least one logic operation unit to obtain the logic operation unit in an idle state; and enabling the logic operation unit in the idle state to receive the data to be processed and process the data to be processed to obtain a data processing result.
In particular, according to embodiments of the present application, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the method shown in the flow chart. In such embodiments, the computer program may be downloaded and installed from a network via a communications device, or from a storage device. The above-described functions defined in the method of the embodiment of the present application are performed when the computer program is executed by the processing device.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
While several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in the present application is not limited to the specific combinations of technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the spirit of the disclosure. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.
Claims (10)
1. A computing engine, the computing engine comprising: the system comprises at least one advanced operation unit, a state query unit and at least one logic operation unit, wherein the at least one advanced operation unit is connected with the state query unit, and the state query unit is connected with the at least one logic operation unit;
the at least one advanced operation unit is used for acquiring data to be processed;
the state query unit is used for querying the state of the at least one logic operation unit to obtain the logic operation unit in an idle state;
the logic operation unit in the idle state is used for receiving and processing the data to be processed to obtain a data processing result;
the at least one advanced arithmetic unit is further configured to receive the data processing result.
2. The computing engine of claim 1, wherein the state query unit is further configured to:
feeding back the logic operation unit in the idle state to the at least one advanced operation unit and communicating with the logic operation unit in the idle state;
the at least one advanced arithmetic unit is specifically configured to:
and sending the data to be processed to the logic operation unit in the idle state through the state query unit.
3. The computing engine of claim 1, wherein the data processing results comprise a plurality of sub-processing results, the at least one advanced arithmetic unit further to:
and outputting the data processing result after receiving all the sub-processing results.
4. A computing engine according to any one of claims 1 to 3, wherein the at least one advanced arithmetic unit comprises: at least one of Montgomery multiplication operation unit, point addition operation unit, multiple point operation unit, point multiplication operation unit and hash algorithm operation unit.
5. A computing engine according to any one of claims 1 to 3, wherein the logic operation unit comprises at least one sub-operation unit, the at least one sub-operation unit comprising: at least one of an addition unit, a subtraction unit, a multiplication unit, a modular addition unit, a modular subtraction unit, a modular multiplication unit, and an exclusive or operation unit.
6. A data processing method, the method being applied to a computing engine, the computing engine comprising at least one advanced arithmetic unit, a state query unit, and at least one logical arithmetic unit, the at least one advanced arithmetic unit being connected to the state query unit, the state query unit being connected to the at least one logical arithmetic unit, the method comprising:
the at least one advanced operation unit acquires data to be processed;
the state inquiry unit inquires the state of the at least one logic operation unit to obtain a logic operation unit in an idle state;
the logic operation unit in the idle state receives and processes the data to be processed to obtain a data processing result;
the at least one advanced arithmetic unit receives the data processing result.
7. The method of claim 6, wherein the method further comprises:
determining a high-level operation unit corresponding to the data to be processed from the at least one high-level operation unit;
the at least one advanced arithmetic unit obtains data to be processed, including:
and the advanced operation unit corresponding to the data to be processed acquires the data to be processed.
8. The method of claim 6, wherein the data processing results comprise a plurality of sub-processing results, the method further comprising:
and after the at least one advanced operation unit receives all the sub-processing results, outputting the data processing results.
9. An electronic device comprising a processor and a memory, the memory having instructions stored therein, the processor executing the instructions to cause the electronic device to perform the method of any of claims 6-8.
10. A computer readable storage medium comprising computer readable instructions which, when run on an electronic device, cause the electronic device to perform the method of any of claims 6 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310248275.6A CN115934031B (en) | 2023-03-15 | 2023-03-15 | Computing engine, data processing method, device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310248275.6A CN115934031B (en) | 2023-03-15 | 2023-03-15 | Computing engine, data processing method, device and storage medium |
Publications (2)
| Publication Number | Publication Date |
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| CN115934031A CN115934031A (en) | 2023-04-07 |
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| US10459644B2 (en) * | 2016-10-28 | 2019-10-29 | Western Digital Techologies, Inc. | Non-volatile storage system with integrated compute engine and optimized use of local fast memory |
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