CN115934000B - Timing method and related device of storage system - Google Patents
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Abstract
The application discloses a timing method and a related device of a storage system, and relates to the technical field of storage systems, wherein the timing method comprises the following steps: processing the received timer creation command to obtain a timer node; mounting all timers in the timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array; and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction. The timer node is mounted in the timer activation linked list array, and the timer corresponding to the timer activation linked list array is subjected to overtime check processing based on the interrupt instruction, so that the function of the timer is realized.
Description
Technical Field
The present disclosure relates to the field of storage systems, and in particular, to a timing method, a timing device, a server, and a computer readable storage medium for a storage system.
Background
With the continuous development of storage technology, RAID (Redundant Arrays of Independent Disks, disk array) technology has emerged. Redundant Array of Independent Disks (RAID) is an important technology in storage systems, currently including RAID levels 0, 1, 5, 6, 10, 50, 60, which use stripes, mirroring and parity to ensure data reliability and concurrently process I/O through multiple disk drives in the array to improve the I/O performance of the RAID array. The RAID card organizes a plurality of hard disks connected with the server into one or more RAID arrays according to RAID level, and a user creates one or more volumes with specified capacity on the RAID card for a host to be used as block equipment, so that the RAID card is a board card for realizing the function of organizing the hard disks connected with the server into the RAID arrays according to RAID level.
In the related technology, along with the rapid development of the storage technology, the real-time requirement of the huge data storage center on the read-write data of the hardware storage system is higher and higher, and the real-time performance of the timing function in the existing storage system cannot meet the system requirement.
Therefore, how to improve the real-time performance of the timing function in the storage system, and further improve the real-time performance in the storage system is a major problem for those skilled in the art.
Disclosure of Invention
The purpose of the present application is to provide a timing method, a timing device, a server and a computer readable storage medium of a storage system, so as to improve the real-time performance of a timing function in the storage system.
In order to solve the above technical problems, the present application provides a timing method of a storage system, including:
processing the received timer creation command to obtain a timer node;
mounting all timers in the timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction.
Optionally, processing the received timer creation command to obtain a timer node includes:
receiving the timer creation instruction;
determining a corresponding global idle timer node in a global idle timer node linked list based on the timer creation instruction;
and activating the global idle timer node to obtain the timer node.
Optionally, determining a corresponding global idle timer node in a global idle timer node linked list based on the timer creation instruction includes:
Analyzing the timer creation instruction to obtain command parameters;
and determining a corresponding global idle timer node in the global idle timer node linked list based on the command parameter.
Optionally, activating the global idle timer node to obtain the timer node includes:
and setting a corresponding beat number for the global idle timer node based on the command parameter to obtain the timer node.
Optionally, the process of creating the global idle timer node linked list includes:
when the storage system is powered on, applying for a plurality of global idle timer nodes from the memory;
and linking the plurality of global idle timer nodes to obtain the global idle timer node linked list.
Optionally, linking the plurality of global idle timer nodes to obtain the global idle timer node linked list, including:
and linking the plurality of global idle timer nodes based on the front pointer field and the back pointer field of each global idle timer node to obtain the global idle timer node linked list.
Optionally, mounting timers in all the timer nodes to a timer activation linked list array includes:
And mounting the corresponding timer node to the timer activation linked list array based on the beat number in each timer node.
Optionally, the process of creating the timer activation linked list array includes:
setting a plurality of corresponding beat array elements based on the preset beat number, and forming the beat array;
and mounting the corresponding timer activation linked list to the corresponding element in the beat array.
Optionally, the process of setting the clock beats in the timer activation linked list array includes:
and determining a beat time length based on the real-time demand information and the system performance, and setting the beat time length as the clock beat.
Optionally, performing timeout checking processing on a corresponding timer in the timer activation linked list array based on the interrupt instruction includes:
triggering an interrupt processing function through the interrupt instruction;
and waking up a timer thread through the interrupt processing function, and performing overtime check processing on a corresponding timer in a timer activation linked list array based on the timer thread.
Optionally, triggering an interrupt processing function by the interrupt instruction includes:
receiving the interrupt instruction from a hardware timer module;
Triggering an interrupt processing function through the interrupt instruction.
Optionally, performing timeout checking processing on a corresponding timer in the timer activation linked list array based on the timer thread includes:
judging whether a corresponding timer in the timer activation linked list array is overtime or not through the timer thread;
if yes, the timeout processing function is called back.
Optionally, the determining, by the timer thread, whether the corresponding timer in the timer activation linked list array is overtime includes:
selecting a timer activation linked list of a corresponding element from the timer activation linked list array through the timer thread;
judging whether the corresponding timer in the timer activation linked list is overtime or not.
Optionally, selecting, by the timer thread, a timer activation linked list of a corresponding element from the timer activation linked list array, including:
determining a corresponding timer activation linked list based on a current timer pointer of the timer activation linked list array;
and if the timer activation linked list is not empty, processing the timer activation linked list through the timer thread.
Optionally, the method further comprises:
when the interrupt instruction is received, the current timer pointer points to the next element.
Optionally, the process of creating the timer thread includes:
when the storage system is powered on, the timer thread is created based on a preset priority.
Optionally, when the timer creation command is a periodic command, the method further includes:
and after the timer performs overtime check processing, inserting the timer into the timer activation linked list array.
The present application also provides a timing device of a storage system, including:
the timer node activation module is used for processing the received timer creation command to obtain a timer node;
the timer node mounting module is used for mounting all timers in the timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
and the timer judging module is used for carrying out overtime check processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction.
The application also provides a server comprising:
a memory for storing a computer program;
a processor for implementing the steps of the timing method as described above when executing the computer program.
The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the timing method as described above.
The timing method of the storage system provided by the application comprises the following steps: processing the received timer creation command to obtain a timer node; mounting all timers in the timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array; and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction.
The timer node is mounted in the timer activation linked list array, and the timer corresponding to the timer activation linked list array is subjected to overtime check processing based on the interrupt instruction, so that the function of the timer is realized.
The present application further provides a timing device, a server and a computer readable storage medium of a storage system, which have the above advantages and are not described herein.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1 is a flowchart of a timing method of a memory system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a RAID card according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a bidirectional linked list of global idle timer nodes according to an embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of a doubly linked list according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a structure of a timer activation linked list array according to an embodiment of the present disclosure;
FIG. 6 is a flow chart of another timing method provided by an embodiment of the present application;
FIG. 7 is a schematic diagram of a timing device of a memory system according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a server according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a timing method, a timing device, a server and a computer readable storage medium of a storage system, so as to improve the real-time performance of a timing function in the storage system.
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The timer node is mounted in the timer activation linked list array, and the timer corresponding to the timer activation linked list array is subjected to overtime check processing based on the interrupt instruction, so that the function of the timer is realized, and the interrupt function and the timer are independent and work in parallel, so that the mutual influence is avoided, and the instantaneity and the performance of the timer function are improved.
A timing method of a storage system provided in the present application is described below by way of one embodiment.
Referring to fig. 1, fig. 1 is a flowchart of a timing method of a memory system according to an embodiment of the present application.
In this embodiment, the method may include:
s101, processing a received timer creation command to obtain a timer node;
this step aims at processing the received timer creation command to obtain the timer node. Wherein the timer node is a structure body providing a timing function.
The timer creation command is a command sent by the outside and received by the device, and is mainly used for creating a corresponding timer command. The timer creation command may be a timer creation command sent by the user, a timer creation command received from the network, or a timer creation command generated by the server based on a preset condition.
Further, the step may include:
s1011, receiving a timer creation instruction;
s1012, determining a corresponding global idle timer node in a global idle timer node linked list based on a timer creation instruction;
and S1013, activating the global idle timer node to obtain the timer node.
It can be seen that this alternative is mainly illustrative of how the timer node is acquired. In the alternative scheme, a timer creation instruction is received; determining a corresponding global idle timer node in a global idle timer node linked list based on a timer creation instruction; and activating the global idle timer node to obtain the timer node. That is, in the alternative, the corresponding global idle timer node is directly extracted from the existing global idle timer node linked list, and application is not required from the memory, so that the efficiency of creating the global idle timer node is improved, and the problem that the global idle timer node cannot be created due to the memory problem is avoided.
Further, S1012 in the above alternative may include:
and 2, determining a corresponding global idle timer node in the global idle timer node linked list based on the command parameter.
It can be seen that this alternative is mainly to explain how to determine the corresponding global idle timer node. In the alternative scheme, analyzing a timer creation instruction to obtain command parameters; and determining a corresponding global idle timer node in the global idle timer node linked list based on the command parameter. That is, the appropriate global idle timer node is selected based on the command parameters.
Further, S1013 in the above alternative may include:
and setting a corresponding beat number for the global idle timer node based on the command parameter to obtain the timer node.
It can be seen that this alternative is mainly illustrative of how the timer node is activated. In the alternative scheme, the corresponding beat number is set for the global idle timer node based on the command parameter, and the timer node is obtained. That is, the presence duration to the timer node is determined based on the number of beats.
Further, the process of creating the global idle timer node linked list in the previous alternative may include:
and step 2, linking a plurality of global idle timer nodes to obtain a global idle timer node linked list.
It can be seen that this alternative is mainly to explain how to create a global idle timer node list. In the alternative scheme, when the storage system is powered on, a plurality of global idle timer nodes are applied from a memory; and linking the plurality of global idle timer nodes to obtain a global idle timer node linked list. That is, multiple global idle timer nodes may be applied from memory directly based on a memory allocation module in firmware.
Further, step 2 in the above alternative may include:
and linking a plurality of global idle timer nodes based on the front pointer field and the back pointer field of each global idle timer node to obtain a global idle timer node linked list.
It can be seen that this alternative is mainly described for linking a plurality of global idle timer nodes into a doubly linked list. In the alternative scheme, a plurality of global idle timer nodes are linked based on a front pointer field and a back pointer field of each global idle timer node, so as to obtain a global idle timer node linked list.
S102, mounting timers in all timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
on the basis of S101, the step aims at mounting timers in all timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array.
Further, the step may include:
And mounting the corresponding timer node to the timer activation linked list array based on the beat number in each timer node.
It can be seen that this alternative is mainly to explain how to mount the timer node. In this alternative, the corresponding timer node is mounted to the timer activation linked list array based on the number of beats in each timer node.
Further, in this embodiment, the process of creating the timer activation linked list array may include:
and step 2, mounting the corresponding timer activation linked list to the corresponding element in the beat array.
It can be seen that this alternative is mainly to explain how to create an array of timer activation linked lists. In the alternative scheme, a plurality of corresponding beat array elements are set based on the preset beat number, and a beat array is formed; and mounting the corresponding timer activation linked list to the corresponding element in the beat array. That is, a beat array is constructed first, and then a timer activation linked list is mounted to a corresponding element in the beat array, so that a structure similar to a two-dimensional array is realized. The timer activates the linked list array to integrate the advantages of small memory space occupied by the array, random access of data and high searching speed with the advantages of dynamic addition and deletion and variable size of the linked list.
Further, in this embodiment, the process of setting the clock beats in the timer activation linked list array may include:
and determining the beat time length based on the real-time demand information and the system performance, and setting the beat time length as a clock beat.
That is, the clock tick value is determined by the storage system platform and the user requirements are determined in combination. For example, if the real-time requirement of the user on the RAID card is very high, determining whether to use 1ms as one clock or 5ms as one clock according to the performance of the RAID card system platform, if the performance of the hardware platform of the RAID card system can achieve 1ms as one clock, using 1ms as one clock, otherwise using 5ms as one clock; if the real-time requirement of the user on the RAID card is not high, taking 10ms as a clock beat.
Thus, the timing time length is measured by the number of clock beats, for example, the clock beat is 5ms, and the application program sets the timing time to 3s, then 3s/5 ms=600, i.e., 600 beats.
S103, performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction.
On the basis of S102, this step aims at performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction. That is, it is determined whether the corresponding timer times out based on the interrupt instruction received each time. Wherein, each time an interrupt instruction is received, a beat is obtained. Therefore, by matching with the beat, whether the timer overtakes or not can be quickly determined, and the instantaneity of the timing function is improved.
Further, the step may include:
s1031, triggering an interrupt processing function through an interrupt instruction;
s1032, waking up the timer thread through the interrupt processing function, and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the timer thread.
It can be seen that this alternative is mainly illustrative of how the timeout check can be performed. In the alternative scheme, an interrupt processing function is triggered through an interrupt instruction; and waking up the timer thread through the interrupt processing function, and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the timer thread. Obviously, the process of timeout checking in the alternative scheme is realized through an interrupt processing function and a timer thread, which are independent and do not interfere with each other, so that the timeliness of timeout checking is improved.
Further, S1031 in the above alternative may include:
and step 2, triggering an interrupt processing function through an interrupt instruction.
It can be seen that this alternative is mainly illustrative of how the interrupt handling function is triggered. In the alternative scheme, an interrupt instruction is received from a hardware timer module; the interrupt handling function is triggered by an interrupt instruction. The stability of the interrupt instruction is improved by the hardware timer module.
Further, S1032 in the previous alternative may include:
and step 2, if yes, calling back the timeout processing function.
It can be seen that this alternative is mainly illustrative of how the timeout check can be performed. In the alternative scheme, whether the corresponding timer in the timer activation linked list array is overtime is judged by a timer thread; if yes, the timeout processing function is called back. That is, whether the timer is overtime is judged, if yes, a corresponding function is executed, and the function of the timer is realized.
Further, step 1 in the previous alternative may include:
step 1.1, selecting a timer activation linked list of a corresponding element from a timer activation linked list array through a timer thread;
and 1.2, judging whether a corresponding timer in the timer activation linked list is overtime.
In the alternative scheme, the timer thread selects the timer activation linked list of the corresponding element from the timer activation linked list array; and judging whether the corresponding timer in the timer activation linked list is overtime or not. Therefore, in the alternative, the corresponding timer activation linked list is selected first, and then judgment is performed.
Further, step 1 in the previous alternative may include:
step 1.1, determining a corresponding timer activation linked list based on a current timer pointer of a timer activation linked list array;
and 1.2, judging whether the corresponding timer in the timer activation linked list is overtime or not through a timer thread if the timer activation linked list is not empty.
In the alternative scheme, the corresponding timer activation linked list is determined based on the current timer pointer of the timer activation linked list array; if the timer activation linked list is not empty, judging whether the corresponding timer in the timer activation linked list is overtime or not through a timer thread. That is, the timer activation linked list specified at the current beat number is determined by the current timer pointer.
Further, the method may further include:
when an interrupt instruction is received, the current timer pointer points to the next element.
Further, the process of creating the timer thread in this embodiment may include:
when the storage system is powered up, a timer thread is created based on the preset priority. Wherein the preset priority may be a high priority.
Further, in this embodiment, when the timer creation command is a periodic command, the method may further include:
After the timer performs timeout checking, the timer is inserted into the timer activation linked list array. Periodic timing operations are achieved.
In summary, in this embodiment, by mounting the created timer node to the timer activation linked list array, and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction, the function of the timer is implemented, and since the interrupt function and the timer are independent and work in parallel, the mutual influence is avoided, and the real-time performance and performance of the timer function are improved.
The following further describes a timing method of a storage system according to another specific embodiment.
In this embodiment, a timing method of the storage system provided in the present application will be described by taking a RAID card as an example.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a RAID card according to an embodiment of the present disclosure.
First, the structure of a RAID card in a storage system is introduced, including: timer software logic function module 110, hardware timer module 120, and allocation module 150 in the firmware layer.
The allocation module applies for a plurality of global idle timer nodes from a memory when the RAID card is electrified and initialized, and links the plurality of global idle timer nodes into a global idle timer node bidirectional linked list by utilizing a front pointer field and a back pointer field in the global idle timer nodes.
The timer software logic function module is responsible for taking out timer nodes from the global idle timer node doubly-linked list, when an application program of a user operates a RAID card to create one or more timer nodes, the timer software logic function module takes out a corresponding number of timer nodes from the global idle timer node doubly-linked list and forms the doubly-linked list, and the timer software logic function module maintains a timer activation linked list array, wherein the timer activation linked list array combines the linked list array with the array, and the advantages of small memory space occupation of the array, random access of data, high searching speed and dynamic addition and deletion of the linked list and the advantages of variable size are fused together.
Wherein the hardware timer module triggers a periodic timed interrupt drive.
The firmware layer in the RAID card comprises a driver, a RAID card kernel, a file system, a management monitoring system, a timer software logic function module and the like, wherein the RAID card kernel provides a bottom logic function, and the file system can provide a function of accessing files and a logic unit number LUN (Logical Unit Number, logic unit number). The driver of the firmware layer in the RAID card realizes the code logic function of adapting each peripheral. The processor executes program instructions for processing the host I/O request.
Further, in FIG. 2, disk group 1 (130) forms a RAID array number 1, disk group 2 forms a RAID array number 2, and so on, disk group N forms a RAID array number N. RAID array No. 1, RAID array No. 2. The RAID card controller 140 is responsible for the software processing function in the RAID card, the RAID card controller specially implements the software function, the hardware module executes some algorithms, data management and other functions, so as to implement the separation of soft and hard, the hardware and the software work independently and in parallel, and the timer performance and the function of the RAID card are improved through the design of the soft and hard separation system architecture.
The RAID card timer designed by the embodiment provides single timing and periodic timing functions. The timer is driven by a hardware timer module providing periodic timed interrupts, each timed interrupt being referred to as a clock tick. The clock beat value is determined by the system platform of the RAID card and comprehensively determined by the user requirements. For example, if the real-time requirement of the user on the RAID card is very high, determining whether to use 1ms as one clock or 5ms as one clock according to the performance of the RAID card system platform, if the performance of the hardware platform of the RAID card system can achieve 1ms as one clock, using 1ms as one clock, otherwise using 5ms as one clock; if the real-time requirement of the user on the RAID card is not high, taking 10ms as a clock beat.
The timing time length is measured by the number of clock beats, for example, the clock beat is 5ms, and the application program sets the timing time to 3s, then 3s/5 ms=600. Thus, the logic for the user to set the timing may include:
and 4, finally, setting the created timer value to 600 by the timer software logic function module according to the parameters.
The structure of the timer node is as follows:
typedef struct TIMER_STRUCT
{
uint timer_id;// timer id
char timer name;// timer naming pointer
Active active_timer and/timer internal management structure
struct TIMER_STRUCT
* Pre_pointer,// pointer to previous timer
* Next_pointer;// pointer to subsequent timer
} Timer;
Wherein, timer_id is timer id and timer_name is timer naming pointer. The active_timer is an internal management structure of the timer, and the active_timer is inserted into the timer activation linked list array after the timer is activated. The pre_pointer is a pointer to the previous timer, and the next_pointer is a pointer to the next timer.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a bidirectional linked list of global idle timer nodes according to an embodiment of the present application.
FIG. 3 is a diagram of a global free timer node doubly linked list, which is formed by pre_pointer head and next_pointer back pointers in a plurality of timer nodes.
Furthermore, the active_timer field in the timer node is a most main field and is also a structure body, the active_timer structure body needs to be activated before the timer works, and after the active_timer structure body is activated, the active_timer structure body is put into an appointed array linked list of the timer activation linked list array according to the beat number.
The active_timer structure may be as follows:
typedef struct Timer_Active
{
parameter para_timeout;// timing timeout function Parameter
void (function_timeout) and/or timing timeout processing function
uint remaining_beats;// number of beats remaining timed
uint cycle_ticks;// number of beats of periodic timer
struct Timer_Active
* Pre-active pointer,// pointer to previous active_timer structure
* next active pointer
uint timer_type;// timer type
}Active；
Based on the above description, when the application program of the user applies for one or more timers to the RAID card, the software logic function module will take out the corresponding number of timers from the doubly linked list of the globally idle timer nodes and form a doubly linked list maintained by the timers. The application program of the user creates three timers in the RAID card, and the process of successful extraction and the process of forming a doubly linked list after extraction are shown in figure 4.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a doubly linked list according to an embodiment of the present application.
Indicated at 500 in fig. 4 is a global idle timer node doubly linked list applied by the allocatemodule, and when the user's application program sends a command to create three timers to the RAID card, the software logic function module retrieves the three timer nodes from the head of the global idle cache node linked list. Thus, the doubly linked list of global idle timer nodes after three timer nodes are fetched is shown as 510 in FIG. 4. The timer software logic function module constructs the fetched three timer nodes into a doubly linked list (as shown at 520 in fig. 4).
Further, a TIMER activation linked list array maintained by the TIMER software logic function module is defined as timer_list [ timer_entries ], and the timer_list array has 32 elements.
Thus, macro definition #define timer_entries 32 is used, i.e. timer_entries is equal to 32.
And defining a timer_list [ tx_timer_entries ] and a global variable timer_current_ptr. As can be seen from the above definition, stored in the timer_list [ TX_TIMER_ENTRIES ] is an array of pointers, and the timer_current_ptr is a secondary pointer.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a timer activation linked list array according to an embodiment of the present application.
The timer active linked list array timer_list has 32 elements, from 0-31, each pointing to a linked list and also representing beat counts. 0 represents beat 0,1 represents beat 1..31 represents beat 31, timer_list [0] represents beat 0, and timer_list [31] represents beat 31. For example, as shown in fig. 5, when a plurality of timers are activated, they are mounted on their corresponding doubly linked lists according to their beat numbers.
As can be seen from fig. 5, the timer according to the embodiment of the present invention activates the linked list array to combine the linked list array with the linked list array, and combines the advantages of small memory space occupied by the array, random access of data, and fast searching speed with the advantages of dynamically adding and deleting the linked list and variable size.
Referring to fig. 6, fig. 6 is a flowchart of another timing method according to an embodiment of the present application.
Finally, the timing method that may be implemented in this embodiment may include:
s201, powering up the RAID card, and starting initialization of the platform system.
S202, after initialization of each module is completed, a timer thread with high priority is created.
S203, the RAID card receives a creation timer command issued by the user application program and analyzes the command.
S204, according to the analyzed command parameters, the corresponding timer nodes are taken out from the global idle timer node doubly linked list.
S205, all the activated timers are mounted in a timer activation linked list array.
S206, the hardware timer module triggers periodic timing interrupt, thereby triggering interrupt processing function.
S207, the interrupt processing function wakes up the timer thread.
S208, the timer thread checks whether the timer in the linked list is overtime, and if so, the overtime processing function is called back (the overtime processing function is the function_timeout field in the active_timer structure).
S209, suspending the timer thread after processing is completed, and waiting for the next interrupt.
Wherein the timer activated linked list array timer_list has 32 elements, from 0-31, each element points to a linked list and also represents a beat count. 0 represents beat 0,1 represents beat 1..31 represents beat 31, timer_list [0] represents beat 0, and timer_list [31] represents beat 31.
The timer software logic function of this embodiment maintains a global pointer to timer_current_ptr and points to timer_list [0] when initialized, and when each clock interrupt is sent by the hardware timer module, 1 is added to timer_current_ptr, if 31 is reached, the timer_current_ptr starts from 0 and points to timer_list [0] again. The interrupt handling function determines whether timer_current_ptr is empty, that is, whether the corresponding linked list has an active timer, and if not, wakes up the timer thread to process.
The timer thread acquires an activation timer in the timer_current_ptr linked list, and judges whether the remaining time of the activation timing is 0. If 0, the timeout is indicated, a timeout processing function (function_timeout) process is called (the timeout processing function is the function_timeout field in FIG. 4). If the remaining time of the activation timing is not 0, the method is inserted into the timer_list activation linked list again.
If the timer is a periodic timer, the timer is inserted into the activation linked list again after the timer is overtime. Therefore, the embodiment realizes the single timing and periodic timing functions of the RAID card timer.
Therefore, under the condition of not adding hardware, the technical scheme designed by the embodiment can improve the real-time performance of the read-write data and processing business of the RAID card and increase the core competitiveness of a company in the RAID card market;
The embodiment adopts the design thought of soft and hard separation, the hardware and the software work independently and in parallel, and the timer performance and the function of the RAID card are improved through the design of a soft and hard separation system architecture;
in the embodiment, a timer software logic function module, a newly-added hardware timer module and an allocatemodule are newly added in a RAID card firmware layer, and the single timing and periodic timing functions of the RAID card timer are realized through periodic timing interrupt driving sent by the hardware timer module, so that the instantaneity of read-write data and processing business of the RAID card is improved;
the timer activation linked list array designed by the embodiment combines the linked list with the array for use, and combines the advantages of small memory space occupied by the array, random access of data and high searching speed with the advantages of dynamic addition and deletion and variable size of the linked list;
the embodiment provides a detailed design scheme for improving the performance and the function of the RAID card timer in detail, the design scheme is quite detailed, the service logic is clear, the logic control and the algorithm are simple and clear, and the implementation is easy. By improving the real-time performance of the RAID card, not only the I/O performance of the storage system is improved, but also the data security can be improved.
The following describes a timing device of a storage system according to an embodiment of the present application, and the timing device of the storage system described below and the timing method of the storage system described above may be referred to correspondingly.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a timing device of a memory system according to an embodiment of the present application.
In this embodiment, the apparatus may include:
a timer node activation module 71, configured to process the received timer creation command to obtain a timer node;
a timer node mounting module 72, configured to mount timers in all timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
the timer judging module 73 is configured to perform timeout checking processing on a timer corresponding to the timer activation linked list array based on the interrupt instruction.
Optionally, the process of processing the received timer creation command to obtain the timer node may include:
receiving a timer creation instruction;
determining a corresponding global idle timer node in a global idle timer node linked list based on a timer creation instruction;
and activating the global idle timer node to obtain the timer node.
Optionally, the process of determining the corresponding global idle timer node in the global idle timer node linked list based on the timer creation instruction may include:
Analyzing the timer creation instruction to obtain command parameters;
and determining a corresponding global idle timer node in the global idle timer node linked list based on the command parameter.
Optionally, the process of activating the global idle timer node to obtain the timer node may include:
and setting a corresponding beat number for the global idle timer node based on the command parameter to obtain the timer node.
Optionally, the process of creating the global idle timer node linked list may include:
when the storage system is powered on, applying for a plurality of global idle timer nodes from the memory;
and linking the plurality of global idle timer nodes to obtain a global idle timer node linked list.
Optionally, the process of linking the plurality of global idle timer nodes to obtain the global idle timer node linked list may include:
and linking a plurality of global idle timer nodes based on the front pointer field and the back pointer field of each global idle timer node to obtain a global idle timer node linked list.
Optionally, the process of mounting timers in all timer nodes to the timer activation linked list array may include:
And mounting the corresponding timer node to the timer activation linked list array based on the beat number in each timer node.
Optionally, the process of creating the timer activation linked list array may include:
setting a plurality of corresponding beat array elements based on the preset beat number, and forming a beat array;
and mounting the corresponding timer activation linked list to the corresponding element in the beat array.
Optionally, the process of setting the clock beats in the timer activation linked list array may include:
and determining the beat time length based on the real-time demand information and the system performance, and setting the beat time length as a clock beat.
Optionally, the process of performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction may include:
triggering an interrupt processing function through an interrupt instruction;
and waking up the timer thread through the interrupt processing function, and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the timer thread.
Optionally, the process of triggering the interrupt processing function by the interrupt instruction may include:
receiving an interrupt instruction from a hardware timer module;
the interrupt handling function is triggered by an interrupt instruction.
Optionally, the process of performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the timer thread may include:
judging whether a corresponding timer in the timer activation linked list array is overtime or not through a timer thread;
if yes, the timeout processing function is called back.
Optionally, the process of determining, by the timer thread, whether the corresponding timer in the timer activation linked list array has timed out may include:
selecting a timer activation linked list of a corresponding element from the timer activation linked list array through a timer thread;
and judging whether the corresponding timer in the timer activation linked list is overtime or not.
Optionally, the process of selecting, by the timer thread, the timer activation linked list of the corresponding element from the timer activation linked list array may include:
determining a corresponding timer activation linked list based on a current timer pointer of the timer activation linked list array;
and if the timer activation linked list is not empty, processing the timer activation linked list through a timer thread.
Optionally, the method may further include:
when an interrupt instruction is received, the current timer pointer points to the next element.
Optionally, the process of creating the timer thread may include:
When the storage system is powered up, a timer thread is created based on the preset priority.
Optionally, when the timer creation command is a periodic command, the method may further include:
after the timer performs timeout checking, the timer is inserted into the timer activation linked list array.
According to the embodiment, the built timer node is mounted in the timer activation linked list array, and the timer corresponding to the timer activation linked list array is subjected to overtime check processing based on the interrupt instruction, so that the function of the timer is realized, and the interrupt function and the timer are independent and work in parallel, so that the mutual influence is avoided, and the instantaneity and the performance of the timer function are improved.
The present application further provides a server, please refer to fig. 8, fig. 8 is a schematic structural diagram of a server provided in an embodiment of the present application, and the server may include:
a memory for storing a computer program;
a processor for implementing the steps of the timing method of any one of the storage systems described above when executing the computer program.
As shown in fig. 8, which is a schematic diagram of a composition structure of a server, the server may include: a processor 10, a memory 11, a communication interface 12 and a communication bus 13. The processor 10, the memory 11 and the communication interface 12 all complete communication with each other through a communication bus 13.
In the present embodiment, the processor 10 may be a central processing unit (Central Processing Unit, CPU), an asic, a dsp, a field programmable gate array, or other programmable logic device, etc.
The memory 11 is used for storing one or more programs, and the programs may include program codes, where the program codes include computer operation instructions, and in this embodiment, at least the programs for implementing the following functions are stored in the memory 11:
processing the received timer creation command to obtain a timer node;
mounting all timers in the timer nodes to a timer activation linked list array; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
and performing timeout checking processing on the corresponding timer in the timer activation linked list array based on the interrupt instruction.
In one possible implementation, the memory 11 may include a storage program area and a storage data area, where the storage program area may store an operating system, and at least one application program required for functions, etc.; the storage data area may store data created during use.
In addition, the memory 11 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device or other volatile solid-state storage device.
The communication interface 12 may be an interface of a communication module for interfacing with other devices or systems.
Of course, it should be noted that the structure shown in fig. 8 does not limit the server in the embodiment of the present application, and the server may include more or fewer components than those shown in fig. 8 or may combine some components in practical applications.
The present application also provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor, performs the steps of a timing method of any one of the storage systems described above.
The computer readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
For the description of the computer-readable storage medium provided in the present application, reference is made to the above method embodiments, and the description is omitted herein.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above describes in detail a timing method, a timing device, a server and a computer readable storage medium of a storage system provided in the present application. Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
Claims (18)
1. A method of timing a storage system, comprising:
receiving a timer creation instruction;
determining a corresponding global idle timer node based on the timer creation instruction;
activating the global idle timer node to obtain the timer node;
mounting the corresponding timer nodes to a timer activation linked list array based on the beat number in each timer node; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
Triggering an interrupt processing function through an interrupt instruction, waking a timer thread through the interrupt processing function, and performing timeout checking processing on a corresponding timer in a timer activation linked list array based on the timer thread so as to judge whether the corresponding timer is overtime or not when the interrupt instruction is received each time; wherein, each time the interrupt instruction is received, a beat is obtained.
2. The timing method of claim 1, wherein determining a corresponding global idle timer node based on the timer creation instruction comprises:
and determining a corresponding global idle timer node in a global idle timer node linked list based on the timer creation instruction.
3. The timing method of claim 2, wherein determining a corresponding global idle timer node in a global idle timer node linked list based on the timer creation instruction comprises:
analyzing the timer creation instruction to obtain command parameters;
and determining a corresponding global idle timer node in the global idle timer node linked list based on the command parameter.
4. A timing method in accordance with claim 3, characterized by activating said global idle timer node to obtain said timer node, comprising:
And setting a corresponding beat number for the global idle timer node based on the command parameter to obtain the timer node.
5. The timing method of claim 2, wherein the process of creating the global idle timer node list comprises:
when the storage system is powered on, applying for a plurality of global idle timer nodes from the memory;
and linking the plurality of global idle timer nodes to obtain the global idle timer node linked list.
6. The timing method of claim 5, wherein linking the plurality of global idle timer nodes to obtain the global idle timer node linked list comprises:
and linking the plurality of global idle timer nodes based on the front pointer field and the back pointer field of each global idle timer node to obtain the global idle timer node linked list.
7. The timing method of claim 1, wherein creating the timer activation linked list array comprises:
setting a plurality of corresponding beat array elements based on the preset beat number, and forming the beat array;
and mounting the corresponding timer activation linked list to the corresponding element in the beat array.
8. The timing method of claim 7, wherein the process of setting the clock ticks in the timer activation linked list array comprises:
and determining a beat time length based on the real-time demand information and the system performance, and setting the beat time length as the clock beat.
9. A timing method in accordance with claim 1, wherein triggering an interrupt handling function by said interrupt instruction comprises:
receiving the interrupt instruction from a hardware timer module;
triggering an interrupt processing function through the interrupt instruction.
10. The timing method of claim 1, wherein performing timeout checking processing on a corresponding timer in the timer activation linked list array based on the timer thread comprises:
judging whether a corresponding timer in the timer activation linked list array is overtime or not through the timer thread;
if yes, the timeout processing function is called back.
11. The timing method of claim 10, wherein determining, by the timer thread, whether a corresponding timer in the timer activation linked list array has timed out comprises:
selecting a timer activation linked list of a corresponding element from the timer activation linked list array through the timer thread;
Judging whether the corresponding timer in the timer activation linked list is overtime or not.
12. The timing method of claim 10, wherein determining, by the timer thread, whether a corresponding timer in the timer activation linked list array has timed out comprises:
determining a corresponding timer activation linked list based on a current timer pointer of the timer activation linked list array;
and if the timer activation linked list is not empty, judging whether the corresponding timer in the timer activation linked list is overtime or not through the timer thread.
13. The timing method as recited in claim 12, further comprising:
when the interrupt instruction is received, the current timer pointer points to the next element.
14. The timing method of claim 1, wherein creating the timer thread comprises:
when the storage system is powered on, the timer thread is created based on a preset priority.
15. The timing method of claim 1, wherein when the timer creation command is a periodic command, further comprising:
and after the timer performs overtime check processing, inserting the timer into the timer activation linked list array.
16. A timing device for a memory system, comprising:
the timer node activation module is used for receiving a timer creation instruction, determining a corresponding global idle timer node based on the timer creation instruction, and activating the global idle timer node to obtain the timer node;
the timer node mounting module is used for mounting the corresponding timer nodes to a timer activation linked list array based on the beat number in each timer node; the timer activation linked list array comprises a beat array and a plurality of timer activation linked lists mounted with corresponding elements in the beat array;
the timer judging module is used for triggering an interrupt processing function through an interrupt instruction, waking up a timer thread through the interrupt processing function, and performing overtime check processing on a corresponding timer in a timer activation linked list array based on the timer thread so as to judge whether the corresponding timer overtakes or not when the interrupt instruction is received each time; wherein, each time the interrupt instruction is received, a beat is obtained.
17. A server, comprising:
A memory for storing a computer program;
processor for implementing the steps of the timing method according to any of claims 1 to 15 when executing said computer program.
18. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the timing method according to any of claims 1 to 15.
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| CN101477386B (en) * | 2009-01-12 | 2011-03-16 | 杭州华三通信技术有限公司 | Timer implementing method and apparatus |
| CN102478878A (en) * | 2010-11-23 | 2012-05-30 | 天津中兴软件有限责任公司 | Timing method |
| CN104035786B (en) * | 2014-07-01 | 2017-11-24 | 上海斐讯数据通信技术有限公司 | The optimization method and system of a kind of software timer |
| CN105302739A (en) * | 2014-07-21 | 2016-02-03 | 深圳市中兴微电子技术有限公司 | Memory management method and device |
| CN107864694B (en) * | 2016-07-21 | 2020-11-03 | 百度时代网络技术（北京）有限公司 | System and method for managing data flow of processing nodes in an unmanned vehicle |
| CN106406997B (en) * | 2016-09-20 | 2020-03-06 | 新华三技术有限公司 | Timer scheduling method and device |
| CN108845872B (en) * | 2018-06-21 | 2021-02-02 | 武汉虹信科技发展有限责任公司 | Method for implementing software timer for embedded system |
| CN109039746B (en) * | 2018-08-07 | 2022-02-25 | 新华三技术有限公司 | Method for detecting bidirectional forwarding path and detecting session state and processor |
| CN109274546B (en) * | 2018-08-07 | 2020-08-14 | 新华三技术有限公司 | Timer scheduling method and device |
| CN113992588B (en) * | 2021-10-21 | 2024-02-09 | 浪潮电子信息产业股份有限公司 | Data transmission method, device, electronic equipment and readable storage medium |
| CN115576501B (en) * | 2022-12-06 | 2023-03-10 | 苏州浪潮智能科技有限公司 | Node updating method, system and related device of RAID card |
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