CN115904714A

CN115904714A - Memory allocation system and server

Info

Publication number: CN115904714A
Application number: CN202211448171.1A
Authority: CN
Inventors: 梁坤
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-11-18
Filing date: 2022-11-18
Publication date: 2023-04-04

Abstract

The invention relates to a memory allocation system and a server. The system comprises: the system comprises a mainboard comprising a substrate management controller, a complex programmable logic device and a plurality of central processing units, wherein the substrate management controller is used for monitoring the memory demand state of each central processing unit; the system comprises a CXL protocol conversion chip and a conversion board used for inserting a plurality of DIMM slots of a memory, wherein the DIMM slots are respectively and correspondingly connected with a plurality of CXL output pins of the CXL protocol conversion chip; the first connecting assembly is used for connecting PCIE pins of each central processing unit to a plurality of PCIE input pins of the CXL protocol conversion chip; the second connecting assembly is used for connecting the substrate management controller and the complex programmable logic device to a control pin of the CXL protocol conversion chip so as to adjust the memory of each central processing unit based on the memory requirement state. The scheme of the invention pools the memory, increases the memory capacity and realizes the dynamic adjustment of the memory of each central processing unit.

Description

Memory allocation system and server

Technical Field

The present invention relates to hardware circuit designs, and more particularly, to a memory allocation system and a server.

Background

The Gen-Z alliance has made a new architecture that addresses some of the problems in memory and computer interconnection. The GEN-Z proposal is accompanied with the construction of a data center, but with the development of the whole computer architecture, the architecture generates great disadvantages. Along with the development of the process, the requirements of the information transmission rate, the power consumption of the computing nodes and the storage specification enable the nodes of the whole data center to tend to be pooled and separated, and the layout of storage, a memory and a processor in one box is broken. The GEN-Z will be similar to a connector once they are separated into different boxes for heat dissipation or other reasons, so its design disadvantage will be against the development of servers.

For this purpose, intel proposed a new architecture for memory pooling-the CXL (Compute Express Link) protocol at 2019 and attracted important members of the former GEN-Z alliance, e.g., the CXL alliance. It is worth noting that several vendors like AMD and ampere have also joined this alliance, and thus the CXL protocol will be one direction in the development of the server industry. With the development of cloud computing applications, informatization gradually covers various fields of society. People's daily life and daily life are more and more communicated through the network, and the network data volume is also increasing continuously. The memory of the server also presents a number of challenges, and a data center is composed of a large number of servers. Dynamic Random Access Memory (DRAM) represents a significant cost per data center, reaching even 50% from microsoft corporation. Servers are not homogenous and workloads are dynamic, and they are constantly changing and improving.

In the existing scheme, a MEMORY link is directly connected to a Central Processing Unit (CPU), DDR5 is currently used, and when the MEMORY in a MEMORY pool is insufficient, DDR5 is configured from 1SPC (SLOT PER CHANNEL) to 2SPC or even 3SPC, or a DDR5 MEMORY bank with a larger MEMORY capacity is configured. Or when the memory cannot be further expanded, data is preferentially exchanged in the server so as to make up more memory space for use, so that a plurality of chip manufacturers increase channels for interconnecting the CPUs and channels capable of being directly connected with the DDR5 in the next generation of the CPUs. Besides, how much DIMM (Dual-Inline-Memory-Modules) is mounted will seriously affect the rate of information transmission and data processing, and the uplink and downlink are also fixed values and cannot be supplied as required.

Referring to fig. 1A, the last generation platform EGS of Intel, each CPU supports 8DIMM CHANNELs, the UPI of the interconnection of the two CPUs is 4X24, and the maximum capacity of the memory pool of the two-way server (1 SPC) is 4096GB (4T). Under the design of fig. 1A, in addition to using the memory bank mounted on the processor itself, in some cases, CPU0 and CPU1 may also call each other's memory resource through UPI. However, the information transfer rate drops a lot in the design of fig. 1A, which is unacceptable for current cloud service vendors. Referring to fig. 1B, in the Intel present-generation platform BHS, each CPU supports 12DIMM CHANNELs, the UPI of interconnection between two CPUs is 6X24, the maximum capacity of the memory pools of the two servers (1 SPC) is 6144GB (6T), the number of CHANNELs on which the respective CPUs can mount memory banks is simply increased, the memory capacity is increased, but the problems of power consumption and the like also occur, and higher requirements are required for heat dissipation, structure, layout and wiring. With the further development of artificial intelligence and cloud, the limitation and the increase of the design of fig. 1B still needs a new architecture. However, the design of fig. 1A and 1B suffers from the following disadvantages: (1) The improved process plus channel can reach the peak as the process matures more and cannot be further optimized. (2) The smaller the process, the more cores (cores) are stacked, and the heat dissipation requirements are not easily met.

Referring to FIG. 1C, DDR5 supports PER CHANNEL 2-3 DIMMs plugged, but this creates other disadvantages: for example, transmission rate is theoretically reduced by about 33%, and such 3SPC is only one conceptual architecture proposed in the design specification (design guide) of processor manufacturers. However, the design of FIG. 1C suffers from the following drawbacks: and (1) the layout is difficult, and the current 4U chassis is not easy to meet. (2) Layout engineers have difficulty in routing, design difficulty is too great, 2SPC is feasible, and 3SPC is too low. (3) From 1SPC to 2SPC, the operating rate of DDR is reduced from 4800 5600MT/s at 1SPC to 4400MT/s, and the delay of transmission is increased by several tens of nanoseconds, which is not preferable for commercial users such as the cloud.

The existing CPU memory allocation mode can be analyzed by combining the contents, and the following defects exist: first, the existing design is difficult to meet the memory requirements of the whole cloud architecture, server ecosystem, and data center. Second, even if the memory capacity requirement is met, the required cost is too high, the user buys a product function order which is not required by the user, and the universality is poor. Thirdly, the memory pool cannot dynamically optimize and supply the memory along with the change of the system load of the server, and the flexibility is poor.

Disclosure of Invention

In view of the above, the present invention provides a memory allocation system and a server, which aims to solve the problems of the existing CPU memory allocation.

According to a first aspect of the present invention, there is provided a memory allocation system, comprising:

the system comprises a mainboard, a plurality of processors and a plurality of communication interfaces, wherein the mainboard comprises a substrate management controller, a complex programmable logic device and a plurality of central processing units with PCIE pins, and the substrate management controller is used for monitoring the memory demand state of each central processing unit;

the conversion board comprises a CXL protocol conversion chip and a plurality of DIMM slots for inserting memories, and the DIMM slots are respectively and correspondingly connected with a plurality of CXL output pins of the CXL protocol conversion chip;

a first connection component configured to connect each central processing unit PCIE pin to a plurality of PCIE input pins of the CXL protocol conversion chip;

and the second connecting component is used for connecting the substrate management controller and the complex programmable logic device to a control pin of the CXL protocol conversion chip so as to enable the substrate management controller and the complex programmable logic device to adjust the memory allocated to each central processing unit based on the memory requirement state.

In some embodiments, the motherboard includes a first central processor and a second central processor interconnected by a UPI bus.

In some embodiments, the first connection assembly includes a first Slim line interface disposed on the main board and a second Slim line interface disposed on the conversion board, and the first Slim line interface and the second Slim line interface are connected by a cable;

PCIE pins of the first central processing unit and the second central processing unit are both connected to the first Slimline interface, and a PE 0X 16 pin of the CXL protocol conversion chip is connected with the second Slimline interface.

In some embodiments, the second connection assembly includes a third Slimine interface disposed on the main board and a fourth Slimine interface disposed on the conversion board, the third Slimine interface and the fourth Slimine interface are connected by a cable;

the substrate management controller and the complex programmable logic device are connected with the third Slimline interface, and a UART pin, a PERST pin and a GPIO pin of the CXL protocol conversion chip are connected with the fourth Slimline interface.

In some embodiments, the second connection component further includes a data selector disposed on the motherboard, two input and output paths of the data selector are respectively connected to the baseboard management controller and the complex programmable logic controller, and an output of the data selector is connected to the fourth slim interface.

In some embodiments, the data selector is configured to switch PCIE resources input to the conversion board.

In some embodiments, the data selector is further configured to:

and when one of the first central processing unit and the second central processing unit has an urgent memory, the PCIE resource of the central processing unit with the urgent memory is used as the only input of the CXL protocol conversion chip.

In some embodiments, the number of the conversion boards is multiple, and the connection modes of the conversion boards and the main board are the same.

In some embodiments, the central processor is on board the X86 architecture or the ARM architecture.

According to a second aspect of the present invention, there is also provided a server, which includes the memory allocation system described above.

The memory allocation system and the server at least have the following beneficial technical effects: the memory is pooled, the DRAM capacity of the memory is increased, the memory of each central processing unit is dynamically adjusted, the ratio of system cores is optimized, the capacity of processing storage and computing resources is improved, the memory density on a single system is improved, and the cost of the memory resources in a unit system is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.

FIG. 1A is a diagram illustrating memory allocation in a conventional EGS platform;

FIG. 1B is a schematic diagram of memory allocation of a conventional BHS platform;

FIG. 1C is a diagram of a conventional DDR5 support with multiple DIMM plugs;

fig. 2 is a schematic structural diagram of a memory allocation system according to an embodiment of the present invention;

fig. 3A is a schematic overall structure diagram of another memory allocation system according to an embodiment of the present invention;

FIG. 3B is a schematic diagram of a circuit connection on a side of the motherboard shown in FIG. 3A;

FIG. 3C is a schematic diagram of the circuit connection on one side of the transfer plate in FIG. 3A;

fig. 4 is a schematic diagram illustrating an overall structure of a memory allocation system including two converter plates according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, merely for convenience of description and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. Furthermore, the terms "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In some embodiments, referring to fig. 2, the present invention provides a memory allocation system, which specifically includes the following structures:

the motherboard 100 (i.e., main Board, abbreviated as MB), the motherboard 100 includes a baseboard management controller 110 (i.e., BMC), a complex programmable logic device 120 (i.e., CPLD), and a plurality of central processing units having PCIE pins, and the baseboard management controller 110 is configured to monitor a memory requirement state of each central processing unit;

a conversion BOARD 200 (i.e., SWITCH BOARD), wherein the conversion BOARD 200 includes a CXL protocol conversion chip 210 (i.e., CXL SWITCH) and a plurality of DIMM SLOTs 220 (i.e., DIMM SLOT) for inserting a memory, and the DIMM SLOTs 220 are respectively connected to a plurality of CXL output pins of the CXL protocol conversion chip 210;

a first connection component 300, the first connection component 300 being configured to connect each central processor PCIE pin to a plurality of PCIE input pins of the CXL protocol conversion chip 210;

a second connection component 400, where the second connection component 400 is configured to connect the baseboard management controller 110 and the complex programmable logic device 120 to a control pin of the CXL protocol conversion chip 210, so that the baseboard management controller 110 and the complex programmable logic device 120 adjust the memory allocated to each central processing unit based on the memory requirement status.

The memory allocation system at least has the following beneficial technical effects: the memory is pooled, the DRAM capacity of the memory is increased, the memory of each central processing unit is dynamically adjusted, the ratio of system cores is optimized, the capacity of processing storage and computing resources is improved, the memory density on a single system is improved, and the cost of the memory resources in a unit system is reduced.

In some embodiments, the motherboard 100 includes a first central processing unit 130 (i.e., CPU 0) and a second central processing unit 140 (i.e., CPU 1) thereon, the first central processing unit 130 and the second central processing unit 140 being interconnected via a UPI bus.

In some embodiments, please refer to fig. 3A to 3C, the first connecting assembly 300 includes a first slim line interface Slimline _1 disposed on the main board 100 and a second slim line interface Slimline _2 disposed on the conversion board 200, and the first slim line interface Slimline _1 and the second slim line interface Slimline _2 are connected by a cable;

PCIE pins of the first central processing unit 130 and the second central processing unit 140 are both connected to the first slim interface Slimline _1, and PE 0X 16 pin of the CXL protocol conversion chip 210 is connected to the second slim interface Slimline _ 2.

In some embodiments, please refer to fig. 3A to 3C, the second connecting assembly 400 includes a third slim line interface Slimline _3 disposed on the main board 100 and a fourth slim line interface Slimline _4 disposed on the conversion board 200, and the third slim line interface Slimline _3 and the fourth slim line interface Slimline _4 are connected by a cable;

the baseboard management controller 110 and the complex programmable logic device 120 are both connected to the third slim interface slim line _3, and the UART pin, the PERST pin, and the GPIO pin of the CXL protocol conversion chip 210 are all connected to the fourth slim interface slim line _4.

In some embodiments, as shown in fig. 3A to fig. 3C, the second connecting assembly 400 further includes a data selector SIGNAL MUX disposed on the motherboard 100, two input and output of the data selector SIGNAL MUX are respectively connected to the bmc 110 and the plc, and an output of the data selector SIGNAL MUX is connected to the fourth slim interface Slimline _4.

In some embodiments, the data selector SIGNAL MUX is configured to switch PCIE resources input to the conversion board 200.

In some embodiments, the data selector SIGNAL MUX configuration is further configured to: in response to a memory urgency of one of the first central processing unit 130 and the second central processing unit 140, the PCIE resource of the central processing unit having the memory urgency is used as the only input of the CXL protocol conversion chip 210.

In some embodiments, referring to fig. 4, the number of the conversion boards 200 is multiple, and the connection manner of the conversion boards 200 and the main board 100 is the same.

In another embodiment, to facilitate understanding of the solution of the present invention, the memory adjustment system of the present invention is described in detail below with reference to the working principle, and the concept of pooling memory resources is adopted to implement dynamic allocation to solve the excessive DRAM requirements of users in order to avoid over-configuring the server. Therefore, the CXL SWITCH chip using the CXL protocol can not only realize memory expansion, but also change the mounted memory resources of each processor according to the requirements of the system, really pool the memory, dynamically allocate the memory resources in the pool according to the requirements of the system, and communicate the memory pool through the CXL protocol.

Wherein CXL2.0 is defined on a PCIe5.0 basis, allowing the alternate protocol to use the PCIe5.0 characteristics of the physical PCIe layer. When the CXL accelerator or the expansion card and the PCIE equipment are simultaneously inserted into the host port, the rate negotiation of the PCIE protocol 1.0 is prioritized, and after the CXL is confirmed to be supported by the two parties, the CXL interconnection protocol is activated. By using the CXL SWITCH, a PCIE interface is converted into a DDR5 interface in a physical form, and the interconnection and the expansion of the PCIE are compatible, so that the flexibility and the expandability in memory resources and transmission are greatly improved.

As shown in fig. 2, according to Intel's current latest platform design, it supports the CXL2.0 protocol. Placing a CXL resource (PCIE 5.0 in physical form) connector MCIO at the end of a main BOARD, routing other signals including (SMB, PRSNT, 100M _CLKDP \ DN, and the like) to MISC CON, connecting all the signals to a SWITCH BOARD through a cable, routing to a SWITCH IC through on-BOARD routing, and connecting the corresponding signals to a corresponding DIMM SLOT after conversion. In fact, in a two-way or even multi-way system, the management signals and the selection signals can be output from the CPLD or BMC, and these logic control signals are sent to the CXL SWITCH chip by the MISC CON, when the workload of the CPU0 is too large and the memory requirement is increased, the memory resources in the memory pool are connected to the CPU0, and when the workload of the CPU1 and the memory requirement are increased, the same processing can be performed, and only the memory resource allocation strategy converted by the memory CXL needs to be written in the EEPROM storing the BIOS CODE.

For clarity of explanation, the system implementation is described with reference to fig. 3B and 3C, and the specific structure of the motherboard and the conversion will be described in detail below:

the design of the mainboard MB end is still the current mainstream design framework of the server mainboard MB end, and the design framework comprises two CPUs, a BMC, a CPLD and DIMMs, only a little change is made outside the two parts, logic control signals from the BMC and the CPLD to the SWITCH BOARD are added, and the MUX is added in the middle of some logic control signals and is used for switching PCIE resources transmitted to the SWITCH BOARD, when the memory of the CPU0 is urgent, the PCIE resources of the CPU0 are used as the input of a CXL SWITCH chip on the SWITCH BORAD, and when the memory of the CPU1 is urgent, the PCIE resources of the CPU1 are used as the input of the CXL SWITCH chip on the SWITCH BORAD, so that the dynamic allocation of the memory of a memory pool can be realized.

The design of the conversion plate is as follows: slim _4: and the main board MB is provided with a connector for the logic control signal sent by cable wiring routing. Slimline _2: and the mainboard MB is provided with a connector for PCIE signals sent by cable wiring routing. I2C: the communication signals, PCA9548 connected to the SWITCH BOARD, will convert one set of I2 Cs into 8 sets of I2 Cs for accessing devices, such as VR information, CXL SWITCH firmware information, CLOCK GENERATOR information, etc. UART: the CXL SWITCH chip is used for transmitting the interface of work LOG, changes USB HUB through the UART, and the performance reaches mainboard MB, transmits mainboard MB end to through USB 2.0's agreement, prints the LOG through the USB connector. PERST: and resetting the PCIE transmitted through the slim _ 2. GPIO: some configuration pin pins of the CXL SWITCH chip can control the CXL SWITCH to work in different modes, and need to be implemented by matching with special firmware. RESET: the pin used for resetting the whole CXL SWITCH chip is externally connected with a reset button. SYS _ REF _ CLK: the reference clock of the system. DIMM SLOT: memory slot of standard DDR5 interface. CLOCK GENERATOR: a device that generates 100M clocks.

The dynamic memory allocation of the workflow or memory pool of the whole system is realized by adopting the following steps:

step one, AUX power of the conversion BOARD SWITCH BOARD and AUX power of the MAIN BOARD MB are connected together, and MAIN power is also connected together. When the PWRGD on the SWITCH BOARD is sent to the main BOARD MB, the CXL SWITCH chip starts to convert, and the PCIE resource is sent to the SWITCH BOARD, converted into the CXL resource, and converted into the memory of the memory pool, and if the default state is too low, these memories will be mounted on the LEGACY-CPU, that is, on the CPU 0. The memory resources of two DIMMs, namely CXL link bandwidth x8 and capacity 512GB, can be converted through the current default GPIO configuration, and the maximum bandwidth reaches 32GB/s based on DDR5 design.

And step two, writing a strategy of converting PCIE into CXL resource in advance in an EEPROM of a BMC, monitoring and managing the whole system by the BMC, specifically realizing the communication modes of I2C and I3C, telling the BMC when the memory resource of the system is insufficient, sending a control logic signal by the BMC to control a MUX to control an input source of a CXL SWITCH chip, and thus mounting the memory under a NON-LEGACY CPU, namely the CPU1. Therefore, the expansion and dynamic allocation of the memory resources in the system memory pool can be realized.

And step three, when the capacities of the two DIMMs cannot meet the use requirement of the system, the I2C informs the BMC, and the BMC controls the high-low level of the GPIO of the CXL SWITCH chip through an I2C return instruction so as to control the CXL SWICCH working mode. The CXL signal is expanded to 4DIMM SLOT to meet the memory requirement of the system, adaptation on firmware is needed, and firmware for port control and uplink and downlink speed needs to be well manufactured in the mounted EEPROM. When the memory resource of the CPU1 is insufficient, the last step is repeated. Therefore, the expansion and dynamic allocation of the memory resources in the system memory pool can be further realized.

Step four, certainly, the extension of the CXL bootd is not the wireless extension of the memory, and other problems will occur after the extension is performed to a certain number, and when the number exceeds a certain number, the bandwidth of the CXL cannot meet the requirement that the CXL extends the bandwidth of more DIMM ports, and the problem that the uplink and downlink rates do not meet the DDR5 transmission rate follows, which is not in accordance with the purpose and application scenario of system design. At present, the number of PCIE ports is increased in an inter EGS platform and in the following, so resources are further increased, more PCIE can be converted into CXL resources, and the system design shown in fig. 4 can be adopted to implement expansion by referring to the following standards:

standard one, more PCIE signals at the MB end of the main BOARD can be connected to the SWITCH BOARD for conversion by using a larger slim line.

And in the second standard, external connectors of other PCIE PORTs are added at the MB end of the mainboard, and more switching BOARDs are connected through cable.

And thirdly, when a plurality of SWITCH BOARDs are used, the MUX is also used at the MB end of the main BOARD to control the input of the CXL SWITCH chip, so that the expansion and dynamic allocation of resources in the memory pool can be realized.

The memory adjustment system has the following beneficial effects:

firstly, the layout of only placing DIMM resources at the MB end of a mainboard on the traditional server architecture is changed, the DIMM resources are placed on a small board through a cable connection small board, the layout at the MB end of the mainboard is optimized, and the space structure in close sessions is optimized.

Secondly, PCIE resources are converted into CXL resources by using a CXL protocol, and the CXL resources are converted into DIMM memory resources meeting the JDEC protocol standard, so that the capacity of a memory pool is enlarged, the traditional scheme that PCIE is converted into RSSD for storage is changed, the data processing and information exchange rate of the RSSD and a processor is 300ms, and the DIMM resources converted by the CXL protocol improve the rate to dozens of microseconds, so that four orders of magnitude are improved.

Thirdly, changes are made on a hardware link and a firmware, the logical control of the MUX and the CPLD is used on the hardware link, so that the logical signal link of the process control of the memory resource conversion is completed, and corresponding conversion strategies are made in advance in the EEPROM of the CXL SWITCH chip and the BMC in combination with the adaptation made on the firmware, so that closed-loop feedback is formed in the application process of the server system, and dynamic allocation of the memory resources in the memory pool is realized.

Fourthly, the expansion of the memory resources of the whole system is controllable, the memory is converted according to the system requirements, a plurality of designs are reserved, and when the system memory requirements are not large, SLIMLINE can be converted into standard SLOT of PCIE X16 through a customized cable (patch card) and is used for connecting PCIE equipment such as a network card and the like, so that the resource utilization rate of the whole system is improved.

Fifth, there is a significant cost reduction, not only in the ratio of DRAM to core, but also in the production and manufacturing costs, including the cost reduction of different plates across the BOARD (MB using ultra low, SWITCH BOARD using top low).

According to another aspect of the present invention, there is also provided a server, including the memory allocation system described above.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims

1. A memory allocation system, the system comprising:

the system comprises a mainboard and a plurality of data processing units, wherein the mainboard comprises a baseboard management controller, a complex programmable logic device and a plurality of central processing units with PCIE pins, and the baseboard management controller is used for monitoring the memory demand state of each central processing unit;

the conversion board comprises a CXL protocol conversion chip and a plurality of DIMM slots for inserting memories, and the DIMM slots are correspondingly connected with a plurality of CXL output pins of the CXL protocol conversion chip respectively;

2. The memory allocation system of claim 1, wherein the motherboard comprises a first central processing unit and a second central processing unit, the first central processing unit and the second central processing unit interconnected via a UPI bus.

3. The memory allocation system of claim 2, wherein said first connection assembly comprises a first Slmline interface disposed on said main board and a second Slmline interface disposed on said converter board, said first Slmline interface and said second Slmline interface being connected by a cable;

the PCIE pin of the first central processing unit and the PCIE pin of the second central processing unit are both connected to the first Slimline interface, and the PE 0X 16 pin of the CXL protocol conversion chip is connected to the second Slimline interface.

4. The memory allocation system of claim 3, wherein the second connection assembly comprises a third Slim line interface disposed on the main board and a fourth Slim line interface disposed on the converter board, the third Slim line interface and the fourth Slim line interface being connected by a cable;

the baseboard management controller and the complex programmable logic device are connected with the third Slim line interface, and a UART pin, a PERST pin and a GPIO pin of the CXL protocol conversion chip are connected with the fourth Slim line interface.

5. The memory allocation system according to claim 4, wherein the second connection component further comprises a data selector disposed on a motherboard, two input/output paths of the data selector are respectively connected to the baseboard management controller and the complex programmable logic controller, and an output of the data selector is connected to the fourth slim line interface.

6. The memory allocation system of claim 5, wherein the data selector is configured to switch PCIE resources input to the converter board.

7. The memory allocation system of claim 6, wherein the data selector is further configured to:

8. The memory allocation system of claim 6, wherein the number of the switch boards is multiple, and the connection manner of the switch boards and the motherboard is the same.

9. The memory allocation system of claim 1, wherein the cpu is implemented with an X86 architecture or an ARM architecture.

10. A server, characterized in that the server comprises a memory allocation system according to any one of claims 1-9.