CN115904307B - Data buffer overflow processing method and communication system - Google Patents
Data buffer overflow processing method and communication system Download PDFInfo
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Abstract
The invention discloses a data buffer overflow processing method and a communication system, comprising the following steps: the method comprises the steps that a transmitter generates an initial data signal according to a frame interval period and a frame duration period, wherein the frame duration period is smaller than or equal to the depth of a data buffer; the transmitter sets a synchronous head at the frame head of the initial data signal as a target data signal to be transmitted to the receiver; and the receiver detects the synchronous head of the target data signal in real time, writes the target data signal into the data buffer when the synchronous head is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed so as to avoid overflow of the data buffer.
Description
Technical Field
The present invention relates to the field of electronic communications technologies, and in particular, to a data buffer overflow processing method and a communication system.
Background
In a wireless communication system, a sampling rate conversion and other subsequent digital signal processing are required after analog signals received by a receiver are subjected to analog-to-digital conversion. Typically, the analog-to-digital converter operates in an independent clock domain, while the sample rate conversion module and other subsequent digital signal processing modules operate in a baseband processing clock domain. For clock domain conversion, a FIFO (First In First Out, first-in first-out) data buffer is added between the analog-to-digital converter and the sample rate conversion module for buffering. During continuous reading and writing of the FIFO (First In First Out, first-in first-out) data buffer by the receiver, i.e. during continuous writing of the digital signal into the data buffer and continuous reading of the digital signal from the data buffer, the data buffer overflows (reads empty or full) due to the following reasons:
1) The read-write clock of the data buffer is generated by using different crystal oscillators, the speed of writing into the data buffer is not matched with the speed of reading the data buffer due to the production process error of the crystal oscillators, and when the read-write speed of the data buffer is inconsistent, the phenomenon of empty or full reading occurs after the system operates for a long time, which leads to the error code of a receiving end, namely the phenomenon of overflowing of the data buffer.
2) In sample rate conversion, for a fractional sample rate system, the read-write clock frequency is not an integer multiple, and it is difficult to ensure that the read-write rate of the data buffer is completely matched by adjusting the read duty ratio of the data buffer to prevent overflow of the data buffer.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a data buffer overflow processing method and a communication system, so as to solve the problem of overflow of a data buffer caused by unmatched read-write rates of the data buffer in the prior art.
The technical scheme of the invention is as follows:
a data buffer overflow processing method includes:
the method comprises the steps that a transmitter generates an initial data signal according to a frame interval period and a frame duration period, wherein the frame duration period is smaller than or equal to the depth of a data buffer;
the transmitter sets a synchronous head at the frame head of the initial data signal as a target data signal to be transmitted to the receiver;
and the receiver detects the synchronous head of the target data signal in real time, writes the target data signal into the data buffer when the synchronous head is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed.
The invention further provides that the step of generating the initial data signal by the transmitter in dependence of the frame interval period and the frame duration period comprises:
the transmitter generates an initial data signal according to the frame interval period, the frame duration period and the frame protection period;
wherein the frame interval period is greater than the frame duration period plus twice the frame protection period; the data buffer depth is greater than the frame duration period plus twice the frame protection period.
The invention further provides that the step of generating the initial data signal by the transmitter in accordance with the frame interval period and the frame duration period further comprises:
the receiver sets the same frame interval period as the transmitter.
The present invention further provides that the step of setting, by the transmitter, a synchronization header at a frame header of the initial data signal as a target data signal to be transmitted to the receiver includes:
and inserting a frame synchronization code sequence into a starting position set of the initial data signal of each frame as a target data signal to be input to a receiver.
The present invention further provides that the step of setting a synchronization header at a frame header of the initial data signal and outputting a target data signal by the transmitter further comprises:
the transmitter sets a synchronization header at a frame header of the initial data signal and adds information of a transmitter frame interval period and a transmitter frame duration period at the frame header.
The invention further provides that the step of writing the target data signal into the data buffer when the synchronous head is detected, and reading the target data signal from the data buffer after the target data signal is written comprises the steps of:
when the synchronous head is detected, the write-in enabling end of the data buffer is controlled to be opened, and after the frame duration period is continuously enabled, the write-in enabling end of the data buffer is closed, and the read enabling end of the data buffer is controlled to be opened.
The invention further provides that the frame interval period is greater than twice the frame duration period.
The invention further provides that the receiver detects the synchronous head of the target data signal in real time, when the synchronous head is detected, the target data signal is written into the data buffer, and after the writing of the target data signal is completed, the step of reading the target data signal from the data buffer comprises the following steps:
when the synchronous head is detected, recording the current time, and calculating a waiting period and a continuous period according to the frame interval period and the frame continuous period;
controlling a write-in enabling end of the data buffer to be closed according to the waiting period and to be opened according to the continuous period;
and controlling the reading enabling end of the data buffer to be opened according to the writing enabling end of the data buffer.
The present invention further provides that when the synchronization header is detected, the step of recording the current time and calculating the waiting period and the duration period according to the frame interval period and the frame duration period includes:
the duration period is equal to the frame duration period plus twice the frame protection period;
in the disconnected state, the waiting period is equal to the frame interval period minus the frame protection period;
in the connected state, the waiting period is equal to the frame interval period minus the frame duration period minus twice the frame duration period.
A communication system for implementing a data buffer overflow handling method as described above, comprising: a transmitter and a receiver;
the transmitter is connected with the receiver through a wireless link, generates an initial data signal according to the frame interval period and the frame duration period, and sets a synchronous head at a frame head of the initial data signal and outputs a target data signal;
the receiver is used for receiving the target data signal, detecting the synchronous head in real time, writing the target data signal into the receiver data buffer when the synchronous head is detected, and reading the target data signal from the receiver data buffer after the target data signal is written.
The present invention is further provided, the transmitter including: the system comprises a transmitting end baseband processing module, a synchronous head module, a transmitter fractional multiple sampling conversion module, a transmitter data buffer and a digital-to-analog converter; the receiver comprises a receiving end baseband processing module, a receiver fractional multiple sampling conversion module, a receiver data buffer, a synchronization module and an analog-to-digital converter;
the transmitting end baseband processing module is connected with the synchronous head module and is used for transmitting an initial data signal to the synchronous head module according to the frame interval period and the frame duration period;
the synchronous head module is connected with the transmitter fractional multiple sampling conversion module and is used for setting a synchronous head at the frame head of the initial data as a target data signal and transmitting the target data signal to the transmitter fractional multiple sampling conversion module;
the fractional multiple sampling conversion module is connected with the transmitter data buffer and is used for performing fractional multiple sampling rate conversion on the target data signal and transmitting the target data signal to the transmitter data buffer;
the transmitter data buffer is connected with the digital-to-analog converter, and is used for buffering the target data signal subjected to fractional multiple sampling rate conversion and outputting the target data signal to the digital-to-analog converter; the digital-to-analog converter is used for performing digital-to-analog conversion on the buffered target data signal and transmitting the target data signal to a receiver through a wireless link;
the analog-to-digital converter is connected with the receiver data buffer and is used for performing analog-to-digital conversion on the target data signal after digital-to-analog conversion and outputting the target data signal to the receiver data buffer;
the receiver data buffer is respectively connected with the receiver fractional multiple sampling rate conversion module and the synchronization module, and is used for writing the target data signal according to the detection signal output by the synchronization module and outputting the target data signal to the receiver fractional multiple sampling rate conversion module after the target data signal is written;
the receiver fractional sampling rate module is connected with the synchronous module and is used for reading the target data signal and carrying out fractional sampling rate conversion on the target data signal so as to output the target data signal to the synchronous module;
the synchronization module is respectively connected with the receiver data buffer and the receiving end baseband processing module and is used for outputting the target data signal converted by the receiver fractional multiple sampling rate conversion module to the receiving end baseband processing module, detecting a synchronization head of the signal converted by the receiver fractional multiple sampling rate conversion module and sending a detection signal to the receiver data buffer when the synchronization head is detected;
the receiving end baseband processing module is connected with the synchronizing module and is used for carrying out frame de-processing on the signals converted by the receiver fractional multiple sampling rate conversion module.
The invention provides a data buffer overflow processing method and a communication system, wherein the method comprises the following steps: the method comprises the steps that a transmitter generates an initial data signal according to a frame interval period and a frame duration period, wherein the frame duration period is smaller than or equal to the depth of a data buffer; the transmitter sets a synchronous head at the frame head of the initial data signal as a target data signal to be transmitted to the receiver; and the receiver detects the synchronous head of the target data signal in real time, writes the target data signal into the data buffer when the synchronous head is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed. The invention generates an initial data signal according to the frame interval period and the frame duration period, and sets a synchronous head at the frame head of the initial data signal, so as to predict the arrival time of the initial data signal of each frame by detecting the synchronous head, thereby obtaining the time point of writing the target data signal into the data buffer. When the time point of writing the target data signal into the data buffer is obtained, writing the target data signal into the data buffer, and reading the target data signal after the writing of the target data signal is completed by enabling the frame duration period to be smaller than or equal to the depth of the data buffer so that the data volume of the target data signal does not exceed the storage space of the data buffer, thereby avoiding the writing of the data buffer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained from the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of a prior art read/write timing diagram of a data buffer under rate matching.
FIG. 2 is a flow chart of a method for processing overflow of a data buffer in the present invention.
Fig. 3 is a schematic diagram of a structure of detecting a synchronization header after a data buffer in a communication system according to a data buffer overflow processing method of the present invention.
Fig. 4 is a schematic diagram of a communication system for detecting a synchronization header before a data buffer in the data buffer overflow processing method according to the present invention.
FIG. 5 is a timing diagram illustrating a method for detecting a synchronization header before a data buffer according to the present invention.
FIG. 6 is a timing diagram illustrating a method for detecting a synchronization header after a data buffer according to the present invention.
Fig. 7 is a schematic diagram of a communication system in the communication system of the data buffer overflow handling method of the present invention.
Detailed Description
The invention provides a data buffer overflow processing method and a communication system, which are used for making the purposes, technical schemes and effects of the invention clearer and more definite, and the invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The inventor researches that in a communication system, the read-write clock of the data buffer is generated by using different crystal oscillators, the speed of writing the data buffer is not matched with the speed of reading the data buffer due to the production process error of the crystal oscillators, and when the read-write speed of the data buffer is inconsistent, the data buffer can be output after the system is operated for a long timeThe phenomenon of empty or full reading occurs, which leads to error code at the receiving end, namely, overflow of the data buffer. In some cases, the read-write rate matching can be achieved through sampling rate conversion, and when the sampling rate conversion multiple is a fraction, it is difficult to ensure the complete matching of the read-write rate of the data buffer by adjusting the duty ratio read by the data buffer. For example, the baseband processing clock frequency is 62.5Mhz and the digital-to-analog conversion clock domain frequency is 245.76Mhz, and the relationship between the baseband processing clock frequency and the digital-to-analog clock frequency is not an integer multiple, the read duty ratio needs to be set by the data buffer to perform rate matching, that is, the integers P and Q are set such that
Assuming values p=116 and q=118, as shown in fig. 1, at this duty ratio, the amount of write data is smaller than the amount of read data, but after passing
After seconds, the data buffer will enter a read empty state (L is the depth of the data buffer), so it is difficult to ensure that the read-write rate of the data buffer is completely matched by adjusting the read duty ratio of the data buffer so as to prevent the data buffer from overflowing.
The invention provides a data buffer overflow processing method aiming at the technical problems.
Referring to fig. 2 to 6, in one embodiment of the data buffer overflow processing method, the method includes the steps of:
s100, the transmitter generates an initial data signal according to a frame interval period T and a frame duration period D, wherein the frame duration period D is smaller than or equal to a data buffer depth L.
Specifically, generating the initial data signal according to the frame interval period T and the frame duration period D means that the transmitter generates one frame of the initial data signal every other frame interval period T, and the duration of one frame of the initial data signal is the frame duration period D. Generally, the initial data signal is continuously written into the data buffer and the initial data signal is continuously read from the data buffer at the same time, but if the initial data signal is written into the data buffer at a rate not matching the rate of reading from the data buffer, the data buffer will overflow. Therefore, the transmitter sets the frame interval period T and the frame duration period D by the framing technique such that one frame of the initial data signal is transmitted every frame interval period T, and the duration of the initial data signal is the frame duration period D, wherein the frame interval period T is greater than the frame duration period D. And setting a frame interval period T and a frame duration period D to control the data volume of the target data signal written into the data buffer memory, so as to prevent the data buffer memory from being empty or full. The data buffer has a limit to the amount of data stored, that is, the data buffer depth L has a limit, and when the amount of data input into the data buffer exceeds the data buffer depth, the data buffer overflows. Therefore, by setting the data buffer depth L to be larger than the frame duration period D (L > D), it is prevented that the data buffer overflows when the subsequent data is written into the data buffer.
Specifically, in one embodiment, step S100 includes:
s110, the transmitter generates an initial data signal according to a frame interval period T, a frame duration period D and a frame protection period a; wherein the frame interval period T is greater than the frame duration period D plus twice the frame protection period a; the data buffer depth L is greater than the frame duration period D plus twice the frame protection period a.
Specifically, by setting the frame protection period a and making the frame interval period T > the frame duration period d+2 x the frame protection period a (T > d+2a), it is prevented that the data at the front end or the rear end of the frame duration period D is not completely written into the data buffer due to delay or other reasons when the target data signal is written into the data buffer later, so that the data is lost. By making the data buffer depth L > the frame duration period d+2 the frame protection period a (L > d+2a), it is possible to further prevent the subsequent data buffer write data amount from exceeding the data buffer depth L, causing the data buffer to overflow.
In one embodiment, step S100 further comprises:
s120, the receiver sets the same frame interval period as the transmitter and the frame duration period.
In a communication system, a transmitter transmits data information of a signal to a receiver only during transmission of the signal to the receiver through a wireless link, and the receiver cannot confirm a frame interval period T and a frame duration period D of the signal transmitted by the transmitter, so that the information of the transmitter and the receiver is synchronized by setting the same frame interval period T and the same frame duration period D as those of the transmitter, and thus, overflow of a subsequent data buffer is also avoided.
And S200, the transmitter sets a synchronous head at the frame head of the initial data signal as a target data signal and transmits the target data signal to the receiver.
Specifically, a frame synchronization code sequence is inserted in a starting position of the initial data signal of each frame in a concentrated manner to be input into a receiver as a target data signal, so that a subsequent receiver can predict the time when the target data signal reaches the data buffer in the receiver, namely the time when the target data signal is written into the data buffer, through detecting a synchronization head, thereby avoiding overflow of the subsequent data buffer.
In one embodiment, step S200 includes:
s210, the transmitter sets a synchronization header at the frame header of the initial data signal, and adds information of a transmitter frame interval period T and a transmitter frame duration period D at the frame header.
Specifically, in the communication system, the transmitter transmits only the data information of the signal to the receiver in the process of transmitting the signal to the receiver through the wireless link, and the receiver cannot confirm the frame interval period T and the frame duration period D of the transmitter transmitting the signal, so that the transmitter and the transmitter information are synchronized by adding the information of the frame interval period T and the frame duration period D of the transmitter at the frame head, so that the frame interval period T and the frame duration period D of the transmitter of the target signal can be detected at the same time when the synchronization head is detected later, thereby facilitating the subsequent confirmation of the data writing node of the data buffer and the written data amount of the data buffer, and further preventing the overflow of the data buffer.
And S300, the receiver detects the synchronous head of the target data signal in real time, writes the target data signal into the data buffer when the synchronous head is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed.
Specifically, when the transmitter transmits the target data signal to the receiver through the wireless link, the receiver detects the synchronization header of the target data signal in real time, when the synchronization header is detected, the signal containing the specified frame interval period T and the frame duration period D arrives, at this time, the target data signal is written into the data buffer, and after one frame of the target data signal is written, that is, after the frame duration period D passes, the data buffer enters a data reading state. And after the target data signals are written into the data buffer, the target data signals of the data buffer are read, so that the problem of unmatched read-write speed of the data buffer is avoided, and overflow of the data buffer is prevented.
In one embodiment, the S300 includes:
s310, as shown in FIG. 5, when the synchronous head is detected, the write-in enabling end of the data buffer is controlled to be opened, and after the frame is continuously enabled for the period D, the write-in enabling end of the data buffer is closed, and the read enabling end of the data buffer is controlled to be opened.
Specifically, when the synchronization head is detected, the current time is recorded, and the write enable end of the data buffer is controlled to be opened so that the target data signal is written into the data buffer, and the write enable end of the data buffer continuously enables the frame duration period, that is, the target data signal is continuously written into the data buffer for the frame duration period, so that the target data signal is completely written. After the frame is continuously enabled for the duration period D, namely after the data signal is written into the data buffer, the writing enabling end of the data buffer is closed, and the reading enabling end of the data buffer is opened so as to read the data written into the data buffer. The frame interval period T >2 and the frame duration period D are set so that there is enough time to read the data written into the data buffer. And when the synchronous head is not detected, the writing enabling end of the data buffer is closed, and the reading enabling end of the data buffer is closed to stop data transmission. After the writing of the target data signal is completed, the target data signal is read, and the frame duration period D in the target data signal is smaller than or equal to the depth of the data buffer, so that overflow of the data buffer is avoided.
The time can be set to realize the operation of reading the target data signal from the data buffer after the target data signal is completely written into the data buffer. After the synchronous head is detected, the read enabling end of the data buffer is controlled to be opened after the frame of the transmitter is continuously in the period D, or the read enabling end of the data buffer can be controlled to be opened by capturing the falling edge of the write enabling end of the data buffer when the falling edge of the write enabling end arrives.
In one embodiment, the S300 includes:
s320, as shown in fig. 4 and 6, when the synchronization header is detected, the current time is recorded, and a waiting period and a duration period are calculated according to the frame interval period T and the frame duration period D.
And controlling the write-in enabling end of the data buffer to be closed according to the waiting period and to be opened according to the continuous period.
And controlling the reading enabling end of the data buffer to be opened according to the writing enabling end of the data buffer.
Specifically, when the synchronous head is not detected, the write enabling end and the read enabling end of the data buffer are opened, so that the target data signal is continuously written and read by the data buffer. When the synchronization header is detected, the current time is recorded, and the waiting period and the duration period are calculated according to the frame interval period T and the frame duration period D. The waiting period is the period time when the data buffer write enabling end does not work, and the duration period is the period time when the data buffer write enabling end works. It should be noted that, the duration period matches the frame duration period D of the target data signal, which is understood to be greater than or equal to the frame duration period D, so that the target data signal can be completely written into the data buffer. The read enabling end of the data buffer is turned on according to the write enabling end of the data buffer, and after the write enabling end of the data buffer is enabled, the data buffer is controlled to be turned on after a continuous period, so as to read the target data signal of the data buffer, and further prevent the data buffer from overflowing.
In one embodiment, step S320 includes:
s321, the duration period is equal to the frame duration period plus twice the frame protection period.
In the disconnected state, the waiting period is equal to the frame interval period minus the frame protection period.
In the connected state, the waiting period is equal to the frame interval period minus the frame duration period minus twice the frame duration period.
Specifically, as shown in fig. 4, when the receiver is started, the receiver enters a disconnected state. During the non-connection state, the write enable end of the data buffer is opened, the target data signal is continuously written into the data buffer, meanwhile, the synchronous head in the target data signal is continuously detected, when the synchronous head is detected, the receiver records the current time, and calculates a waiting period, wherein the waiting period=the frame interval period T-the frame protection period a, and meanwhile, the write enable end of the data buffer is controlled to be closed. At this time, the receiver enters a connected state.
When the receiver enters the connection state, after the receiver continuously waits according to the waiting period calculated before entering the connection state, namely after the data buffer write enabling end continuously closes the waiting period, the data buffer write enabling end is controlled to be opened, and the continuous period is continuously enabled, wherein the continuous period = the frame continuous period d+2 the frame protection period a. And during the enabling period of the writing enabling end of the data buffer, the target data signal is continuously written into the data buffer, after the enabling and receiving of the writing enabling end of the data buffer, the fractional sampling rate module of the receiver reads all data (target data signal) of the data buffer, performs fractional sampling rate conversion, and inputs the target data signal to the synchronous module after conversion.
And if the synchronous head is detected, the synchronous module keeps a connection state, records the current time and calculates a waiting period, wherein the waiting period=the frame interval period T-the frame duration period-2 and the frame duration period D. Meanwhile, input data (target data signal) is input to the baseband processing module for signal processing, for example: channel estimation and compensation are performed, transmitting end data is recovered, a received signal is recovered to be in a bit stream form, and customized control data and service data are separated, which can be understood as demodulation processing and frame de-framing processing. When no synchronization header is detected, a non-connected state is entered. With this cycle until the power is turned off and the communication ends.
Referring to fig. 7, the present invention further provides a communication system, including: a transmitter and a receiver; the transmitter is connected with the receiver through a wireless link, and is used for presetting a transmitter frame interval period T and a transmitter frame duration period D, generating an initial data signal according to the frame interval period T and the frame duration period D, setting a synchronous head at a frame head of the initial data signal and outputting a target data signal.
The receiver is used for receiving the target data signal, detecting the synchronous head in real time, writing the target data signal into the data buffer when the synchronous head is detected, and reading the target data signal from the data buffer after the target data signal is written. In particular, embodiments of a data buffer overflow processing method are described herein, and are not described in detail.
In one embodiment, the transmitter includes: a transmitting end baseband processing module 110, a synchronous head module 120, a transmitter fractional multiple sampling conversion module 130, a transmitter data buffer 140 and a digital-to-analog converter 150; the receiver includes a receiving end baseband processing module 250, a synchronization module 240, a receiver fractional multiple sampling conversion module 230, a receiver data buffer 220, and an analog-to-digital converter 210; the transmitting-end baseband processing module 110 is connected to the synchronization header module 120, and is configured to transmit an initial data signal to the synchronization header module 120 according to the frame interval period and the frame duration period; the synchronization header module 120 is connected to the transmitter fractional multiple sampling conversion module 130, and is configured to set a synchronization header at a frame header of the initial data as a target data signal, and send the target data signal to the transmitter fractional multiple sampling conversion module 130; the fractional sample conversion module 130 is connected to the transmitter data buffer 140, and is configured to perform fractional sample rate conversion on the target data signal and send the target data signal to the transmitter data buffer 140; the transmitter data buffer 140 is connected to the digital-to-analog converter 150, and the transmitter data buffer 140 is configured to buffer the signal after fractional multiple sampling rate conversion and output the signal to the digital-to-analog converter 150; the digital-to-analog converter 150 is configured to perform digital-to-analog conversion after buffering and transmit the buffered digital-to-analog conversion to a receiver through a wireless link.
The analog-to-digital converter 210 is connected to the receiver data buffer 220, and is configured to perform analog-to-digital conversion on the signal after digital-to-analog conversion and output the signal to the receiver data buffer 220; the receiver data buffer 220 is respectively connected to the receiver fractional sample rate conversion module 230 and the synchronization module 240, and is configured to write a target data signal according to a detection signal, and output the target data signal to the receiver fractional sample rate conversion module 230 after the target data signal is written; the receiver fractional sample rate module 230 is connected to the synchronization module 240, and is configured to read the target data signal, and perform receiver fractional sample rate conversion on the target data signal to output to the synchronization module 240; the synchronization module 240 is respectively connected to the receiver data buffer and the receiving-end baseband processing module 250, and is configured to output the signal converted by the receiver fractional sample rate conversion module 230 to the receiving-end baseband processing module 250, perform synchronization header detection on the signal converted by the receiver fractional sample rate conversion module 230, and send a detection signal to the receiver data buffer 220 when the synchronization header is detected; the receiving-end baseband processing module 250 is connected to the synchronization module 240, and is configured to perform a frame de-processing on the signal converted by the receiver fractional multiple sampling rate conversion module 230. It should be noted that, because the analog-to-digital converter is in the analog-to-digital converter clock domain, and the receiver fractional sampling conversion module and the receiving end baseband processing module are in the baseband processing clock domain, in general, the analog-to-digital converter clock domain is far greater than the baseband processing clock domain, and the larger the working clock domain is, the more resources are occupied, so that by setting the synchronization module between the receiver fractional sampling rate module and the receiving end baseband processing module, the resource consumption of the synchronization module can not be increased. In particular, embodiments of a data buffer overflow processing method are described herein, and are not described in detail.
In summary, the data buffer overflow processing method and the communication system provided by the invention include: the method comprises the steps that a transmitter generates an initial data signal according to a frame interval period and a frame duration period, wherein the frame duration period is smaller than or equal to the depth of a data buffer; the transmitter sets a synchronous head at the frame head of the initial data signal as a target data signal to be transmitted to the receiver; and the receiver detects the synchronous head of the target data signal in real time, writes the target data signal into the data buffer when the synchronous head is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed. The invention generates an initial data signal according to the frame interval period and the frame duration period, and sets a synchronous head at the frame head of the initial data signal, so as to predict the arrival time of the initial data signal of each frame by detecting the synchronous head, thereby obtaining the time point of writing the target data signal into the data buffer. When the time point of writing the target data signal into the data buffer is obtained, writing the target data signal into the data buffer, and reading the target data signal after the writing of the target data signal is completed by enabling the frame duration period to be smaller than or equal to the depth of the data buffer so that the data volume of the target data signal does not exceed the storage space of the data buffer, thereby avoiding the writing of the data buffer.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. A method for processing overflow of a data buffer, comprising:
the method comprises the steps that a transmitter generates an initial data signal according to a frame interval period and a frame duration period, wherein the frame duration period is smaller than or equal to the depth of a data buffer;
the transmitter sets a synchronous head at the frame head of the initial data signal as a target data signal to be transmitted to the receiver;
the receiver detects the synchronous head of the target data signal in real time, writes the target data signal into the data buffer when the synchronous head is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed;
the step of generating the initial data signal by the transmitter according to the frame interval period and the frame duration period includes:
the transmitter generates an initial data signal according to the frame interval period, the frame duration period and the frame protection period;
wherein the frame interval period is greater than the frame duration period plus twice the frame protection period; the data buffer depth is greater than the frame duration period plus twice the frame protection period.
2. The data buffer overflow handling method of claim 1, wherein the step of the transmitter generating an initial data signal based on a frame interval period and a frame duration period further comprises:
the receiver sets the same frame interval period as the transmitter.
3. The data buffer overflow processing method of claim 1, wherein the step of the transmitter setting a synchronization header at a frame header of the initial data signal as a target data signal to be transmitted to the receiver comprises:
and inserting a frame synchronization code sequence into a starting position set of the initial data signal of each frame as a target data signal to be input to a receiver.
4. The data buffer overflow processing method of claim 1, wherein the step of the transmitter setting a synchronization header at a frame header of the initial data signal and outputting a target data signal further comprises:
the transmitter sets a synchronization header at a frame header of the initial data signal and adds information of a transmitter frame interval period and a transmitter frame duration period at the frame header.
5. The data buffer overflow processing method of claim 1, wherein the step of writing a target data signal to the data buffer when the sync head is detected, and reading the target data signal from the data buffer after the target data signal is written, comprises:
when the synchronous head is detected, the write-in enabling end of the data buffer is controlled to be opened, and after the frame duration period is continuously enabled, the write-in enabling end of the data buffer is closed, and the read enabling end of the data buffer is controlled to be opened.
6. The data buffer overflow handling method of claim 5, wherein the frame interval period is greater than twice the frame duration period.
7. The data buffer overflow processing method of claim 1, wherein the receiver detects the sync header of the target data signal in real time, writes the target data signal to the data buffer when the sync header is detected, and reads the target data signal from the data buffer after the writing of the target data signal is completed, comprising:
when the synchronous head is detected, recording the current time, and calculating a waiting period and a continuous period according to the frame interval period and the frame continuous period;
controlling a write-in enabling end of the data buffer to be closed according to the waiting period and to be opened according to the continuous period;
and controlling the reading enabling end of the data buffer to be opened according to the writing enabling end of the data buffer.
8. The data buffer overflow processing method of claim 1, wherein the step of recording the current time and calculating the waiting period and the sustaining period based on the frame interval period and the frame sustaining period when the sync header is detected comprises:
the duration period is equal to the frame duration period plus twice the frame protection period;
in the disconnected state, the waiting period is equal to the frame interval period minus the frame protection period;
in the connected state, the waiting period is equal to the frame interval period minus the frame duration period minus twice the frame duration period.
9. A communication system for implementing the data buffer overflow handling method of any of claims 1-8, the communication system comprising: a transmitter and a receiver;
the transmitter is connected with the receiver through a wireless link, generates an initial data signal according to the frame interval period and the frame duration period, and sets a synchronous head at a frame head of the initial data signal and outputs a target data signal;
the receiver is used for receiving the target data signal, detecting the synchronous head in real time, writing the target data signal into the receiver data buffer when the synchronous head is detected, and reading the target data signal from the receiver data buffer after the target data signal is written.
10. The communication system according to claim 9, wherein the transmitter comprises: the system comprises a transmitting end baseband processing module, a synchronous head module, a transmitter fractional multiple sampling conversion module, a transmitter data buffer and a digital-to-analog converter; the receiver comprises a receiving end baseband processing module, a receiver fractional multiple sampling conversion module, a receiver data buffer, a synchronization module and an analog-to-digital converter;
the transmitting end baseband processing module is connected with the synchronous head module and is used for transmitting an initial data signal to the synchronous head module according to the frame interval period and the frame duration period;
the synchronous head module is connected with the transmitter fractional multiple sampling conversion module and is used for setting a synchronous head at the frame head of the initial data as a target data signal and transmitting the target data signal to the transmitter fractional multiple sampling conversion module;
the fractional multiple sampling conversion module is connected with the transmitter data buffer and is used for performing fractional multiple sampling rate conversion on the target data signal and transmitting the target data signal to the transmitter data buffer;
the transmitter data buffer is connected with the digital-to-analog converter, and is used for buffering the target data signal subjected to fractional multiple sampling rate conversion and outputting the target data signal to the digital-to-analog converter; the digital-to-analog converter is used for performing digital-to-analog conversion on the buffered target data signal and transmitting the target data signal to a receiver through a wireless link;
the analog-to-digital converter is connected with the receiver data buffer and is used for performing analog-to-digital conversion on the target data signal after digital-to-analog conversion and outputting the target data signal to the receiver data buffer;
the receiver data buffer is respectively connected with the receiver fractional multiple sampling rate conversion module and the synchronization module, and is used for writing the target data signal according to the detection signal output by the synchronization module and outputting the target data signal to the receiver fractional multiple sampling rate conversion module after the target data signal is written;
the receiver fractional sampling rate module is connected with the synchronous module and is used for reading the target data signal and carrying out fractional sampling rate conversion on the target data signal so as to output the target data signal to the synchronous module;
the synchronization module is respectively connected with the receiver data buffer and the receiving end baseband processing module and is used for outputting the target data signal converted by the receiver fractional multiple sampling rate conversion module to the receiving end baseband processing module, detecting a synchronization head of the signal converted by the receiver fractional multiple sampling rate conversion module and sending a detection signal to the receiver data buffer when the synchronization head is detected;
the receiving end baseband processing module is connected with the synchronizing module and is used for carrying out frame de-processing on the signals converted by the receiver fractional multiple sampling rate conversion module.
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