CN115882990A - Clock synchronization method and device in digital subcarrier multiplexing system - Google Patents
Clock synchronization method and device in digital subcarrier multiplexing system Download PDFInfo
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Abstract
The invention relates to a clock synchronization method and a clock synchronization device in a digital subcarrier multiplexing system. The method comprises the following steps: interpolating a sequence of multiplexed signal samples comprising a plurality of subcarriers based on the fractional interval and a base pointer; carrying out subcarrier demultiplexing on the multiplexed signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence; respectively carrying out dispersion compensation on the multi-channel subcarrier signal sampling sequences; selecting a target subcarrier signal sampling sequence from the multi-channel subcarrier signal sampling sequences subjected to dispersion compensation to perform timing error detection to obtain timing error information; calculating a fractional interval and a base pointer based on the timing error information; determining fractional interval conversion parameters based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional intervals according to the conversion parameters; the sequence of multiplexed signal samples is interpolated based on the base pointer and the converted fractional interval. Thus, a feedback cycle is completed, and the timing error of the multiplex signal sampling sequence is eliminated after a plurality of feedback cycles.
Description
Technical Field
The present invention relates to the field of optical fiber communication technologies, and in particular, to a clock synchronization method and apparatus in a digital subcarrier multiplexing system.
Background
With the C + L band available frequency of the optical fiber being almost fully utilized, the traditional Wavelength Division Multiplexing (WDM) system that only relies on increasing the number of Multiplexing wavelengths or reducing the channel spacing faces the physical bottleneck that the system capacity is difficult to further increase, the optical transmission system faces huge bandwidth pressure, and the single Wavelength channel 800Gbps and higher rate coherent optical transmission technology becomes the key technology in the field of large-capacity long-distance optical fiber transmission under this background. A Digital Subcarrier Multiplexing (DSCM) system not only has the technical advantages of Enhanced chromatic dispersion and nonlinear tolerance and reduced Phase Noise (EEPN) Enhanced by an equalizer, but also can realize flexible adjustment of transmission rate and transmission distance through dynamic configuration of subcarriers, and realize optimal adaptation to dynamic optical connection, and has become one of powerful system solutions supporting transmission of a single wavelength channel 800Gbps and higher rates, so that the DSCM system has been continuously concerned by researchers in the academic and industrial fields in China and abroad in recent years.
In a Digital subcarrier multiplexing system, clock synchronization is one of basic functions in a Digital Signal Processing (DSP) algorithm module at a receiving end, and a currently proposed clock synchronization scheme suitable for a DSCM system is to perform clock synchronization on each subcarrier Signal through a DSP algorithm. However, the DSCM clock technical solutions have some disadvantages that the existing clock synchronization scheme causes a complex circuit structure and a high algorithm complexity.
Disclosure of Invention
The invention provides a clock synchronization method and a clock synchronization device in a digital subcarrier multiplexing system, which are used for solving the defects of complex circuit structure and higher algorithm complexity caused by the existing clock synchronization scheme.
The invention provides a clock synchronization method in a digital subcarrier multiplexing system, which comprises the following steps:
interpolating a sequence of multiplexed signal samples comprising a plurality of subcarriers based on the fractional interval and a base pointer;
carrying out subcarrier demultiplexing on the multiplexing signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence;
respectively carrying out dispersion compensation on the multi-channel subcarrier signal sampling sequences;
selecting one path of target subcarrier signal sampling sequence from the multipath subcarrier signal sampling sequences after dispersion compensation to carry out timing error detection to obtain timing error information;
calculating a fractional interval and a base pointer based on the timing error information;
determining conversion parameters of the fractional intervals based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional intervals according to the conversion parameters; the conversion parameter is used for shortening the period of the fractional interval and keeping the amplitude unchanged;
and interpolating the multiplex signal sampling sequence based on the basic pointer and the converted fractional interval, so as to complete a feedback cycle, and eliminating the timing error of the multiplex signal sampling sequence after a plurality of feedback cycles.
According to the clock synchronization method in the digital subcarrier multiplexing system provided by the invention,
the determining a conversion parameter of the fractional interval based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter includes:
and determining the conversion parameter of the fractional interval based on the sum of the symbol rates of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter.
According to the clock synchronization method in the digital subcarrier multiplexing system provided by the invention,
the determining of the fractionally spaced conversion parameters based on the sum of the symbol rates of the respective subcarrier signal sample sequences and the symbol rate of the target subcarrier signal sample sequence is determined by calculating according to the following formula:
wherein M represents a conversion parameter, R SCi Representing the symbol rate, R, of a sequence of samples i of a subcarrier signal SC_TED Representing the symbol rate, R, of a sample sequence of a target subcarrier signal SC1 +R SC +…+R SCi Means that after M is determined based on the sum of the symbol rates of the subcarrier signal sample sequences, the period of the fractional interval is shortened by M times, keeping its amplitude constant.
According to the clock synchronization method in the digital subcarrier multiplexing system provided by the invention,
said calculating fractional intervals and base pointers based on said timing error information, comprising:
filtering the timing error information to output a control word;
a fractional interval and a base pointer are calculated based on the control word.
According to the clock synchronization method in the digital subcarrier multiplexing system provided by the invention,
said interpolating said sequence of multiplexed signal samples based on said base pointer and converted fractional interval comprises:
performing polynomial interpolation on the sequence of multiplexed signal samples by Lagrangian interpolation or linear interpolation based on the base pointer and the converted fractional interval to correct timing errors on the sequence of multiplexed signal samples.
The invention also provides a clock synchronization device in a digital subcarrier multiplexing system, which comprises:
an interpolation module for interpolating the sequence of multiplexed signal samples based on the base pointer and the converted fractional interval;
the subcarrier demultiplexing module is used for carrying out subcarrier demultiplexing on the multiplexing signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence;
the dispersion compensation module is used for carrying out dispersion compensation on the multi-channel subcarrier signal sampling sequence;
a timing error detection module, configured to select one target subcarrier signal sampling sequence from the dispersion-compensated multiple subcarrier signal sampling sequences to perform timing error detection, so as to obtain timing error information;
a fractional interval and base pointer calculation module for calculating fractional intervals and base pointers based on the timing error information;
a fractional interval conversion module, configured to determine a conversion parameter of the fractional interval based on a symbol rate of each subcarrier signal sampling sequence, and convert the fractional interval according to the conversion parameter; the conversion parameter is used for shortening the period of the fractional interval and keeping the amplitude unchanged;
and the operation control module is used for carrying out parameter control on the subcarrier demultiplexing module, the dispersion compensation module, the timing error detection module, the fractional interval and basic pointer calculation module, the fractional interval conversion module and the interpolation module.
The invention provides a clock synchronization method and a device in a digital subcarrier multiplexing system, which are based on the characteristic that clocks of subcarriers in the digital subcarrier multiplexing system are homologous, only perform timing error detection on one path of target subcarrier signal in a multi-path subcarrier signal sampling sequence, and then calculate a fractional interval and a basic pointer based on timing error information obtained by the timing error detection; determining conversion parameters of the fractional intervals based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional intervals according to the conversion parameters: shortening the period of the fraction interval by converting parameters and keeping the amplitude degree of the fraction interval unchanged; and interpolating the multiplexing signal sampling sequence based on the basic pointer and the converted fractional interval, circularly executing the steps, and after a plurality of feedback cycles, enabling the fractional interval to form stable periodic change from irregular change at the beginning, and eliminating the timing error on the multiplexing signal sampling sequence. Therefore, the embodiment of the invention corrects the timing error on the multiplex signal sampling sequence and completes the synchronization of all the subcarrier signal sampling sequences. Compared with the prior art, the clock synchronization is respectively carried out on each subcarrier signal sampling sequence, and the embodiment of the invention does not need to carry out the parallel operation of the multiple subcarrier signal sampling sequences, so that the required circuit area is smaller, the circuit complexity is reduced, and the algorithm complexity is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a clock synchronization method in a digital subcarrier multiplexing system provided by the present invention;
FIG. 2 is a functional block diagram of a DSCM coherent optical receiver DSP according to an embodiment of the present invention;
FIG. 3 is a spectrum diagram of a 4 × 32GBaud PM-16QAM DSCM system multiplexing signal composed of 4 sub-carriers with a sub-carrier symbol rate of 32GBaud according to the present invention;
FIG. 4 is a schematic diagram showing the comparison between the performance of the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention in the 4 × 32GBaud PM-16QAM DSCM system provided by the present invention and the performance of the clock synchronization method performed by each subcarrier in the prior art;
FIG. 5 is a spectrum of a 128GBaud PM-16QAM DSCM system multiplexing signal composed of 8 subcarriers with different symbol rates provided by the invention;
FIG. 6 is a schematic diagram showing the comparison between the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention in the 128GBaud PM-16QAM DSCM system composed of 8 subcarriers with different symbol rates provided by the present invention and the clock synchronization method respectively performed by each subcarrier in the existing scheme;
fig. 7 is a schematic diagram of the comparison of the algorithm complexity between the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention and the clock synchronization method respectively performed on each subcarrier in the existing scheme;
fig. 8 is a functional structure diagram of a clock synchronization apparatus in the digital subcarrier multiplexing system provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a clock synchronization method in a digital subcarrier multiplexing system includes:
it should be noted that the fractional interval and the basic index are determined by a timing error detected from the subcarrier. The initial fractional interval may be a random fractional interval.
And 200, carrying out subcarrier demultiplexing on the multiplexing signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence.
In particular, the electronic device performs polynomial interpolation using a base pointer and an initial fractional interval on a sequence of multiplexed signal samples comprising a plurality of subcarriers. The polynomial interpolation may be determined by lagrange interpolation or linear interpolation. And the electronic equipment performs subcarrier demultiplexing on the multiplexing signal sampling sequence comprising the plurality of subcarriers to obtain a multi-channel subcarrier signal sampling sequence.
It should be noted that various time domain algorithms and frequency domain algorithms may be used for the subcarrier demultiplexing operation in the embodiments of the present invention.
specifically, the electronic device performs dispersion compensation on each subcarrier signal sampling sequence, and the dispersion compensation algorithm may adopt a frequency domain algorithm or a time domain algorithm.
And 400, selecting one path of target subcarrier signal sampling sequence from the dispersion-compensated multipath subcarrier signal sampling sequences to perform timing error detection to obtain timing error information.
And the electronic equipment selects one path of target subcarrier signal sampling sequence from the multipath subcarrier signal sampling sequences after dispersion compensation to carry out timing error detection so as to obtain timing error information. The target subcarrier signal sampling sequence is any subcarrier signal sampling sequence in the multipath subcarrier signal sampling sequence.
The embodiment of the invention carries out timing error detection on the target subcarrier signal sampling sequence and extracts timing error information. Where timing error detection may select the applicable algorithm according to the subcarrier sampling rate. For example, taking the case of a sampling rate of 2 times the symbol rate of the subcarrier as an example, the timing error detection may use algorithms such as the Godard algorithm, the Gardner algorithm, or other clock error detection, the output of the timing error detection algorithm is represented as ∈ (n), and n represents the sequence number of the current sample value.
The electronics determine a fractional interval and a base pointer to interpolate the sequence of multiplexed signal samples based on the timing error information. Specifically, the step 500 of calculating the fractional interval and the basic pointer based on the timing error information includes:
step 510, filtering the timing error information to output a control word.
Step 520, calculating fractional intervals and base pointers based on the control words.
In particular, embodiments of the present invention may track timing phase errors and timing frequency errors. And after filtering the timing error information and eliminating noise influence, outputting a control word W (n).
The electronic device calculates a base pointer and a fractional interval from the control word W (n).
Specifically, the step 600 of determining the conversion parameter of the fractional interval based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter includes:
and determining the conversion parameter of the fractional interval based on the sum of the symbol rates of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter.
Specifically, the determining the fractionally spaced conversion parameter based on the sum of the symbol rates of the subcarrier signal sample sequences and the symbol rate of the target subcarrier signal sample sequence is determined by calculating according to the following formula:
wherein M represents a conversion parameter, R SCi Representing the symbol rate, R, of a sequence of samples i of a subcarrier signal SC_TED Representing the symbol rate, R, of a sample sequence of a target subcarrier signal SC1 +R SC2 +…+R SCi Indicating that after M is determined based on the sum of the symbol rates of the subcarrier signal sample sequences, the fractional interval period is shortened by M times, keeping its amplitude constant.
It should be noted that, in the digital subcarrier multiplexing system, different symbol rates R are generally allocated to subcarriers according to actual requirements SCi The more common configuration is to allocate a higher symbol rate to the center subcarrier of the spectrum, allocate a lower symbol rate to the edge subcarriers of the spectrum, and allocate the same symbol rate to each subcarrierEmbodiments of the present invention are applicable in both cases, but require a complex symbol rate of the multiplexed signal sample sequence
(i.e., R) SC1 +R SC2 +…+R SCi ) Symbol rate R of a sample sequence of a target subcarrier signal which is required to be an error in detection SC_TED Integer multiples of. The electronics interpolate the sequence of multiplexed signal samples based on the base pointer and the converted fractional interval to correct timing errors on the sequence of multiplexed signal samples. Specifically, step 100 is executed again to interpolate the sequence of samples of the multiplexed signal based on the fractional interval and the base pointer. The electronics perform polynomial interpolation on the sequence of multiplexed signal samples by lagrange interpolation or linear interpolation based on the base pointer and the converted fractional interval to correct timing errors on the sequence of multiplexed signal samples. Thus, one feedback loop processing is completed. After multiple times of feedback circulation processing, stable periodic variation is formed at fractional intervals, a clock synchronization loop is finally converged, clock synchronization of all subcarrier signals is achieved, and a synchronized subcarrier signal sampling sequence is output.
Based on the characteristic that each subcarrier clock in a digital subcarrier multiplexing system is homologous, timing error detection is only carried out on one path of target subcarrier signals in a multi-path subcarrier signal sampling sequence, and fractional intervals and basic pointers are calculated based on timing error information obtained by the timing error detection; determining conversion parameters of the fractional intervals based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional intervals according to the conversion parameters; interpolating the sequence of multiplexed signal samples based on the base pointer and the converted fractional interval to correct timing errors on the sequence of multiplexed signal samples. And circularly executing the steps, and after a plurality of feedback cycles, enabling the fraction interval to change from irregular at the beginning to form stable periodic change, and eliminating the timing error on the multiplex signal sampling sequence. Therefore, the embodiment of the invention corrects the timing error on the multiplex signal sampling sequence and completes the synchronization of all the subcarrier signal sampling sequences. Compared with the prior art, the clock synchronization is respectively carried out on each subcarrier signal sampling sequence, and the embodiment of the invention does not need to carry out the parallel operation of the multiple subcarrier signal sampling sequences, so that the required circuit area is smaller, the circuit complexity is reduced, and the algorithm complexity is reduced.
Referring to fig. 2, the present invention first performs Analog-to-Digital conversion on an Analog signal received by a coherent optical receiver of a DSCM system through an ADC (Analog-to-Digital Converter) to obtain a multiplexed signal sample sequence, completes IQ imbalance compensation and coarse frequency offset estimation at a receiving end on the multiplexed signal, then interpolates the multiplexed signal sample sequence including a plurality of subcarriers based on a fractional interval and a basic pointer through an interpolation filter, and then a subcarrier demultiplexer demultiplexes the interpolated multiplexed signal sample sequence to obtain a multi-subcarrier signal sample sequence. The embodiment of the invention takes a frequency domain algorithm as an example, firstly, a multiplexing signal sampling sequence is grouped and converted to a frequency domain through Fast Fourier Transform (FFT), subcarrier demultiplexing is carried out in the frequency domain, a plurality of subcarrier signal sampling sequences are obtained after subcarrier demultiplexing is carried out and dispersion compensation is carried out, a timing error detector arbitrarily selects a target subcarrier sampling sequence with dispersion compensation to carry out timing error detection, loop filtering is carried out on the timing error after the timing error is extracted through a loop filter to generate a control word, a basic pointer and fractional intervals are calculated through a numerical control oscillator according to the control word and are converted into the fractional intervals, lagrange cubic polynomial interpolation is carried out on the next group of multiplexing signal sampling values in the multiplexing signal sampling sequence to achieve the purpose of removing the timing error, a clock synchronization loop is formed, the timing frequency difference is continuously tracked, fed back and corrected according to the process cycle, and finally the fractional intervals form stable period change, so that clock synchronization of each subcarrier signal sampling sequence is realized. After the synchronous sampling sequence of each subcarrier signal sampling sequence is obtained, polarization demultiplexing, self-adaptive equalization, fine frequency offset estimation and phase offset compensation are respectively carried out on each path of subcarrier, and finally the service information bit of each path of subcarrier signal sampling sequence is recovered.
The performance or effect of the clock synchronization method in the digital subcarrier multiplexing system according to the embodiment of the present invention is verified through experiments 1 and 2.
The performance of the clock synchronization method in the digital subcarrier multiplexing system according to the embodiment of the present invention is compared with the performance of the method for performing clock synchronization on each subcarrier in the existing scheme by experiment 1. In experiment 1, a polarization multiplexing 16-QAM-DSCM system is used, 4 subcarriers with a symbol rate of 32gbaud are used, each subcarrier signal is shaped by Nyquist (Nyquist) filtering at a transmitting end, a roll-off coefficient is 0.1, adjacent subcarriers are not overlapped during multiplexing, and a spectrogram of a multiplexed signal is shown in fig. 3. In experiment 1, the line width of a laser is 100kHz, the frequency offset is 1.5GHz, and the timing frequency difference is 50ppm, and a simulation result of detecting a timing error by using a subcarrier 3 under the conventional single-mode optical fiber transmission condition of 20-40 spans (the span length is 80 km) shows that, as shown in fig. 4, compared with a method of respectively performing clock synchronization on each subcarrier in the existing scheme, the clock synchronization method in the digital subcarrier multiplexing system provided by the invention has the cost of a Q value lower than 0.1dB.
In experiment 2, a polarization multiplexing 16QAM-DSCM system is used, 8 subcarriers are provided in total, each channel of subcarrier signal is shaped by Nyquist filtering at the transmitting end, the roll-off coefficient is 0.1, adjacent subcarriers are also just not overlapped when subcarriers are multiplexed, the spectrogram of the multiplexed signal is shown in fig. 5, wherein the symbol rates of subcarrier 1, subcarrier 2, subcarrier 7 and subcarrier 8 are 8gbaud, the symbol rates of subcarrier 3 and subcarrier 6 are 16 gbaud, the symbol rates of subcarrier 4 and subcarrier 5 are 32gbaud, and the composite symbol rate of the multiplexed signal is 128 gbaud. In simulation, the line width of a laser is 100kHz, the frequency deviation is 1.5GHz, the timing frequency difference is 50ppm, and the simulation result of using the subcarrier 5 for timing error detection under the conventional single-mode optical fiber transmission condition of 20-40 spans (the span length is 80 kilometers) shows that, as shown in FIG. 6, compared with the method for respectively performing clock synchronization on each subcarrier in the existing scheme, the clock synchronization method in the digital subcarrier multiplexing system provided by the invention has the maximum Q value cost of 0.1dB.
Therefore, the clock synchronization method in the digital subcarrier multiplexing system only performs timing error detection and loop filtering on one path of subcarriers in the multiple subcarriers, and compared with the scheme that each subcarrier is respectively performed with clock synchronization in the existing scheme, the clock synchronization method provided by the invention has lower algorithm complexity and can reduce the circuit area required by realizing the clock synchronization DSP algorithm. As shown in fig. 7, starting from the number of subcarriers being greater than or equal to 2, the algorithm complexity of the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention is lower than that of the method in which each subcarrier is separately clock-synchronized in the existing scheme, and the greater the number of subcarriers is, the more obvious the advantage of the clock synchronization method provided by the present invention in the aspect of algorithm complexity is, and when the number of subcarriers reaches 8, the clock synchronization method in the digital subcarrier multiplexing system provided by the present invention can reduce the algorithm complexity by about 45%.
The clock synchronization device in the digital subcarrier multiplexing system provided by the present invention is described below, and the clock synchronization device in the digital subcarrier multiplexing system described below and the clock synchronization method in the digital subcarrier multiplexing system described above can be referred to correspondingly.
Referring to fig. 8, a clock synchronization apparatus in a digital subcarrier multiplexing system includes:
an interpolation module 201, configured to interpolate the sequence of multiplexed signal samples based on the basic pointer and the converted fractional interval;
a subcarrier demultiplexing module 202, configured to perform subcarrier demultiplexing on the multiplexed signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence;
the dispersion compensation module 203 is configured to perform dispersion compensation on the multiple subcarrier signal sampling sequences respectively;
a timing error detection module 204, configured to select one target subcarrier signal sampling sequence from the dispersion-compensated multiple subcarrier signal sampling sequences to perform timing error detection, so as to obtain timing error information;
a fractional interval and base pointer calculation module 205 for calculating a fractional interval and a base pointer based on the timing error information;
a fractionally spaced transform module 206, configured to determine a transform parameter of the fractionally spaced based on a symbol rate of each subcarrier signal sampling sequence, and transform the fractionally spaced according to the transform parameter; the conversion parameter is used for shortening the period of the fractional interval and keeping the amplitude unchanged;
and an operation control module 207, configured to perform parameter control on the subcarrier demultiplexing module, the dispersion compensation module, the timing error detection module, the fractional interval and basic pointer calculation module, the fractional interval conversion module, and the interpolation module.
The invention provides a clock synchronization method and a device in a digital subcarrier multiplexing system, which are based on the characteristic that clocks of subcarriers in the digital subcarrier multiplexing system are homologous, only perform timing error detection on one path of target subcarrier signal in a multi-path subcarrier signal sampling sequence, and then calculate a fractional interval and a basic pointer based on timing error information obtained by the timing error detection; determining conversion parameters of the fractional intervals based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional intervals according to the conversion parameters: shortening the period of the fraction interval by converting parameters and keeping the amplitude degree of the fraction interval unchanged; and interpolating the multiplex signal sampling sequence based on the basic pointer and the converted fractional interval, circularly executing the steps, and after a plurality of feedback cycles, enabling the fractional interval to form stable periodic change from irregular change at the beginning, and eliminating the timing error on the multiplex signal sampling sequence. Therefore, the embodiment of the invention corrects the timing error on the multiplex signal sampling sequence and completes the synchronization of all the subcarrier signal sampling sequences. Compared with the prior art, the clock synchronization is respectively carried out on each subcarrier signal sampling sequence, and the embodiment of the invention does not need to carry out the parallel operation of the multiple subcarrier signal sampling sequences, so that the required circuit area is smaller, the circuit complexity is reduced, and the algorithm complexity is reduced.
In one embodiment, said determining a transition parameter for said fractional interval based on a symbol rate of each of said sequences of subcarrier signal samples, said transitioning said fractional interval according to a transition parameter, comprises:
and determining the conversion parameter of the fractional interval based on the sum of the symbol rates of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter.
In one embodiment, said determining said fractionally spaced conversion parameters based on the sum of the symbol rates of each of said subcarrier signal sample sequences and the symbol rate of said target subcarrier signal sample sequence is determined by calculating the following formula:
wherein M represents a conversion parameter, R SCi Representing the symbol rate, R, of a sequence of samples i of a subcarrier signal SC_TED Representing the symbol rate, R, of a sample sequence of a target subcarrier signal SC +R SC +…+R SCi Indicating that after M is determined based on the sum of the symbol rates of the subcarrier signal sample sequences, the fractional interval period is shortened by M times, keeping the amplitude constant.
In one embodiment, the fractional interval and base pointer calculation module comprises:
the control word acquisition module is used for filtering the timing error information to output control words;
and the fractional interval and basic pointer acquisition module is used for calculating the fractional interval and the basic pointer based on the control word.
In one embodiment, the interpolation module is specifically configured to perform polynomial interpolation on the sequence of multiplexed signal samples by lagrange interpolation or linear interpolation based on the base pointer and the converted fractional interval to correct a timing error on the sequence of multiplexed signal samples.
Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment may be implemented by software plus a necessary hardware platform, and may also be implemented by hardware.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. A method for clock synchronization in a digital subcarrier multiplexing system, comprising:
interpolating a sequence of multiplexed signal samples comprising a plurality of subcarriers based on fractional intervals and a base pointer;
carrying out subcarrier demultiplexing on the multiplexing signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence;
respectively carrying out dispersion compensation on the multi-channel subcarrier signal sampling sequences;
selecting one path of target subcarrier signal sampling sequence from the multipath subcarrier signal sampling sequences after dispersion compensation to carry out timing error detection to obtain timing error information;
calculating a fractional interval and a base pointer based on the timing error information;
determining conversion parameters of the fractional intervals based on the symbol rate of each subcarrier signal sampling sequence, and converting the fractional intervals according to the conversion parameters; the conversion parameter is used for shortening the period of the fractional interval and keeping the amplitude unchanged;
and interpolating the multiplex signal sampling sequence based on the basic pointer and the converted fractional interval, so as to complete a feedback cycle, and eliminating the timing error of the multiplex signal sampling sequence after a plurality of feedback cycles.
2. The method of claim 1, wherein said determining the fractionally spaced transition parameters based on the symbol rate of each of said sequences of subcarrier signal samples, and wherein said fractionally spaced transitions according to the transition parameters comprises:
and determining the conversion parameter of the fractional interval based on the sum of the symbol rates of the subcarrier signal sampling sequences and the symbol rate of the target subcarrier signal sampling sequence, and converting the fractional interval according to the conversion parameter.
3. The method of claim 2, wherein said determining said fractionally spaced transition parameters based on a sum of symbol rates of said respective subcarrier signal sample sequences and a symbol rate of said target subcarrier signal sample sequence is determined by calculating according to the following formula:
wherein M represents a conversion parameter, R SCi Representing the symbol rate, R, of a sequence of samples i of a subcarrier signal SC_TED Representing the symbol rate, R, of a sample sequence of a target subcarrier signal SC1 +R SC +…+R SCi Indicating that after M is determined based on the sum of the symbol rates of the subcarrier signal sample sequences, the period of the fractional interval is shortened by M times, keeping the amplitude constant.
4. The method of clock synchronization in a digital subcarrier multiplexing system of claim 1, wherein the calculating fractional intervals and base pointers based on the timing error information comprises:
filtering the timing error information to output a control word;
a fractional interval and a base pointer are calculated based on the control word.
5. The method of claim 1, wherein the interpolating the sequence of multiplexed signal samples based on the base pointer and the converted fractional interval comprises:
performing polynomial interpolation on the sequence of multiplexed signal samples by Lagrange interpolation or linear interpolation to correct timing errors on the sequence of multiplexed signal samples based on the base pointers and the converted fractional intervals.
6. A clock synchronization apparatus in a digital subcarrier multiplexing system, comprising:
an interpolation module for interpolating the sequence of multiplexed signal samples based on the base pointer and the converted fractional interval;
the subcarrier demultiplexing module is used for carrying out subcarrier demultiplexing on the multiplexing signal sampling sequence to obtain a multi-channel subcarrier signal sampling sequence;
the dispersion compensation module is used for carrying out dispersion compensation on the multi-channel subcarrier signal sampling sequence;
a timing error detection module, configured to select one target subcarrier signal sampling sequence from the dispersion-compensated multiple subcarrier signal sampling sequences to perform timing error detection, so as to obtain timing error information;
a fractional interval and base pointer calculation module for calculating a fractional interval and a base pointer based on the timing error information;
a fractional interval conversion module, configured to determine a conversion parameter of the fractional interval based on a symbol rate of each subcarrier signal sampling sequence, and convert the fractional interval according to the conversion parameter; the conversion parameter is used for shortening the period of the fractional interval and keeping the amplitude of the fractional interval unchanged;
and the operation control module is used for carrying out parameter control on the subcarrier demultiplexing module, the dispersion compensation module, the timing error detection module, the fractional interval and basic pointer calculation module, the fractional interval conversion module and the interpolation module.
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